JPH0312467B2 - - Google Patents
Info
- Publication number
- JPH0312467B2 JPH0312467B2 JP9068382A JP9068382A JPH0312467B2 JP H0312467 B2 JPH0312467 B2 JP H0312467B2 JP 9068382 A JP9068382 A JP 9068382A JP 9068382 A JP9068382 A JP 9068382A JP H0312467 B2 JPH0312467 B2 JP H0312467B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- transparent body
- resin
- bonding
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 41
- 239000011347 resin Substances 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 description 12
- 239000012780 transparent material Substances 0.000 description 8
- 238000000465 moulding Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000000428 dust Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000035939 shock Effects 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は樹脂封止型半導体装置およびその製造
方法に係り、特に紫外線消去型の樹脂封止型EP
−ROMの製造およびその製造方法に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a resin-sealed semiconductor device and a method for manufacturing the same, and particularly relates to an ultraviolet erasable resin-sealed EP.
-Relating to ROM manufacturing and its manufacturing method.
(b) 技術の背景
近時情報処理装置等に於いて、紫外線消去型の
EP−ROM（消去、書き込み可能な半導体記憶装
置）が多く用いられる。(b) Background of technology Recently, in information processing equipment, ultraviolet erasing type
EP-ROM (erasable/writable semiconductor memory device) is often used.
(c) 従来技術と問題点
従来EP−ROMは、第１図に示すようにセラミ
ツク・ケースを用いて構成されていた。(c) Prior art and problems Conventional EP-ROMs were constructed using a ceramic case as shown in FIG.
即ち従来はEP−ROMチツプ１がセラミツク・
ケース内に配設され、セラミツク・ケース２上に
ガラス窓３を有する金属蓋（又はセラミツク蓋）
４がろう材（又は低融点ガラス）５によつて気密
に封着された構造となつていた。なお同図に於
て、６はチツプ・ステージ、７は内部配線、８は
外部リード、９はボンデイング・ワイヤ、１０は
ボンデイング・パツド、１１は金・シリコン
（Au−Si）合金、１２はメタライズ部を示してい
る。 That is, conventionally, EP-ROM chip 1 was made of ceramic.
A metal lid (or ceramic lid) disposed inside the case and having a glass window 3 on the ceramic case 2
4 was hermetically sealed with a brazing material (or low melting point glass) 5. In the figure, 6 is a chip stage, 7 is an internal wiring, 8 is an external lead, 9 is a bonding wire, 10 is a bonding pad, 11 is a gold-silicon (Au-Si) alloy, and 12 is a metallization. It shows the part.
しかし従来のEP−ROMは上記のようにセラミ
ツク・ケース２を用いるために製造工程が複雑に
なり、且つ材料費も高価なので製造原価が高くな
るという問題があつた。 However, as mentioned above, the conventional EP-ROM uses the ceramic case 2, which complicates the manufacturing process, and the material costs are also high, resulting in a high manufacturing cost.
又従来の構造に於いてはガラス窓３とEP−
ROMチツプ２の表面との間に空間部を有するた
め、ガラス窓３の内面に静電気等によりごみ、汚
染物質等が被着し、ガラス窓３の透光性が損なわ
れて、長期間使用していると情報の消去が困難に
なつてくるという問題もあつた。 Also, in the conventional structure, glass window 3 and EP-
Since there is a space between the surface of the ROM chip 2 and the surface of the glass window 3, dust, contaminants, etc. may adhere to the inner surface of the glass window 3 due to static electricity, and the translucency of the glass window 3 may be impaired. There was also the problem that it became difficult to erase information when
(c) 発明の目的
上記の問題点を解決するものとして、リードフ
レームに搭載したチツプの表面上に紫外線透過材
を接着して樹脂成形した例が、特開昭57−42152
号公報に記載されている。(c) Purpose of the Invention In order to solve the above-mentioned problems, an example in which an ultraviolet transmitting material is bonded onto the surface of a chip mounted on a lead frame and resin molded is disclosed in Japanese Patent Application Laid-Open No. 57-42152.
It is stated in the No.
しかしながら、この例では、紫外線透過材の上
面にテープ材料を付着した状態でモールド型に入
れ、樹脂封止した後、テープ材料を剥がすことで
その上に付着した樹脂を除去している。そのた
め、紫外線透過材の上面が成形された樹脂の上面
より内側に凹んでしまう欠点がある。それに伴
い、凹んだ紫外線封止材の上面にごみが付着し消
去用の紫外線が透過せず、メモリの消去ができな
くなる。またかかる公知例においてはチツプ取付
部とリードは同一平面上に位置するためチツプ取
付部上に載置されているチツプとリード間には段
差が生じ、ボンデイングワイヤはかかる段差間を
介するため水平に接続することは出来ず、ワイヤ
内の応力は均一ではなく特にワイヤとチツプ端子
との接続部に集中応力が生ずるため、モールド材
料が凝固の際その収縮力でワイヤが損傷を受け易
く、かつチツプ取付部とリード間の距離は短いた
めその間に介在するモールド部材は半導体装置が
熱シヨツクを受けた場合クラツクを生ずることに
なる。 However, in this example, the ultraviolet transmitting material is placed in a mold with the tape material attached to its upper surface, sealed with resin, and then the tape material is peeled off to remove the resin attached thereon. Therefore, there is a drawback that the top surface of the ultraviolet transmitting material is recessed inward from the top surface of the molded resin. As a result, dust adheres to the top surface of the recessed ultraviolet encapsulant, preventing ultraviolet rays for erasing from passing through, making it impossible to erase the memory. In addition, in such a known example, since the chip mounting part and the leads are located on the same plane, a step is created between the chip placed on the chip mounting part and the leads, and the bonding wire is passed between the steps, so that it is not horizontal. The stress within the wire is not uniform, and concentrated stress occurs particularly at the connection between the wire and the chip terminal. When the mold material solidifies, the wire is easily damaged by the shrinkage force, and the chip Since the distance between the mounting portion and the lead is short, the molding member interposed therebetween will cause cracks when the semiconductor device receives a thermal shock.
本発明は樹脂封止型半導体装置特に紫外線消去
型の樹脂封止型EP−ROMにおいてこれらの問題
点を解決し透光体の上面へのごみ等の付着、チツ
プステージとリード間の樹脂のクラツクの発生及
び封止用樹脂の収縮の際のボンデイングワイヤの
損傷等を防止しうる構造を目的とする。 The present invention solves these problems in a resin-sealed semiconductor device, particularly an ultraviolet-erasable resin-sealed EP-ROM, and prevents dust from adhering to the upper surface of the transparent body and cracks in the resin between the chip stage and the leads. The object of the present invention is to provide a structure that can prevent damage to the bonding wire when the sealing resin shrinks.
(e) 発明の構成
即ち本発明は、
チツプステージと、
該チツプステージの周辺であつて、該チツプス
テージより高い位置に設けられた複数のリード
と、該チツプステージ上に搭載されたリード表面
と略同一平面に配置されたチツプと、
該チツプ上のボンデイングパツドと前記リード
とを略水平に接続するボンデイングワイヤと、
該チツプの表面上に固着され、所定の高さを有
する透光体と、
該チツプステージ、チツプ、リードの内側部
分、ボンデイングワイヤ、及び該透光体とを埋め
込むよう設けられた成形樹脂とを有し、
前記透光体の上面が該成形樹脂の外部に露出さ
れ、該成形樹脂の上面と該透光体の上面とが同一
平面になつていることを特徴とする樹脂封止型半
導体装置であり、さらに、
チツプステージと、該チツプステージの周辺に
設けられた複数のリードとが一体形成されている
リードフレームの、前記チツプステージ上にチツ
プをボンデイングし続いてチツプ上のボンデイン
グパツドとリードの内部方向先端部とをボンデイ
ングワイヤで接続する工程と、
上面と下面を有し所定の高さを有する透光体の
該下面を該チツプの表面上に接着する工程と、
該透光体とチツプとを搭載したリードフレーム
を、モールド上型が該透光体の上面に接し、直接
透光体を押し下げることにより該チツプステージ
が押し下げられ、チツプ表面とリード表面とが略
同一平面となり、ボンデイングワイヤも略水平と
なる様にして、モールド型に搭載して、樹脂成形
を行う工程とを有し、
前記透光体の上面か該成形樹脂の外部に露出さ
れ、該成形樹脂の上面と該透光体の上面とが同一
平面になる様形成されることを特徴とする樹脂封
止型半導体装置の製造方法である。(e) Structure of the invention In other words, the present invention comprises a chip stage, a plurality of leads provided around the chip stage at a higher position than the chip stage, and a lead surface mounted on the chip stage. A chip disposed substantially on the same plane; a bonding wire connecting bonding pads on the chip and the leads substantially horizontally; and a transparent body fixed on the surface of the chip and having a predetermined height. , a molded resin provided to embed the chip stage, the chip, the inner portion of the lead, the bonding wire, and the transparent body, the upper surface of the transparent body being exposed to the outside of the molded resin, A resin-sealed semiconductor device characterized in that the upper surface of the molded resin and the upper surface of the transparent body are on the same plane, and further comprising a chip stage and a plurality of semiconductor devices provided around the chip stage. bonding the chip onto the chip stage of the lead frame integrally formed with the leads, and then connecting the bonding pad on the chip and the inward tip of the lead with a bonding wire; bonding the lower surface of the transparent body having a predetermined height onto the surface of the chip; The chip stage is pushed down by directly pushing down the transparent body that is in contact with the top surface, so that the chip surface and the lead surface are approximately on the same plane, and the bonding wire is also approximately horizontal. The method is characterized in that the upper surface of the transparent body is exposed to the outside of the molded resin, and the upper surface of the molded resin and the upper surface of the transparent body are formed on the same plane. This is a method for manufacturing a resin-sealed semiconductor device.
上記の構造または製造方法のため、透光体の上
面と成形樹脂の上面とが同一平面上に形成され、
透光体の上面にごみが付着することはなくなる。
また一般に樹脂成形のあと、樹脂は収縮するが透
光体として特に紫外線の透過特性のよい石英ガラ
スを使用する場合、透光体は殆ど収縮せず、さら
にかかる透光体とかチツプの如き熱伝導性の小な
る部分の周囲の樹脂は凝固は緩やかであるが、分
子間の結合は強固となり、一方リード等熱伝導性
のよい部分の周囲の樹脂は、凝固は速いが分子間
結合は弱くなつており、従つてとくに透光体とし
て石英ガラスを使用し、しかもその占める体積が
大となつている場合成形樹脂内での残留応力は極
めて不均一となつており、このような状態で熱シ
ヨツク（例えば−50〜＋150℃の範囲）による熱
ストレスが生ずると樹脂内にクラツクを生じ易
く、特にチツプステージとリード間の樹脂にクラ
ツクが生じ耐湿性低下の原因となる。 Due to the above structure or manufacturing method, the upper surface of the transparent body and the upper surface of the molded resin are formed on the same plane,
Dust will no longer adhere to the upper surface of the transparent body.
Generally, after resin molding, the resin shrinks, but when quartz glass, which has particularly good UV transmission characteristics, is used as a transparent material, the transparent material hardly shrinks, and furthermore, such a transparent material or a heat conductive material such as a chip can be used as a transparent material. The resin around areas with low thermal conductivity solidifies slowly, but the intermolecular bonds become strong, while the resin around areas with good thermal conductivity, such as leads, solidifies quickly but the intermolecular bonds become weak. Therefore, especially when quartz glass is used as a transparent material and the volume occupied by it is large, the residual stress within the molded resin becomes extremely non-uniform, and in such a state thermal shock When thermal stress occurs (for example, in the range of -50 to +150°C), cracks are likely to occur in the resin, particularly in the resin between the chip stage and the leads, causing a decrease in moisture resistance.
しかしながら本発明では、リードはチツプステ
ージより高い位置となつているので、同一平面に
ある場合よりチツプステージとリード間の距離が
大となり、熱シヨツクを受けた場合でもクラツク
を生ずることは少なく、十分な耐湿性を維持する
ことが可能となる。 However, in the present invention, since the leads are located at a higher position than the chip stage, the distance between the chip stage and the leads is larger than when they are on the same plane, and even when subjected to heat shock, cracks are less likely to occur. It is possible to maintain moisture resistance.
さらにチツプステージとリード間に高さの差が
あることは、チツプステージ上に載置されている
チツプの電極としてのボンデイングパツド面とリ
ード面とは略水平となり、またボンデイングワイ
ヤの接続部での集中応力も避けられ樹脂の収縮力
によるワイヤの損傷は著るしく減少される。 Furthermore, the difference in height between the chip stage and the leads means that the surface of the bonding pad, which serves as an electrode for the chip placed on the chip stage, and the surface of the leads are approximately horizontal, and the connection part of the bonding wire is concentrated stresses are also avoided, and damage to the wire due to resin shrinkage forces is significantly reduced.
(f) 発明の実施例
以下本発明を一実施例について、第２図に示す
樹脂封止完成体の上面図イ及びＡ−A′矢視断面
図ロ、第３図に示す組立完成体の上面図イ及びＡ
−A′矢視断面図ロを用いて詳細に説明する。(f) Embodiment of the Invention The present invention will now be described as an embodiment of the present invention. Top view A and A
This will be explained in detail using sectional view B as seen from the −A′ arrow.
本発明を適用した樹脂封止型EP−ROMは、例
えは第２図イ及びロに示すように、金属製のチツ
プ・ステージ２１上にEP−ROMチツプ２２が金
（Au）・シリコン（Si）等の合金層２３によりろ
う付け搭載されており、該EP−ROMチツプ２２
のボンデイング・パツド２４と金属リード２５と
の間は通常のワイヤ・ボンデイング手段により
Auあるいはアルミニウム（Al）等のボンデイン
グワイヤ即ち細線２６により接続されている。 In the resin-sealed EP-ROM to which the present invention is applied, for example, as shown in FIGS. ) etc., and is mounted by brazing with an alloy layer 23 such as EP-ROM chip 22.
The bonding pad 24 and the metal lead 25 are bonded by ordinary wire bonding means.
The connection is made by a bonding wire, that is, a thin wire 26 made of Au or aluminum (Al).
そして、EP−ROMチツプ２２の少なくともセ
ル領域２７、即ち通常積層ゲートMOSトランジ
スタ等からなる複数のメモリセル・トランジスタ
とそれ等を接続する回路配線の形成された領域上
に、石英ガラス等からなる紫外線の透光体２８
が、固着されている。 Then, ultraviolet rays made of quartz glass or the like are applied to at least the cell region 27 of the EP-ROM chip 22, that is, the region where a plurality of memory cells and transistors usually made of stacked gate MOS transistors and circuit wiring connecting them are formed. transparent body 28
However, it is fixed.
そして上記構造を有する組立完成体が、トラン
スフアーモールド等の手段によりエポキシ樹脂或
いはシリコン樹脂等からなる樹脂ケース３０中に
前記透光体２８の上面が成形樹脂の上面と同一平
面となるように露出し、且つ通常通り金属リード
２５が外部に導出された状態で埋込まれるように
して構成されている。 The completed assembly having the above structure is exposed in a resin case 30 made of epoxy resin, silicone resin, etc. by means such as transfer molding so that the upper surface of the transparent body 28 is flush with the upper surface of the molded resin. However, as usual, the metal lead 25 is embedded in a state led out to the outside.
次に上記樹脂封止型EP−ROMの形成方法を述
べる。 Next, a method for forming the resin-sealed EP-ROM will be described.
第３図は本発明の構造を有するEP−ROMの樹
脂モールドを行う前の状態、即ち組立完成体の上
面構造イ及びＡ−A′断面構造ロを示したもので
ある。 FIG. 3 shows the state before resin molding of the EP-ROM having the structure of the present invention, that is, the top structure (a) and the A-A' cross-sectional structure (b) of the assembled completed body.
該EP−ROMを形成するには、コバール材等か
らなりチツプ・ステージ及びワイヤ・ボンデイン
グ領域等に例えばAuめつきが施された通常のリ
ード・フレームLFのチツプ・ステージ２１上に、
通常のダイ・ボンデイング手段によりEP−ROM
チツプ２２をボンデイングする。図中２３はこの
際形成されたAuSi合金層を示す。 To form the EP-ROM, a chip stage 21 of a normal lead frame LF made of Kovar material or the like is plated with gold on the chip stage and wire bonding area, etc.
EP-ROM can be manufactured using conventional die bonding means.
Bond the chip 22. In the figure, 23 indicates the AuSi alloy layer formed at this time.
次いで通常のワイヤ・ボンデイング手段により
EP−ROMチツプ２２のボンデイング・パツド２
４とリード・フレームLFに於けるリード２５の
内部方向先端部とをAu或いはAl等の細線２６で
接続する。 Then by conventional wire bonding means
EP-ROM chip 22 bonding pad 2
4 and the inward end of the lead 25 in the lead frame LF are connected by a thin wire 26 made of Au or Al.
次いで該EP−ROMチツプ２２の少なくともメ
モリセル領域２７を覆う所定の大きさを有し、紫
外線をよく透過する例えば石英ガラス等の透光体
２８を、メモリセル領域上に接着剤２９で接着す
るが、この場合透光体の高さは、モールド成形に
際しモールド上型が直接に透光体上面に接し、モ
ールド上型が透光体２８及びROMチツプ２２を
介してチツプステージ２１を押し下げ、チツプ表
面とリード表面とが略同一平面となり、ボンデイ
ングワイヤも略水平となるように選ばれている。
なお上記接着材としては、電導性を有する不純物
や活性不純物を含まないこと、200（℃）以上の耐
熱性を有すること、熱硬化性であること、高い透
明度を有すること、塗布が容易であること、モー
ルド時にガスを発生しないこと等が必要な条件で
あり、この様な接着材は低粘度のエポキシ樹脂及
びシリコーン樹脂から選ぶことができる。又接着
材２９の厚さは可能な限り薄い方が良い。 Next, a transparent material 28, such as quartz glass, which has a predetermined size that covers at least the memory cell area 27 of the EP-ROM chip 22 and is highly transparent to ultraviolet rays, is adhered onto the memory cell area with an adhesive 29. However, in this case, the height of the transparent body is such that during molding, the upper mold directly contacts the upper surface of the transparent body, and the upper mold presses down the chip stage 21 via the transparent body 28 and the ROM chip 22, and the chip The surface is selected so that the surface and the lead surface are substantially coplanar, and the bonding wire is also substantially horizontal.
The adhesive mentioned above must not contain conductive impurities or active impurities, have heat resistance of 200 (℃) or higher, be thermosetting, have high transparency, and be easy to apply. The necessary conditions include not generating gas during molding, and such an adhesive can be selected from low-viscosity epoxy resins and silicone resins. Further, it is preferable that the thickness of the adhesive material 29 be as thin as possible.
次いで180（℃）以上の温度で接着材２９をキユ
アーしてチツプ２２上に透光体２８を固着させ
る。 Next, the transparent material 28 is fixed onto the chip 22 by curing the adhesive 29 at a temperature of 180 (° C.) or higher.
次いで上記組立完成体が形成されたリード・フ
レームFLを従来のモールド型に搭載し、従来と
同様エポキシ等のモールド樹脂を用い150−180
（℃）程度の温度で樹脂成形を行い、次いで150−
180（℃）程度の温度でモールド樹脂のキユアーを
行つて、第２図に示すように前記の組立完成体を
有する所望の領域を樹脂ケース３０中に埋込む。 Next, the lead frame FL with the completed assembly described above is mounted in a conventional mold, and molded with 150-180 mm using molding resin such as epoxy as in the conventional method.
Resin molding is performed at a temperature of about (℃), then 150-
The mold resin is cured at a temperature of about 180 (° C.), and the desired area containing the completed assembly is embedded in the resin case 30 as shown in FIG.
なおこの際前述したように樹脂ケース３０の上
面には透光体２８の上面が表出する。又透光体２
８の上面にはモールド樹脂のばりが薄く被着する
場合もある。この場合例えばサンド・プラスト等
の方法により透光体２８上面の樹脂ばりを完全に
除去する。この際透光体２８の上面にきずがつく
こともあるが、このきずは紫外線の透過線に大き
な影響を与えない。 At this time, as described above, the upper surface of the transparent body 28 is exposed on the upper surface of the resin case 30. Translucent body 2
In some cases, a thin layer of mold resin burrs may adhere to the upper surface of 8. In this case, the resin burrs on the upper surface of the transparent body 28 are completely removed by a method such as sand blasting. At this time, scratches may be formed on the upper surface of the transparent body 28, but these scratches do not significantly affect the transmitted light of ultraviolet rays.
次いで通常通りリード切断、リード折曲げ、外
装めつき等を行つて第２図に示すような樹脂封止
型EP−ROMを形成する。 Next, lead cutting, lead bending, exterior plating, etc. are performed as usual to form a resin-sealed EP-ROM as shown in FIG.
(g) 発明の効果
以上説明したように本発明によれば紫外線消去
型のEP−ROMを量産性に優れ、且つ材料費の安
い樹脂封止構造で形成することができる。従つて
EP−ROMを安価に提供することができる。(g) Effects of the Invention As explained above, according to the present invention, an ultraviolet-erasable EP-ROM can be formed with a resin-sealed structure that is excellent in mass production and has low material costs. accordingly
EP-ROM can be provided at low cost.
又本発明によれば紫外線消去型EP−ROMの透
光窓とメモリセル領域の間に中空部が存在しない
ので、長時間使用しても透光窓の内面が汚染され
ることがない。従つてEP−ROMの信頼性が向上
する。 Further, according to the present invention, since there is no hollow space between the light-transmitting window and the memory cell area of the ultraviolet-erasable EP-ROM, the inner surface of the light-transmitting window will not be contaminated even after long-term use. Therefore, the reliability of EP-ROM is improved.
さらに、本発明によれば、透光体の上面が成形
樹脂の上面と同一面に形成されるので、透光体の
上面にごみが付着することはない。そして、本発
明の製造方法によれば、リードフレームの弾力性
を利用して透光体の上面がモールド上型で押し下
げるようにしているので、透光体の上面に樹脂が
付着することはほとんどなく、またチツプステー
ジとリード間に介在する樹脂は半導体装置の熱シ
ヨツクによる場合でもクラツクを生せず、チツプ
とリード間のボンデイングワイヤも樹脂の収縮力
によつて損傷を受けることは少なくなる。 Further, according to the present invention, since the upper surface of the transparent body is formed on the same plane as the upper surface of the molded resin, dust does not adhere to the upper surface of the transparent body. According to the manufacturing method of the present invention, the upper surface of the transparent body is pressed down by the upper mold by utilizing the elasticity of the lead frame, so that it is almost impossible for resin to adhere to the top surface of the transparent body. Moreover, the resin interposed between the chip stage and the leads does not cause cracks even when subjected to thermal shock of the semiconductor device, and the bonding wires between the chip and the leads are less likely to be damaged by the shrinkage force of the resin.
第１図は従来のEP−ROMの断面図、第２図は
本発明のEP−ROMに於ける樹脂封止完成体の上
面図イ及びＡ−A′矢視断面図ロ、第３図は本発
明のEP−ROMに於ける組立完成体の上面図イ及
びＡ−A′矢視断面図ロである。
図面に於て、２１はチツプ・ステージ、２２は
EP−ROMチツプ、２３は合金層、２４はボンデ
イング・パツド、２５は金属リード、２６は細
線、２７は領域、２８は透光体、２９は接着材、
３０は樹脂ケース、LFはリード・フレームを示
す。
Fig. 1 is a cross-sectional view of a conventional EP-ROM, Fig. 2 is a top view of a resin-sealed completed EP-ROM of the present invention, and a cross-sectional view taken along the line A-A'. FIG. 1 is a top view of a completed assembly of the EP-ROM of the present invention, and FIG. In the drawing, 21 is the chip stage and 22 is the chip stage.
EP-ROM chip, 23 is an alloy layer, 24 is a bonding pad, 25 is a metal lead, 26 is a thin wire, 27 is a region, 28 is a transparent material, 29 is an adhesive material,
30 is a resin case, and LF is a lead frame.
Claims (1)
テージより高い位置に設けられた複数のリード
と、 該チツプステージ上に搭載され、リード表面と
略同一平面に配置されたチツプと、 該チツプ上のボンデイングパツドと前記リード
とを略水平に接続するボンデイングワイヤと、 該チツプの表面上に固着され、所定の高さを有
する透光体と、 該チツプステージ、チツプ、リードの内側部
分、ボンデイングワイヤ、及び該透光体とを埋め
込むよう設けられた成形樹脂とを有し、 前記透光体の上面が該成形樹脂の外部に露出さ
れ、該成形樹脂の上面と該透光体の上面とが同一
平面になつていることを特徴とする樹脂封止型半
導体装置。 ２ チツプステージと、該チツプステージの周辺
に設けられた複数のリードとが一体形成されてな
るリードフレームの、前記チツプステージ上にチ
ツプをボンデイングし、続いてチツプ上のボンデ
イングパツドとリードの内部方向先端部とをボン
デイングワイヤで接続する工程と 上面と下面を有し所定の高さを有する透光体の
該下面を該チツプの表面上に接着する工程と、 該透光体とチツプとを搭載したリードフレーム
を、モールド上型が該透光体の上面に接し、直接
透光体を押し下げることにより該チツプステージ
が押し下げられ、チツプ表面とリード表面とが略
同一平面となり、ボンデイングワイヤも略水平と
なる様にして、モールド型に搭載して、樹脂成形
を行う工程とを有し、 前記透光体の上面が該成形樹脂の外部に露出さ
れ、該成形樹脂の上面と該透光体の上面とが同一
平面になる様形成されることを特徴とする樹脂封
止型半導体装置の製造方法。[Scope of Claims] 1. A chip stage, a plurality of leads provided around the chip stage at a higher position than the chip stage, and a plurality of leads mounted on the chip stage and substantially flush with the lead surface. a bonding wire connecting the bonding pads on the chip and the leads substantially horizontally; a transparent body fixed on the surface of the chip and having a predetermined height; and the chip stage. , a chip, an inner portion of the lead, a bonding wire, and a molded resin provided to embed the transparent body, the upper surface of the transparent body being exposed to the outside of the molded resin, and the molded resin A resin-sealed semiconductor device characterized in that a top surface and a top surface of the transparent body are on the same plane. 2 Bonding a chip onto the chip stage of a lead frame that is integrally formed with a chip stage and a plurality of leads provided around the chip stage, and then bonding the bonding pads on the chip and the inside of the leads. a step of connecting the directional tip portion with a bonding wire; a step of bonding the lower surface of the transparent body having an upper surface and a lower surface and having a predetermined height onto the surface of the chip; and a step of connecting the transparent body and the chip. The chip stage is pushed down by directly pushing down the transparent body with the mounted lead frame in contact with the upper surface of the transparent body, and the chip surface and the lead surface are approximately on the same plane, and the bonding wire is also approximately on the same plane. The transparent body is mounted horizontally in a mold and molded with resin, and the upper surface of the transparent body is exposed to the outside of the molded resin, and the upper surface of the molded resin and the transparent body are 1. A method for manufacturing a resin-sealed semiconductor device, characterized in that the semiconductor device is formed so that the top surface of the semiconductor device is flush with the top surface of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57090683A JPS58207656A (en) | 1982-05-28 | 1982-05-28 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57090683A JPS58207656A (en) | 1982-05-28 | 1982-05-28 | Resin-sealed type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58207656A JPS58207656A (en) | 1983-12-03 |
| JPH0312467B2 true JPH0312467B2 (en) | 1991-02-20 |
Family
ID=14005325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57090683A Granted JPS58207656A (en) | 1982-05-28 | 1982-05-28 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58207656A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6150353A (en) * | 1984-08-20 | 1986-03-12 | Oki Electric Ind Co Ltd | Eprom device |
| JPS6150351A (en) * | 1984-08-20 | 1986-03-12 | Oki Electric Ind Co Ltd | Eprom device |
| JPS625367U (en) * | 1985-03-16 | 1987-01-13 | ||
| JPS61188871U (en) * | 1985-05-16 | 1986-11-25 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5541748A (en) * | 1978-09-18 | 1980-03-24 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS5742152A (en) * | 1980-08-27 | 1982-03-09 | Nec Corp | Resin sealed type semiconductor and manufacture thereof |
-
1982
- 1982-05-28 JP JP57090683A patent/JPS58207656A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5541748A (en) * | 1978-09-18 | 1980-03-24 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS5742152A (en) * | 1980-08-27 | 1982-03-09 | Nec Corp | Resin sealed type semiconductor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58207656A (en) | 1983-12-03 |
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