JPH0311641A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0311641A JPH0311641A JP1145789A JP14578989A JPH0311641A JP H0311641 A JPH0311641 A JP H0311641A JP 1145789 A JP1145789 A JP 1145789A JP 14578989 A JP14578989 A JP 14578989A JP H0311641 A JPH0311641 A JP H0311641A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- base film
- semiconductor device
- resin
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 14
- 238000010292 electrical insulation Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 abstract description 14
- 229920005989 resin Polymers 0.000 abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011889 copper foil Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は樹脂封止してなる半導体装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device sealed with resin.
（従来の技術および解決しようとする課題）半導体チッ
プの高集積化および大型化にともない、半導体装置用パ
ッケージは、より多ビンのものが要求されている。この
ため、たとえば、リードフレームなどもリードの配置密
度がますます高くなっている。しかしながら、リードフ
レームでは用いる金属板材の板厚程度までしかリード間
隔を狭くできないという限界がある。(Prior Art and Problems to Be Solved) As semiconductor chips become more highly integrated and larger, packages for semiconductor devices are required to have a larger number of bins. For this reason, for example, the arrangement density of leads in lead frames and the like is becoming higher and higher. However, the lead frame has a limit in that the lead spacing can only be narrowed to the thickness of the metal plate material used.
これに対し、より多数本のリードを高密度で形成し得る
ものとしてＴＡＢ用テープが提供されている。このＴＡ
Ｂ用テープは電気的絶縁性を有するベースフィルム上に
導体回路を形成するので。In contrast, TAB tapes have been provided as tapes that can form a larger number of leads at a higher density. This TA
B tape forms a conductor circuit on a base film that has electrical insulation properties.
板厚が薄い導体回路であってもベースフィルムで支持さ
れることによって、リードフレームとくらべると、かな
り微細で高密度な導体回路を形成することができるもの
である。Even if the conductor circuit is thin, by being supported by the base film, it is possible to form a conductor circuit that is considerably finer and denser than a lead frame.
このＴＡＢ用テープは通常、チップに一括してリードを
ボンディングするようにして用いられるのであるが、リ
ードパターンがきわめて微細であるために、チップとイ
ンナーリードを的確にボンディングすることが技術的に
難しく、また、ボンディング後に樹脂封止する１−ラン
スファモールドの技術も難しいという問題点がある。This TAB tape is usually used to bond the leads to the chip all at once, but because the lead pattern is extremely fine, it is technically difficult to bond the chip and the inner leads accurately. Furthermore, there is a problem in that the 1-transfer molding technique for resin sealing after bonding is difficult.
そこで、本発明は上記問題点に鑑みてなされたものであ
り、その目的とするところは、チップとインナーリード
とのボンディングが容易にでき、ボンディング後の樹脂
封止も容易にできる半導体装置を提供するにある。The present invention has been made in view of the above problems, and its purpose is to provide a semiconductor device in which bonding between a chip and an inner lead can be easily performed, and resin sealing after bonding can also be easily performed. There is something to do.
（課題を解決するための手段） 本発明は上記目的を達成するため次の構成をそなえる。(Means for solving problems) The present invention has the following configuration to achieve the above object.
すなわち、電気的絶縁性を有するベースフィルム上に導
体回路を形成し、該導体回路が形成された側のベースフ
ィルム面上にチップを搭載し、チップと導体回路とをワ
イヤボンディングし、チップが搭載された側のベースフ
ィルム片面上でチップを樹脂封止して成ることを特徴と
すする。また、前記チップが搭載された面の反対側の面
に放熱体を接合したことを特徴とする。That is, a conductor circuit is formed on a base film having electrical insulation properties, a chip is mounted on the side of the base film on which the conductor circuit is formed, the chip and the conductor circuit are wire-bonded, and the chip is mounted. The chip is resin-sealed on one side of the base film. Further, a heat sink is bonded to the surface opposite to the surface on which the chip is mounted.
（作用）
導体回路はテープのペースフィルＡ ｌに形成する。こ
れによってより高密度に導体回路が形成できる。チップ
をベースフィルムに接合した後、導体回路との間をワイ
ヤボンディングし、ベースフィルム片面側」二でチップ
を樹脂封止する。(Function) The conductor circuit is formed on the tape's paste fill A1. This allows a conductor circuit to be formed with higher density. After bonding the chip to the base film, wire bonding is performed between the chip and the conductor circuit, and the chip is sealed with resin on one side of the base film.
（実施例）
以下本発明の好適な実施例を添付図面に基づいて詳細に
説明する。(Embodiments) Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
第１図は本発明の半導体装置に用いるテープの一実施例
を示す説明図である。FIG. 1 is an explanatory diagram showing one embodiment of the tape used in the semiconductor device of the present invention.
図で１０はベースフィルムであり、ポリイミドの長尺な
薄フィルムからなる。１２はベースフィルム１０の両側
縁近傍に設けたスプロケットホールである。In the figure, 10 is a base film, which is made of a long thin polyimide film. Reference numeral 12 denotes sprocket holes provided near both side edges of the base film 10.
１４は導体回路としてベースフィルム１０上に形成した
インナーリード、１６はアウターリードである。14 is an inner lead formed on the base film 10 as a conductor circuit, and 16 is an outer lead.
１８はベースフィルム１０に穿設したホールで、ホール
１８上にアウターリード１８が延在する。Reference numeral 18 denotes a hole bored in the base film 10, and the outer lead 18 extends over the hole 18.
１’ Ａ Ｂ用テープで一般的に用いられているもので
は、チップを搭載する部分にデバイスホールが穿設され
るが、本実施例のテープは向かい合ったインナーリード
１４間にもベースフィルム１０が連続して存在する。２
０はインナーリード１４の先端間のベースフィルム１０
１に設けたチップ接合部である。In the commonly used 1' A B tape, a device hole is formed in the part where the chip is mounted, but in the tape of this embodiment, the base film 10 is also formed between the facing inner leads 14. exist continuously. 2
0 is the base film 10 between the tips of the inner leads 14
This is the chip joint section provided in 1.
インナーリード１４、アウターリード１６はベースフィ
ルム１０上に銅箔等の導体層を形成した後、導体層にエ
ツチング、めっき等の処理を施して所定形状に形成する
が、チップ接合部２０も、ベースフィルム１０上でチッ
プ接合部２０の範囲内の導体層を残すことによって形成
することができる。なお、導体層は、ベースフィルムに
接着剤を介して接合して得るもの（３層構造）と、めっ
き、スパッタリング等により接着剤を介さずに接合して
得るもの（２層構造）がある。The inner leads 14 and outer leads 16 are formed into a predetermined shape by forming a conductor layer such as copper foil on the base film 10 and then subjecting the conductor layer to etching, plating, etc.; It can be formed by leaving a conductor layer on the film 10 in the area of the chip junction 20. Note that the conductor layer may be obtained by bonding to the base film via an adhesive (three-layer structure), or may be obtained by bonding to the base film without using an adhesive (two-layer structure) by plating, sputtering, or the like.
第２図は」１記テープにチップを搭載した後樹脂封止し
た半導体装置を示す断面図である。２２はチップで、チ
ップ接合部２０−１に接合されている。FIG. 2 is a sectional view showing a semiconductor device in which a chip is mounted on a tape and then sealed with a resin. 22 is a chip, which is joined to the chip joint portion 20-1.
２４はチップ２２とインナーリード１４との間をワイヤ
ボンディングしたワイヤである。２６は封止樹脂であっ
て、ワイヤボンディングを行った後、（５）
ベースフィルム、ＬＯのチップ２２が接合されている片
面側のみに設けられる。この結果、ベースフィルム１０
のチップ２２搭載面の反対側の面は外部に露出する。A wire 24 is wire-bonded between the chip 22 and the inner leads 14. 26 is a sealing resin, and after wire bonding, (5) the base film is provided only on one side to which the LO chip 22 is bonded. As a result, the base film 10
The surface opposite to the chip 22 mounting surface is exposed to the outside.
樹脂封止した後、ベースフィルム１０を所定の大きさに
裁断し、図のように外部リードを所定形状にフォーミン
グする。After resin sealing, the base film 10 is cut to a predetermined size, and external leads are formed into a predetermined shape as shown in the figure.
なお、インナーリード１４およびアウターリード１６等
の導体回路部分を構成する銅箔として電解銅箔を用い、
そのマツ１〜面を封止樹脂２６に接触する側にして樹脂
封止すると、マット面上に小さな凹凸があることにより
、導体回路と封止樹脂とのくいつきがよくなり、密着性
が向上する。これによって、半導体装置の耐湿性が向上
できる。Note that electrolytic copper foil is used as the copper foil constituting the conductive circuit parts such as the inner lead 14 and the outer lead 16,
When resin-sealing is performed with the pine 1 to surface in contact with the sealing resin 26, the small irregularities on the mat surface improve the adhesion between the conductor circuit and the sealing resin, improving adhesion. . Thereby, the moisture resistance of the semiconductor device can be improved.
第３図は、上記例と同様にチップ接合部２０にチップ２
２を接合して、ワイヤボンディングした後、樹脂封止し
てなるものであるが、導体回路に外部リードピン２８を
立設して樹脂封止した例を示す。FIG. 3 shows that the chip 2 is attached to the chip joint 20 as in the above example.
2 are bonded together, wire bonded, and then resin-sealed. An example in which external lead pins 28 are erected on the conductor circuit and resin-sealed is shown.
また、第４図および第５図は上記例の半導体装（６）
置に放熱体３０を設けた例を示す。第４図に示すものは
、樹脂封止した後、チップ２２の裏面部分に相当するベ
ースフィルム１０を除去してチップ接合部２０上に放熱
体３０を接合したものである。4 and 5 show an example in which a heat sink 30 is provided in the semiconductor device (6) of the above example. In the case shown in FIG. 4, after resin sealing, the base film 10 corresponding to the back surface of the chip 22 is removed, and a heat sink 30 is joined onto the chip joint portion 20.
外部リードピン接合部分の裏面はベースフィルム１０が
接合されて保護されている。A base film 10 is bonded to the back surface of the external lead pin bonding portion to protect it.
第５図に示すものは、チップ２２が搭載された面の反対
側の面全体に放熱体３０を接合したものである。In the case shown in FIG. 5, a heat sink 30 is bonded to the entire surface opposite to the surface on which the chip 22 is mounted.
これら各実施例に示ず半導体装置では、ベースフィルム
上にリードパターンを形成するから、リードをより薄く
形成することができ、これによってリードを高密度に形
成することができ、多ピン化の要求に容易に応えること
ができる。また、半導体装置はベースフィルムのチップ
が搭載された片面上でチップを樹脂封止して得られるか
ら、半導体装置の薄型化を図ることができる。In semiconductor devices, which are not shown in these embodiments, lead patterns are formed on a base film, so the leads can be formed thinner, and as a result, leads can be formed with high density, meeting the demand for a large number of pins. can be easily met. Further, since the semiconductor device is obtained by resin-sealing the chip on one side of the base film on which the chip is mounted, the semiconductor device can be made thinner.
さらに、チップとリードとの間はワイヤボンディングに
よって接続するから、ワイヤボンディングに関する従来
技術がそのまま適用でき、チップとリードとを接続する
技術的な困難さを解消することができる。Furthermore, since the chip and the leads are connected by wire bonding, the conventional technology regarding wire bonding can be applied as is, and the technical difficulties in connecting the chip and the leads can be solved.
また、半導体装置に放熱体を設けることも容易にでき、
熱放散性を向上させることによって、チップの高集積化
、大型化に容易に対応することができる。In addition, it is easy to provide a heat dissipation body to a semiconductor device.
By improving heat dissipation, it is possible to easily respond to higher integration and larger sizes of chips.
以上、本発明について好適な実施例を挙げて種々説明し
たが、本発明はこの実施例に限定されるものではなく、
発明の精神を逸脱しない範囲内で多くの改変を施し得る
のはもちろんのことである。The present invention has been variously explained above using preferred embodiments, but the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.
（発明の効果）
本発明によれば、上述したように構成したことにより、
半導体装置の多ピン化が容易にできるとともに、より薄
型でコンパクトな半導体装置を得ることができる。また
、製造過程においては、ワイヤボンディング等の従来技
術が適用でき、製造上の技術的な困難さを解消すること
ができる。また、半導体装置に放熱体を設けることも容
易にでき、これによって熱放散性を向上させることがで
きる等の著効を奏する。(Effects of the Invention) According to the present invention, by having the configuration as described above,
The number of pins in a semiconductor device can be easily increased, and a thinner and more compact semiconductor device can be obtained. Further, in the manufacturing process, conventional techniques such as wire bonding can be applied, and technical difficulties in manufacturing can be solved. Further, it is possible to easily provide a heat dissipation body in the semiconductor device, and this brings about significant effects such as improving heat dissipation performance.
第１図は本発明の半導体装置に用いるテープの一実施例
を示す概略説明図、第２図、第３図、第４図、第５図は
半導体装置の各実施例を示す断面図である。
１０・・・ベースフィルム、 １４・・・インナーリ
ード、 １６・・・アウターリード、１８・・・ホー
ル、 ２０・・・チップ接合部、２２・・・チップ、
２４・・・ワイヤ、２６・・・封止樹脂、 ２８・・
・外部リードピン、 ３０・・・放熱体。FIG. 1 is a schematic explanatory diagram showing one embodiment of the tape used in the semiconductor device of the present invention, and FIGS. 2, 3, 4, and 5 are sectional views showing each embodiment of the semiconductor device. . DESCRIPTION OF SYMBOLS 10... Base film, 14... Inner lead, 16... Outer lead, 18... Hole, 20... Chip joint part, 22... Chip,
24...Wire, 26...Sealing resin, 28...
・External lead pin, 30... Heat sink.
Claims (1)
を形成し、 該導体回路が形成された側のベースフィル ム面上にチップを搭載し、 チップと導体回路とをワイヤボンディング し、 チップが搭載された側のベースフィルム片 面上でチップを樹脂封止して成ることを特徴とする半導
体装置。 ２、チップが搭載された面の反対側の面に放熱体を接合
したことを特徴とする請求項１記載の半導体装置。[Claims] 1. A conductor circuit is formed on a base film having electrical insulation properties, a chip is mounted on the base film surface on the side on which the conductor circuit is formed, and the chip and the conductor circuit are connected with a wire. A semiconductor device characterized by bonding and resin-sealing a chip on one side of a base film on the side on which the chip is mounted. 2. The semiconductor device according to claim 1, wherein a heat sink is bonded to the surface opposite to the surface on which the chip is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1145789A JP2784209B2 (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1145789A JP2784209B2 (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10007703A Division JP2883065B2 (en) | 1998-01-19 | 1998-01-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0311641A true JPH0311641A (en) | 1991-01-18 |
| JP2784209B2 JP2784209B2 (en) | 1998-08-06 |
Family
ID=15393199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1145789A Expired - Lifetime JP2784209B2 (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2784209B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04277636A (en) * | 1991-03-05 | 1992-10-02 | Shinko Electric Ind Co Ltd | Preparation of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285646A (en) * | 1989-04-27 | 1990-11-22 | Hitachi Ltd | Resin sealed semiconductor device and formation thereof |
-
1989
- 1989-06-08 JP JP1145789A patent/JP2784209B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285646A (en) * | 1989-04-27 | 1990-11-22 | Hitachi Ltd | Resin sealed semiconductor device and formation thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04277636A (en) * | 1991-03-05 | 1992-10-02 | Shinko Electric Ind Co Ltd | Preparation of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2784209B2 (en) | 1998-08-06 |
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