JPH03108185A - Semiconductor memory controller - Google Patents

Abstract

PURPOSE:To prevent data from being destroyed by setting read access time with constant time width by deviating from a refresh period by prescribed time or more, and latching read out data simultaneously with the completion of the period. CONSTITUTION:When a time taub elapses with the delay time of a delay circuit 5b after a refresh request signal the inverse of RFSH is completed, a signal the inverse of CE is outputted from a NAND circuit 6a. At this timing, a read access permission signal the inverse of Access with time width equivalent to the delay time tauc of a delay circuit 7 is outputted from an OR circuit 9. The data read out at this time is supplied to a data buffer 16, and is latched with a latch circuit 16a at the trailing edge of the signal the inverse of Access. Next, when the next signal the inverse of RFSH is generated while read access by the signal the inverse of CE is performed, signal output from the circuit 9 is over, therefore, the signal the inverse of RFSH is outputted from a gate 6b as a refresh permission signal the inverse of Refresh, then, refresh is performed at a PSRAM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory control method suitable for use in memory cards and the like, and particularly to control of semiconductor memories that require refreshing to retain stored data. Regarding the method.

[Conventional technology]

Conventionally, memory cards used SRAM as memory and were configured to be backed up by a battery, but the present inventors have developed SRAM as a memory of the same size.
We considered a memory card that uses DRAM and backs it up with a battery because it has a storage capacity about four times that of RAM and can reduce power consumption.

However, in order to retain stored data, DRAM generally requires a refresh time of several hundred n5ec with a cycle of several msec, so it is necessary to manage and arbitrate between external access and refresh. A means is required. Moreover, it controls reading! (chip enable) signal and other control signals are different from memory cards mounted on SR8, and the interface is different, so memory cards mounted on DRAM are compatible with memory cards mounted on conventional SRAM. There was a problem that the .

In order to solve this problem, the present inventor first developed a memory that has a large storage capacity like DRAM (requires refreshing, but does not require a self-refresh circuit or SRAM).
P has a built-in interface that enables data input/output similar to A M, and enables control similar to SRAM.
We would like to propose a memory card using SRAM (pseudo SRAM) (Japanese Patent Application No. 1-180851), and such a memory card will be briefly explained with reference to FIG.

In the figure, when the connector 10 is not connected to an information processing device such as a computer, the power switching circuit 1
2, power is supplied from the backup battery 11 to the PSRAM 20, and its built-in self-refresh circuit 20a operates to perform r) refreshing of the SRAM 20.

This eliminates the need for external refresh
Data is held in RAM 20. In addition, connector 10
When the is connected to the information processing device, the connector 10 is connected to the information processing device.
, the power supply line 10a, and the PSR via the power supply switching circuit 12.
Power is supplied to AM20. At this time, PSRAM2
A refresh request signal of 0 is generated by the arbitration circuit 19.

In this way, the refresh operation is performed inside the memory card independently of the external information processing device, so the information processing device only needs to perform the same control as a memory card mounted on an SRAM tower. It will be compatible with memory cards.

When data from an information processing device connected to the connector 10 is to be stored in a memory card, an address signal is supplied from the information processing device to the address buffer 15 via the connector 10 and the address signal line 10b, and the data is stored in the PSRAM 20.
write address is specified. In addition, the control signal line 10
A Wπ (write enable) signal is supplied to the arbitration circuit 19 via the data signal line 10d and the data buffer 1.
6 is written to a designated address in PSRAM 20.

When reading data from the PSRAM 20, the address signal is similarly transmitted via the address signal line 10b.
Control signals such as an output signal and a σπ (output enable) signal are supplied via the control line 10c. P.S.
Data is read from the address specified by this address signal in the RAM 20, and is stored in the data buffer 16. The signal is supplied to the information processing device via the data signal line 10d and the connector 10.

Here, when reading data, the arbitration circuit 19 operates upon receiving the decoded output of the address signal from the decoder 14, and upon receiving the π signal via the control rfj (? I will let you do it, but
Since a refresh request signal is also generated to refresh the PSRAM 20, arbitration is made so that data read and refresh do not overlap.

Note that the decoder 14 may be provided between the arbitration circuit 19 and the PSRAM 20, so that the arbitration circuit 19 operates with the π signal and the decoder 14 operates with the output of the conditioning circuit 19. If there is only one decoder 14, the decoder 14 may be omitted.

FIG. 6 shows an example of the arbitration circuit 19 in FIG. 5.

In the figure, the arbitration circuit 19 consists of an access arbitration section 19a and a chip enable signal conversion section 19b.

The access arbitration unit 19a is, for example, a Nantes gate 5a.
, 5)), a circuit that delays the output of the Nantes gate 6a with a delay circuit 5a and feeds it back to the Nantes gate 6b, and a circuit that delays the output of the Nantes gate 6b with the delay circuit 5b to form a Nantes gate. 6a with a feedback circuit added, 3113
The level of the signal is inverted and input to the NAND/ITRO a, and the refresh request signal W from the refresh timer 19c is input to the NAND gate 6b.

The output of the Nant gate 6a is a read access permission signal A access that allows read access to the PSRAM 20.
, and the output of the Nant gate 6b is a refresh permission signal Refre that allows refresh of the psRAM 20.
It is sh.

With this configuration, when the Eπ signal is supplied in the refresh request signal FF'TT, the refresh permission signal Refresh is generated at the same timing as the refresh request signal W-π, as shown in the part (■) in FIG. However, the read access permission signal Access is generated much later than the refresh request signal rDingDing2 due to the delay time of the delay circuit 5b. As a result, ■ in Figure 7
As shown in the part, in the PSRAM 20, data is read out τ after the refresh is completed.

In addition, as shown in part (■) in FIG. 7, when the refresh request signal RESI (is generated within the period of the π signal, the τπ signal ends and the read access permission signal A cc
After the completion of ess and the delay time τ of the delay circuit 5a has elapsed, the refresh permission signal Refresh is generated. As a result, the PSRAM 20 is refreshed 1ji after data reading is completed.

The refresh timer 19c is reset by the output signal of the delay circuit 5a, so that the time width of the refresh permission signal Refresh remains constant no matter what timing the refresh request signal T'U occurs.

The chip enable signal converter 19b in FIG.
As shown in FIG. 8, EXOR circuit 2 a + 2 b,
By detecting the change point of the address signal by +2n and supplying the pulse representing this change point and the π signal to the OR circuit 3,! Does the signal indicate the point at which the address changes? ff.

I get a signal. This -π signal is applied to the chip enable terminal of the PSRAM 20 via an AND gate 4 whose gate signal is an inversion of the read access permission signal Access.

In PSRAM20, this? 'ff, data is read from the address specified at that time after a predetermined read access time from the rising edge of the signal, and by operating the data buffer 16 at this timing,
h'J output data is transferred to the information processing device via the data buffer 16.

[Problem to be solved by the invention]

By the way, according to the prior art mentioned above, in the read/stop circuit, the timing at which the refresh request signal is generated is at a point in time when a certain period of time has elapsed from the end timing of the refresh request signal generated immediately before. And, teπ
Even if a refresh request signal is generated during the read access mode while the signal is being supplied, the refresh permission signal is generated only after the read access mode ends.

For this reason, if read access mode continues for a long time,
PSRAM cannot be refreshed.
There was a problem in that it was difficult to retain data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory control method that solves these problems, enables refresh in read access mode, and ensures data retention in PSRAM.

[Means to solve the problem]

In order to achieve the above object, the present invention makes the read access permission signal generated in the read access mode have a fixed time width, and latches the read data in a latch circuit at the timing when the read access by the read access permission signal ends. .

[Effect]

The PSRAM actually enters the read access mode during the period of the read access permission signal. At the end of this period, the PSRAM is released from the read access mode, but since the read data is latched from the time of release, refreshing can be performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the semiconductor memory control method according to the present invention, in which 7 is a delay circuit, 8 is an inverter, 9 is an OR circuit, 16a is a latch circuit, and a fifth
The same reference numerals are given to the parts corresponding to those in FIG.

In the figure, between the Nantes gate 6a and the delay circuit 5a, there is a delay circuit 7 that delays the output of the Nantes gate 6a, and an inverter 8 that inverts the level of the output of the delay circuit 7.
This is different from the prior art in that a circuit consisting of a Nant gate 6a and an OR circuit 9 whose input is the output of an inverter 8 is provided, and a latch circuit 16a is provided in the data buffer 16 to latch the read data from the PSRAM 20. different from.

Similar to the prior art described above, the OR circuit 3 outputs a signal obtained by adding a pulse representing the change point of the address signal to the n signal, and this becomes the input to the R-S flip-flop. The refresh permission signal Refresh is output from the Nantes gate 6b, but the read access permission signal A
ccess is output from the OR circuit 9. This read access permission signal Access is generated by the OR circuit 9 performing an OR operation of the output of the Nant gate 6a and a signal delayed by the delay circuit 7 and inverted in level by the inverter 8, resulting in the delay time τ of the delay circuit 7. . "L" with a time width equal to
” is the signal.

Next, to simplify the explanation, the output of OR circuit 3 is (
In addition to the π signal itself, this τ signal is generated within the period of the refresh request signal
The operation of this embodiment will be explained with reference to FIG. 2, assuming that the next refresh request signal fF''τ is generated within the period of the signal.

When the refresh request signal 1'ffτ is generated and the discard signal is supplied within this period to instruct the read access mode, this output is further transmitted to the delay circuit 5b for a time τ, by the output of the Nant gate 6b. The Nante gate 6a is turned off by the delayed signal, and the 'il signal is not output from the Nante gate 6a.The refresh request signal y is output from the Nante gate 6b as the refresh permission signal Refresh.

After the refresh request signal ■Ding T'H is completed, the delay circuit 5b
When the delay time has elapsed, a π signal is output from the Nant gate 6a, and at this timing, the OR circuit 9 outputs a read access permission signal A access having a time width equal to the delay time τ6 of the delay circuit 7.

As a result, when the P S RAM is refreshed by the refresh permission signal/signal Refrosh, the time τ starts from this point. After a delay of 8 εcess, read access is performed and data is read out in response to the read access permission signal 8εcess.

At this time, this read data is stored in data buffer 1.
6, and the read access permission signal A access
The trailing edge (rising edge) of the signal is latched by the latch circuit 16a.

Next, when the next refresh request signal r ding ding 1 is generated during the read access mode by the te signal, the OR circuit 9
Since the signal output from has finished, Nando Game I/6b
This refresh request signal ■DingDing1 is output as the refresh permission signal Refresh, and P S RA
Refreshing is performed at M.

In this way, even if the read access mode is designated by the D signal from the external information processing device, and this read access mode continues for a long time, and the refresh request signal R D D D is generated during this mode period, the PSRAM In the read access mode, the time width τ is actually output from the OR circuit 9.

It is a read access permission signal of 3..., so in response to this refresh request, PSRAM
A refresh is performed. And at this time, PSR
Since the data read from AM is latched by the latch circuit 16a of the data buffer 16, there is no problem in reading the data in the information processing device.

Note that the read access permission signal Acc from the OR circuit 9
When the refrigeration request signal Yτ is generated during the output of ess, this read access permission signal A acce
Needless to say, the refresh permission signal Refresh is generated after the delay time τ of the delay circuit 5a after the completion of ss.

FIG. 3 is a block diagram showing another embodiment of the semiconductor memory control system according to the present invention, in which 21 is a frequency divider, 22 is a flip-flop, 23.24 is an inverter, 25.26
is a Nante gate, 27 is an OR circuit, 28 is a NOR circuit, 2
9 to 31 are D flip-flops.

The operation of this embodiment will be explained below with reference to FIG.

First, in FIGS. 3 and 4(a), the frequency divider 21
outputs a pulse from the Q and l terminals every n clocks CLK, and the flip-flop 22 divides the frequency of the Q and output pulses by 2, the level of which is inverted every time the output pulse of the frequency divider 21 is supplied. Qz small output is generated. These frequency divider 21 and flip-flop 22 constitute a counter that counts the clock CLK.

Further, the discard signal from the information processing device (not shown) falls at the D flip-flop 29, and the rising edge is the clock C.
The signal is shaped into a signal synchronized with LK, is supplied to the NOR circuit 28, is added to the signal ATD representing the change point of the address signal generated in the same manner as the chip enable signal converter 19b in FIG. When the address signal changes, a φ-e signal is formed by adding a point pulse to the signal.

In standby mode, as shown in Figure 4(b), D
The π signal supplied to the flip-flop 29 is "H", and the φ signal output from the NOR circuit 28 is held at "L".

The Q1 output of the flip-flop 22 is inverted in level by the inverter 23 and supplied to the Nant gate 25, and the QX output of the flip-flop 22 is supplied to the Nant gate 25 as is. As a result, a refresh request signal 71- is obtained from the Nant gate 25, which is "L'" only during the first half of the "H" period of the Q8 output of the flip-flop 22.

This is also a refresh permission signal for the PSRAM (not shown), and this refresh request signal
Refreshing is performed in the PSRAM every L'' period.

Further, the Q8 output whose level has been inverted by the QI ratio output inverter 24 is supplied to the Nantes gate 26, and from this Nantes gate 26 a signal which becomes "L" in the first half of the "L" period of the Q2 output is supplied. However, D
Flip-flop 31 is in a reset release state. Therefore, in the D flip-flop 31, the AND gate 2
The "H" D input is sampled and held at the first falling edge of the output of the Nant gate 26 and the "H" of the D flip-flop 31, and its Q output is held at 'H'. By supplying the Q output held at "H" to the OR circuit 27, the read access permission signal Kaii output from the OR circuit 27 is held at "H".

As a result, read access is prohibited in the PSRAM.

In this way, during standby, refreshing is performed in the PSRAM at regular intervals.

In the case of data reading from PSRAM, the method shown in FIG.
), when the π signal becomes L', the information processing device instructs the read access mode.

Now, at the beginning, the π signal becomes “L” at 0 in Fig. 4 (C).
As for the part, assuming that there is no ATD signal, the φ1 signal output from the NOR circuit 28 is synchronized with the clock CLK and has a level inverted relationship with the π signal. For this reason, the D flip-flop 31 is in the reset release state during the period in which the φ signal is "H", that is, the period in which the π signal is "L".

Therefore, when the output of the Nant gate 26 becomes "L" for the first time, the D flip-flop 31 is still in the unreset state and its Q output is "L", so it is the output of the OR circuit 27. Read access permission signal A c
cess becomes “L”, and during this “L” period, PSRAM
Data reading is performed at . This read data is supplied to the latch circuit 16a and latched at the rising edge (trailing edge) of the read access permission signal.

Further, the D flip-flop 31 goes high at the first rising edge of the output of the Nant gate 26 after its reset is released.
” sample and hold the D input, and its Q output is “H”
This continues until the φ signal output from the NOR circuit 28 becomes "L", that is, the output signal becomes "H" and the D flip-flop 31 is reset.

As a result, if there is no change in the address signal and data is read at the specified address during the specified period of the read access mode by the π signal, then read access is performed again during the specified period of the read access mode. To prevent this from happening, the D flip-flop 31 masks the L'' period of the output of the Nant gate 26 so that it is not output from the OR circuit 27.

Next, it is assumed that the read access mode is designated again by the π signal during the 1L' period of the Q3 output of the flip-flop 22, as shown by the part (■) in FIG. 4(C).

In this case, at the timing of the rising edge of the φ8 signal from the NOR circuit 28, the D flip-flop 30 samples and holds the Q output of 1L, and the Q output of the D flip-flop 30 becomes "L". As a result, the clip-flop 22 is reset at the falling edge, and from this timing, the counter consisting of the frequency divider 21 and the flip-flop 22 restarts the counting operation of the clock CLK. Therefore, from this reset timing, the Q output of the flip-flop 22 is "L" for 172 cycles, and the Q2 output is also "L" for 1/2 cycle. Therefore, the output of the Nant gate 26 becomes "L" during the period in which both the Q+ and Qz small outputs are "L" (the start of this period coincides with the rising edge of the φ8 signal), and the D flip-flop 31 becomes "L". Since the reset is released at the rising edge of the signal, the φ signal becomes "Hl" and the read access permission signal A from the OR circuit 27
access becomes L'', and data is read from the PSRAM.

The subsequent steps are the same as the part (■) in FIG. 4(c).

In this way, the masking function of the D flip-flop 31 ensures that data is read only once for a specified address, and refresh of the PSRAM is performed without interruption during the period when no read access is performed. It will be done.

Also in this embodiment, upon completion of the read access, the data read out is transferred to the latch circuit 16a.
Since the PSRAM is latched, refreshing of the PSRAM is performed without any problem, and reading of data to the information processing device is not hindered by the refresh operation of the PSRAM.

Furthermore, since the data is latched and the PSRAM is placed in standby mode, it is possible to save power.

【Effect of the invention〕

As explained above, according to the present invention, PSRAM can be refreshed periodically regardless of the length of external read access mode, and PSRAM
It is possible to ensure data retention in the memory, data is not destroyed by refreshing, and data can be read externally without any problem.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the semiconductor memory control method according to the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is another embodiment of the semiconductor memory control method according to the present invention. Fig. 4 is a timing chart showing its operation, Fig. 5 is a block diagram showing the PSRAM.
FIG. 6 is a block diagram showing an example of the arbitration circuit in FIG. 5, FIG. 7 is a timing chart showing the operation of the access arbitration section in FIG. 6, and FIG. is a timing chart showing the operation of the chip enable signal converter. 5a, 5b...Delay circuit, 6a, 6b・
・・・・・・・・・Nante Gate, 7・・・・・・・・・
Delay circuit, 8... Inverter, 9...
...OR circuit, 16... Data buffer, 16a... Latch circuit, 19
c...Refresh timer, 22...
...Flip-flop, 23.24...
...Inverter, 25.26...Nands gate, 27...OR circuit, 30°31...D flip-flop. Figure 2 ＼ a), Nate-2 Figure (a) 11 drawings on CL--------------1--
-----------Dish skin (b) Figure 6

Claims (2)

[Claims] (1) In a read access and refresh control method for a semiconductor memory that requires refreshing in order to retain stored data, when a read access mode is externally specified, the refresh period is A semiconductor memory control method characterized by setting a read access time of a certain time width by shifting from a predetermined time period or more, and latching data read from the semiconductor memory in a latch circuit at the end of the read access period. . (2) A semiconductor memory control method according to claim (1), characterized in that the next refresh period following the set read access period is set to be delayed by a predetermined period or more from the read access time.