JP2004280947A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device with which write recovery time can be shortened even for an operation with long internal write cycle. <P>SOLUTION: A command control circuit 400 generates an internal command signal; and a command standby signal generating circuit 500 generates a command standby signal bicsz for delaying the generation of the internal command signal for performing the next command operation when the write operation lasts long. Based on the command standby signal bicsz, a decision circuit 100a decides a relationship between the termination of the write operation and the initiation of the next command operation, inhibits the execution of a refresh operation and executes a read operation when the write operation does not terminate until the initiation of the next command and if the next command is a read operation. After the termination of the read operation, a refresh command refpz is outputted and the refresh is executed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that always performs an internal refresh operation.
[0002]
[Prior art]
2. Description of the Related Art In recent years, small mobile terminal devices such as mobile phones and PDAs (Personal Digital (Data) Assistants) handle a large amount of data in cooperation with the Internet. Accordingly, a high-speed and large-capacity memory is required.
[0003]
At present, an SRAM (Static Random Access Memory) with low power consumption is often used for a mobile phone, but there is a problem that the integration degree of the SRAM is low and the cost increases if the capacity is increased. On the other hand, since a DRAM (Dynamic Random Access Memory) can be increased in capacity at a low cost, an SRAM interface type DRAM is required.
[0004]
Since a DRAM is a volatile memory, it is necessary to perform a refresh operation for holding data at regular intervals. Since this is not necessary in the SRAM, the SRAM interface type DRAM requires some means by controlling the inside of the memory.
[0005]
As this means, an internal refresh is always performed, and when a read (read) / write (write) command is input from the outside, a refresh command generated internally and a command signal from the outside are compared. There is a control method in which the read / write is executed after the refresh as soon as possible, and the refresh is executed after the read / write command as soon as the command is issued. With such a method, the refresh operation becomes invisible from the outside of the memory, so that a refresh command is not necessary as in the SRAM (for example, see Patent Document 1).
[0006]
FIG. 17 is a block diagram of a part of a control system of a conventional DRAM.
This control system includes a refresh / command determination circuit 950, a command decode circuit 951, an RAS operation control circuit 952, and a command control circuit 953.
[0007]
The refresh / command determination circuit 950 determines which of the state transition detection signal atdpz generated from the chip enable signal / CE and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is later than the refresh request signal srtz, the refresh command refpz and the refresh signal refz are output.
[0008]
The command decode circuit 951 receives the state transition detection signal atdpz, the output enable signal / OE, the write enable signal / WE or the chip enable signal / CE, and receives command signals (read command rdpz, write command wrpz, active command). actpz).
[0009]
The RAS (row address strobe) operation control circuit 952 receives the refresh signal refz, the refresh command refpz, and the active command actpz, and outputs a row address strobe signal rasz for activating the core. Further, it outputs a signal icsx for waiting for the next operation until the operation of the previous cycle is completed. Note that the signal icsx is a signal delayed in the opposite phase of the row address strobe signal rasz.
[0010]
The command control circuit 953 receives the command signal and the refresh signal refz, and outputs internal command signals (internal read command rdpx, internal write command wrpx).
[0011]
FIG. 18 is a timing chart showing the operation of the conventional semiconductor memory device when refreshing is performed first.
If the refresh request signal srtz (H level single pulse) is earlier than the state transition detection signal atdpz (H level single pulse), the refresh / command determination circuit 950 causes the refresh command refpz (H level single pulse). One pulse) is output, and the refresh signal refz rises to the H level. Further, in synchronization with the input refresh command refpz, the RAS operation control circuit 952 raises the row address strobe signal rasz to the H level, activates the core, and performs the refresh operation. At this time, the signal icsx goes to L (Low) level, and goes to H level when refreshing is completed.
[0012]
The command decode circuit 951 detects the state transition detection signal atdpz input following the refresh request signal srtz, and outputs the active command actpz (single pulse of H level). The command wrpz is waited in the command control circuit 953. When the refresh operation ends and the signal icsx goes high, the refresh signal refz goes low. In response to this, the command control circuit 953 outputs the standby internal read command rdpx or internal write command wrpx, raises the row address strobe signal rasz to the H level, activates the core, and performs the read or write operation. Do.
[0013]
FIG. 19 is a timing chart showing an operation of a conventional semiconductor memory device when a read or write operation is performed first.
When the state transition detection signal atdpz is earlier than the refresh request signal srtz, the refresh / command determination circuit 950 delays the output of the refresh command refpz. At this time, the row address strobe signal rasz becomes H level by the active command actpz, and the read or write operation is executed according to the internal command signal. The refresh operation is executed by the refresh command refpz output when the signal icsx goes to the H level after the read or write operation ends.
[0014]
Note that the write cycle of the semiconductor memory device may be longer than the normal operation mode. In a semiconductor memory device having an operation mode in which a write cycle is lengthened, if a RAS write operation enters a cycle in which the next operation is to be performed, the internal operation of the next cycle is completed before the operation of the previous cycle is completed. Started and normal operation is no longer possible. Therefore, there is a method of detecting the end of the previous write cycle and controlling the operation of the next cycle.
[0015]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-74943 (FIG. 6)
[0016]
[Problems to be solved by the invention]
However, if the refresh command is waiting in the operation mode in which the write cycle is long, the read operation and the start of the refresh operation in the next cycle conflict because the end of the write cycle is detected and performed. However, there is a problem that normal operation cannot be performed.
[0017]
If the chip enable signal / CE after the write cycle has a sufficient H-level period (standby period or write recovery time), a normal operation can be performed after the write operation of the previous cycle is completed.
[0018]
However, in this case, there is a problem that sufficient write recovery time causes a time overhead and lowers system performance.
The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor memory device capable of shortening a write recovery time even in an operation mode having a long write cycle.
[0019]
[Means for Solving the Problems]
In the present invention, in order to solve the above problem, in a semiconductor memory device performing an internal refresh operation, as shown in FIG. 1, a command control circuit 400 for generating an internal command signal for performing a command operation, and a long write operation are provided. In this case, a command standby signal generation circuit 500 for generating a command standby signal biscsz for waiting for an internal command signal for performing the next command operation, and based on the command standby signal biscsz, termination of the write operation and execution of the next command operation A determination circuit that determines a start relationship and outputs a standby refresh command refpz after the end of the read operation if the write operation does not end until the start of the next command operation or the next command operation is a read operation (see FIG. 1 is described as a refresh / command determination circuit). The semiconductor memory device is provided which is characterized in that.
[0020]
According to the above configuration, the command control circuit 400 generates the internal command signal, and the command standby signal generation circuit 500, when the write operation is long, delays the generation of the internal command signal for performing the next command operation. Generate the signal bikesz. The determination circuit 100a determines the relationship between the end of the write operation and the start of the next command operation based on the command standby signal bicsz. If the write operation does not end until the start of the next command operation, the next command If the operation is a read operation, the standby refresh command refpz is output after the end of the read operation. As a result, after a long write operation, collision between refresh in standby and read operation as the next command operation is prevented.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a part of a control system of the semiconductor memory device according to the first embodiment of the present invention.
[0022]
Hereinafter, a control system of a DRAM will be described as an example.
The control system includes a refresh / command determination circuit 100a, a command decode circuit 200, an RAS operation control circuit 300, a command control circuit 400, and a command standby signal generation circuit 500.
[0023]
The refresh / command determination circuit 100a has a function of determining which of the state transition detection signal atdpz and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is later than the refresh request signal srtz, the refresh command refpz and the refresh signal refz are output. Note that the state transition detection signal atdpz is output from a state transition detection circuit (not shown) upon detecting the fall of the chip enable signal / CE.
[0024]
Furthermore, the refresh / command determination circuit 100a according to the first embodiment of the present invention includes a signal icsx from the RAS operation control circuit 300, an internal read command rdpx from the command control circuit 400, and a command standby signal from the command standby signal generation circuit 500. bidsz.
[0025]
Based on these signals, the refresh / command determination circuit 100a determines the relationship between the end of the write operation and the start of the read operation in the next cycle. Here, if the write operation is not completed before the start of the next read operation, that is, if the state transition detection signal atdpz is detected while the command standby signal bicsz is being input, if the refresh request is waiting , The output of the refresh command refpz is prohibited until the internal read command rdpx is issued by the command control circuit 400. Then, after the read operation is completed, a refresh command refpz is output. When the write operation is completed until the start of the next read operation, the refresh command refpz and the refresh signal refz are output in response to the waiting refresh request regardless of the next command operation.
[0026]
The command decode circuit 200 receives the state transition detection signal atdpz, the output enable signal / OE, the write enable signal / WE or the chip enable signal / CE, and receives command signals (read command rdpz, write command wrpz, active command actpz) and outputs it to the command control circuit 400.
[0027]
The RAS operation control circuit 300 receives the refresh command refpz and the internal active command actpx generated by the command control circuit 400, and outputs a row address strobe signal rasz for activating a core (not shown). Further, the row address strobe signal rasz is delayed to output a signal icsx having an inverted phase.
[0028]
The command control circuit 400 receives a command signal and a refresh signal refz, and receives an internal command signal (an internal read command rdpx, an internal write command wrpx, an internal active command actpx) and a signal writez indicating whether or not a write operation is being performed. Is output.
[0029]
The command wait signal generation circuit 500 is a signal indicating that the write cycle is lengthened, and receives a mode signal modez set and generated by a mode register or the like and a signal writez. Further, based on these signals, a command waiting signal biscsz for waiting for the next command is output, and an internal command signal output from the command control circuit 400 is caused to wait.
[0030]
Next, a specific operation of the control system in FIG. 1 when a read operation is performed after a write operation will be described with reference to a timing chart of each signal.
FIG. 2 is a timing chart for explaining an operation in a control system of the semiconductor memory device according to the first embodiment.
[0031]
When the chip enable signal / CE falls to the L level, this is detected to generate the state transition detection signal atdpz (single pulse of the H level). The state transition detection signal atdpz is input to the refresh / command determination circuit 100a. In the refresh / command determination circuit 100a, the refresh request signal srtz (single pulse of H level) and the state transition detection signal atdpz are compared, and the operation with the earlier timing is selected. In FIG. 2, since the state transition detection signal atdpz rises earlier, the command operation has priority.
[0032]
In cycle 1, a write operation is performed. At this time, the state transition detection signal atdpz is detected, and the command control circuit 400 generates the internal active command actpx (single pulse of L level) by the active command acttpz (single pulse of H level) generated by the command decode circuit 200. ) Is generated. In synchronization with this, in the RAS operation control circuit 300, the row address strobe signal rasz rises to the H level, and the core is activated. Also, the signal icsx becomes L level. At this time, data is written from an input buffer (not shown) to an address specified from outside the core.
[0033]
Further, in the case of a write operation, the command control circuit 400 outputs an internal write command wrpx (single pulse of L level), and in synchronization with this, the signal writez goes high. In the case of a write operation with a long operation cycle, the command standby signal generation circuit 500 receives the mode signal modez (omitted in FIG. 2) and sets the command standby signal bicsz to the H level as shown in FIG.
[0034]
When the chip enable signal / CE returns to the H level and returns to the L level again, the state transition detection signal atdpz is output, and the operation in cycle 2 starts. In cycle 2, a read operation is performed.
[0035]
As shown in FIG. 2, when the write enters the cycle 2, the command standby signal bicsz is at the H level while the write operation is continued, and the command control circuit 400 waits for the output of the internal read command rdpx. When the row address strobe signal rasz goes low and the signal icsx goes high and the write operation in cycle 1 ends, the command standby signal generation circuit 500 detects the rise of the signal icsx and changes the command standby signal bicsz to L. To level. In synchronization with this, the command control circuit 400 outputs the internal active command actpx and outputs the waiting internal read command rdpx (single pulse of L level) to perform the read operation. At this time, the signal writez goes low in synchronization with the output of the internal read command rdpx.
[0036]
In the semiconductor memory device according to the first embodiment of the present invention, the refresh / command determination circuit 100a waits for the refresh command refpz that has been on standby even if the write that entered cycle 2 ends and the signal icsx goes high. Is not output. The refresh command refpz is output at the rise of the signal icsx at the end of the read operation. As a result, the refresh signal refz is set to the H level, and the row address strobe signal rasz is raised to the H level to perform the refresh operation.
[0037]
As described above, in the semiconductor memory device according to the first embodiment of the present invention, the relationship between the write operation and the start of the next read operation is determined by the refresh / command determination circuit 100a. If the operation is not completed until the start of the operation, the standby refresh command is output after the end of the read operation. Thereby, it is possible to prevent a collision between the read operation and the refresh operation.
[0038]
Next, the details of the refresh / command determination circuit 100a will be described.
FIG. 3 is a circuit configuration diagram of an example of the refresh / command determination circuit.
The refresh / command determination circuit 100a includes a NAND circuit 101 that performs NAND logic of a command standby signal bicsz and a state transition detection signal atdpz, an FF circuit 102 having a terminal for inputting an output signal of the NAND circuit 101, and a flip-flop circuit ( A NAND circuit 103 for inputting an output signal of the FF circuit 102 to one input terminal. The signal icsx is input to the other input terminal of the NAND circuit 103, and the output signal of the NAND circuit 103 is input to one input terminal of the NAND circuit 105 via the inverter 104. The output signal of the NOR circuit 107 to which the state transition detection signal atdpz and the state transition detection signal atdpz delayed by the delay circuit 106 are input is input to the other input terminal of the NAND circuit 105 via the inverters 108 and 109. Is input to
[0039]
An output signal of the NAND circuit 105 is input to the FF circuit 110 functioning as a comparison unit. The FF circuit 110 includes NAND circuits 110a and 110b, and the output signal of the NAND circuit 105 is input to one input terminal of the NAND circuit 110a. The output signal of the FF circuit 112 to which the refresh request signal srtz is input to one input terminal via the inverter 111 is input to one input terminal of the NAND circuit 110b. The FF circuit 112 includes NAND circuits 112a and 112b, and the output of the inverter 111 is input to one input terminal of the NAND circuit 112a. The output of the FF circuit 112 is output from the NAND circuit 112a.
[0040]
The output of the FF circuit 110 functioning as a comparison unit is input to the FF circuit 114 via the inverter 113. The FF circuit 114 includes NOR circuits 114a and 114b. Here, the output of the inverter 113 is input to one input terminal of the NOR circuit 114a, the output is output from the NOR circuit 114b, and this output signal becomes the refresh command refpz.
[0041]
The output signal of the FF circuit 114 is further input to the FF circuit 115. The FF circuit 115 includes NOR circuits 115a and 115b. Here, the output of the FF circuit 114 is input to one input terminal of the NOR circuit 115a, and the output is also output from the NOR circuit 115a. The output signal of the FF circuit 115 is inverted by the inverter 116 and output to the outside of the refresh / command determination circuit 100a as a refresh signal refz.
[0042]
Note that the output signal of the FF circuit 115 is input to one input terminal of the NOR circuit 114b included in the FF circuit 114 via the delay circuit 117. Further, the output signal of the FF circuit 115 is input to one input terminal of the NAND circuit 112b included in the FF circuit 112 via the delay circuits 117 and 118 and the inverter 119.
[0043]
The operation of the refresh / command determination circuit 100a will be described.
Note that, here, a description will be given below assuming that the node A is the output signal of the inverter 109, the node B is the output signal of the NAND circuit 105, the node C is the output signal of the FF circuit 102, and the node D is the output signal of the inverter 104.
[0044]
When the refresh request signal srtz is input and a refresh request is made, the output of the FF circuit 112 becomes H level and is input to the FF circuit 110.
The FF circuit 110 functions as a comparison unit that compares which of the state transition detection signal atdpz and the refresh request signal srtz is input first. If the state transition detection signal atdpz is input earlier than the refresh request signal srtz, the node A goes low and the node B goes high, so the refresh request signal srttz is input after that, and the FF circuit , Becomes an H level, while the node B is at the H level, the FF circuit 110 selects the command operation, and the refresh command refpz is not output.
[0045]
At this time, the refresh request signal srttz is held by the FF circuit 112, and when the node B goes low, the refresh operation is selected by the FF circuit 110, and the output of the FF circuit 110 goes low.
[0046]
The output of the FF circuit 110 is input to the FF circuit 114 after being inverted by the inverter 113. At this time, the output of the FF circuit 114 becomes H level, and the refresh command refpz rises to H level and is output. Also, the FF circuit 115 holds the H level for the time during which the signal icsx is at the L level during the execution of the refresh, and outputs the refresh signal refz.
[0047]
On the other hand, when the refresh request signal srtz is input before the state transition detection signal atdpz, if the node D is at the H level, the node B is at the L level. Therefore, the refresh operation is selected by the FF circuit 110, As described above, the refresh command refpz and the refresh signal refz are output.
[0048]
Here, the output level of the node B is determined as follows.
In the FF circuit 102, when both the levels of the two input terminals are at the H level, the state is held. That is, at least one of the command waiting signal biscs and the state transition detection signal atdpz is at L level, and the internal read command rdpx is at H level.
[0049]
In the operation mode in which the write cycle is long, when the command standby signal bicsz is at the H level and the state transition detection signal atdpz becomes the H level by the start of the next read cycle, the FF circuit 102 is set, and the node C It becomes L level. At this time, the node D goes low and the node B goes high. In this state, even if the write operation is completed and the signal icsx rises to H level, the node D holds L level and the node B remains at H level. That is, the refresh command refpz is not output.
[0050]
When the command control circuit 400 generates a single pulse at which the internal read command rdpx goes low, the node C goes high. At this time, when the write operation ends and the signal icsx rises and goes to H level, the node D goes to H level and the state transition detection signal atdpz is at L level, so that the node B goes to L level.
[0051]
Next, the operation of the refresh / command determination circuit 100a in FIG. 3 will be specifically described with reference to a timing chart showing timings of main signals.
FIG. 4 is a timing chart for explaining the operation of the refresh / command determination circuit.
[0052]
The time axis of the timing chart of FIG. 4 coincides with the timing chart of the control system of FIG.
When the chip enable signal / CE falls to L level, this is detected, and a state transition detection signal atdpz, which is a single pulse of H level, is generated. The state transition detection signal atdpz is input to the refresh / command determination circuit 100a. In the refresh / command determination circuit 100a, the FF circuit 110 compares the refresh request signal srtz with the state transition detection signal atdpz, and selects an operation of a signal that is input earlier. In FIG. 4, the state transition detection signal atdpz is early, the node A goes low, and in synchronization with this, the node B, which is the input of the FF circuit 110, goes high, and the command operation is selected. The node A maintains the L level while the signal icsx is at the H level by the delay circuit 106, and thereafter returns to the H level.
[0053]
In cycle 1, the write is executed, the row address strobe signal rasz goes high, and the core is activated. Also, the signal icsx becomes L level. Upon detecting the fall of the signal icsx, the node D becomes L level.
[0054]
When the chip enable signal / CE returns to the H level and returns to the L level again, the state transition detection signal atdpz is output, and the operation in cycle 2 starts. In cycle 2, a read operation is performed.
[0055]
When the operation in cycle 2 starts, the node A goes low in synchronization with the output of the state transition detection signal atdpz. At this time, since the write operation in the cycle 1 is continuing, the command standby signal bicsz is at the H level, so that the node C, which is the output signal of the FF circuit 102, is at the L level. After that, since the FF circuit 102 is in the holding state, the node C holds the L level. Therefore, the node D holds the L level even when the write operation in the cycle 1 is completed and the rising edge of the signal icsx is detected, and the node B remains at the H level. As a result, the refresh command refpz is not output, and the refresh operation is not started.
[0056]
When the internal read command rdpx output after the end of the write operation is detected, the node C goes high. Here, when the reading of the cycle 2 is completed and the signal icsx goes to H level, the rise is detected and the node D goes to H level and the node B goes to L level. Here, the refresh request held in the FF circuit 112 is selected by the FF circuit 110, the refresh command refpz is output, the refresh signal refz is set to the H level, and the refresh operation is performed.
[0057]
When the refresh operation starts, the signal icsx goes to L level, and in synchronization with this, the node D also goes to L level. When the chip enable signal / CE returns to the H level and returns to the L level again, the operation in the next cycle starts. At this time, the state transition detection signal atdpz is generated, and the node A goes low in response to this. At this time, the node B becomes H level.
[0058]
As described above, when the read operation in the next cycle is started before the write operation is completed, the NAND logic of the command standby signal biscs and the state transition detection signal atdpz is obtained, and the NAND logic is input to the FF circuit 102. By holding the node C at the L level until the internal read command rdpx is input and the holding state is released, the refresh operation can be prevented from being executed. Thus, even after a long write cycle, it is possible to prevent a collision between the read operation and the refresh operation in the next cycle.
[0059]
Next, the command control circuit 400 and the command standby signal generation circuit 500 used in the control system of the semiconductor memory device of the present invention will be described.
FIG. 5 is a circuit configuration diagram of the command control circuit.
[0060]
The command control circuit 400 includes an FF circuit 402 for inputting an active command actpz to one input terminal via an inverter 401, an FF circuit 404 for inputting a read command rdpz to one input terminal via an inverter 403, and an inverter 405. And an FF circuit 406 for inputting the write command wrpz to one input terminal through the FF circuit 406. Each of these FF circuits 402, 404, and 406 is composed of two NAND circuits.
[0061]
Output signals of the FF circuits 402, 404, and 406 are input to one input terminals of NAND circuits 407, 408, and 409, respectively. The other input terminals of the NAND circuits 407, 408, and 409 receive an output signal of a NOR circuit 410 that performs NOR logic of the refresh signal refz and the command standby signal bicsz. Here, an output signal of the NAND circuit 407 is output to the outside of the command control circuit 400 as an internal active command actpx, an output signal of the NAND circuit 408 is an internal read command rdpx, and an output signal of the NAND circuit 409 is an internal write command wrpx. Is done.
[0062]
Output signals of the NAND circuits 407, 408, and 409 are input to the NAND circuit 411, and input to the other input terminals of the FF circuits 402, 404, and 406 via the delay circuit 412 and the inverter 413.
[0063]
Outputs of the NAND circuits 409 and 410 are input to an FF circuit 414 including two NAND circuits, and an output signal of the FF circuit 414 is output to the outside of the command control circuit 400 as a signal writez.
[0064]
The operation of the command control circuit 400 will be briefly described.
When an active command actpz, a read command rdpz, and a write command wrpz (single pulse of H level) are input, if the refresh signal refz and the command waiting signal bicsz are at L level, each of the internal command signals (L level single) is output. (One pulse). However, when any one of the internal command signals is output, the FF circuits 402, 404, and 406 are in the holding state, and no other internal command signals are output. Note that the signal writez is output simultaneously when the internal write command wrpx is output.
[0065]
FIG. 6 is a circuit configuration diagram of the command standby signal generation circuit.
The command standby signal generation circuit 500 has two inverters 501 and 502 and a NOR circuit 503. The signal icsx and the mode signal modez are transmitted through the inverter 501, and the signal writez is transmitted through the inverter 502. This is the configuration that is input to.
[0066]
The output signal of the NOR circuit 503 is output to the outside of the command standby signal generation circuit 500 as a command standby signal bicsz. The command standby signal bicsz is output when the mode signal modez output in the mode in which the write cycle is long is H level, the signal writez indicating that the write operation is being executed is H level, and the signal icsx is L level. , H level.
[0067]
Next, an external configuration of the control system of FIG. 1 will be described.
FIG. 7 is a block diagram showing an external configuration of the control system of FIG.
The control system shown in FIG. 1 has the same reference numerals, and a description thereof will be omitted.
[0068]
The control system of the semiconductor memory device according to the embodiment of the present invention includes an address latch circuit 710, an address decode circuit 720, a bit line control circuit 730, a block selection circuit 740, a word line control circuit, in addition to the control system described in FIG. 750, a word line selection circuit 760, a sense amplifier control circuit 770, and a sense amplifier selection circuit 780.
[0069]
The address latch circuit 710 temporarily latches the input external address ADD.
The address decode circuit 720 decodes the external address ADD and supplies address information to the block selection circuit 740 and the word line selection circuit 760.
[0070]
The bit line control circuit 730 receives a row address strobe signal rasz and an internal read command rdpx or an internal write command wrpx among the internal command signals, and outputs a timing signal blspz for releasing a short circuit of a bit line pair, which will be described later, to block selection. Output to the circuit 740 and the word line control circuit 750.
[0071]
The block selection circuit 740 receives the timing signal blspz and outputs a bit line short control signal brsx for releasing the short circuit of the bit line pair of the selected block based on the address information from the address decode circuit 720. Further, a block selection signal rblkz indicating the selected block is output to the word line selection circuit 760 and the sense amplifier selection circuit 780.
[0072]
The word line control circuit 750 receives the timing signal blspz, generates a word line drive timing signal wlspz, and outputs it to the word line selection circuit 760 and the sense amplifier control circuit 770. In addition, it outputs a word line reset timing signal wlrpz for resetting the word line WL in synchronization with the falling of the row address strobe signal rasz.
[0073]
The word line selection circuit 760 raises the word line WL to the H level at the timing of the word line drive timing signal wlspz based on the input block selection signal rblkz and the word line selection address. Further, the word line WL falls to the L level at the timing of the word line reset timing signal wlrpz.
[0074]
The sense amplifier control circuit 770 outputs a sense amplifier activation timing signal mlez for activating a later-described sense amplifier to the sense amplifier selection circuit 780 after a predetermined time from the input of the word line drive timing signal wlspz. Also, after a predetermined time from the input of the word line reset timing signal wlrpz, the sense amplifier activation timing signal mlez falls to L level.
[0075]
The sense amplifier selection circuit 780 receives the block selection signal rblkz and outputs the sense amplifier drive signals lez and lex at the timing of the sense amplifier activation timing signal mlez.
[0076]
FIG. 8 is a circuit diagram showing a configuration example of a part of the core circuit.
The core circuit has a large number of memories arranged in a matrix and is divided into a plurality of blocks.
[0077]
A part of the core circuit shown in FIG. 8 includes a memory cell 801, bit line precharge transistors 802 and 803, a bit line short transistor 804, a sense amplifier 806, transistors 805 and 807 for controlling the sense amplifier, and a transfer gate. Are comprised of the transistors 808 and 809. The memory cell 801 includes a cell transistor 801a and a cell capacitor 801b, and is connected to one of a pair of bit lines BL and / BL (BL in FIG. 8).
[0078]
The pair of bit lines BL and / BL are connected to internal data buses DB and / DB via transistors 808 and 809, respectively. vpr is a bit line precharge voltage.
[0079]
Hereinafter, the operation of FIGS. 7 and 8 will be described with reference to a timing chart, taking a case where a read operation is performed as an example.
FIG. 9 is a timing chart showing an operation of the semiconductor memory device according to the embodiment of the present invention.
[0080]
When the command decode circuit 200 generates an active command actpz (single pulse of H level), the command control circuit 400 generates an internal active command actpx (omitted in FIG. 9), and the RAS operation control circuit 300 , Raises row address strobe signal rasz to H level. Here, the bit line control circuit 730 detects the rise of the row address strobe signal rasz and outputs the timing signal blspz (single pulse of H level).
[0081]
When detecting the timing signal blspz, the word line control circuit 750 generates a word line drive timing signal wlspz (single pulse of H level) and outputs it to the sense amplifier control circuit 770 and the word line selection circuit 760.
[0082]
On the other hand, upon detecting the timing signal blspz, the block selection circuit 740 sets the bit line short control signal brsx of the selected block to L level based on the address information from the address decode circuit 720, and sets the transistor shown in FIG. Turn off 802, 803, 804. Thereby, the short-circuit state of the bit lines BL and / BL is released.
[0083]
The word line selection circuit 760 raises the word line WL to the H level in synchronization with the rise of the word line drive timing signal wlspz based on the block selection signal rblkz and the address information output from the address decode circuit 720. . When the word line WL rises, data in the memory cell 801 is read out to the bit lines BL and / BL.
[0084]
On the other hand, the sense amplifier control circuit 770 raises the sense amplifier activation timing signal mlez to an H level with a predetermined delay from the rising of the input word line drive timing signal wlspz. Upon detecting this signal, the sense amplifier selection circuit 780 outputs the sense amplifier drive signals lex and lez to the transistors 805 and 807 and turns them on. This activates the sense amplifier 806 and amplifies the potential difference between the bit lines BL and / BL. Thereafter, a column selection signal CL (not shown in FIG. 7) for a column is input from the address decode circuit 720, the transistors 808 and 809 are turned on, and the data amplified by the sense amplifier 806 is transferred to the internal data bus DB, / DB.
[0085]
When data reading is completed and restoration is completed, the command decode circuit 200 sends a precharge command prepz (not shown in FIG. 7) to the RAS operation control circuit 300 in order to perform a precharge operation. And the row address strobe signal rasz falls. Upon detecting this, the word line control circuit 750 generates a word line reset timing signal wlrpz and outputs it to the word line selection circuit 760. Upon detecting this, the word line selection circuit 760 lowers the selected word line WL to L level.
[0086]
Further, in response to the word line reset timing signal wlrpz, the sense amplifier control circuit 770 lowers the sense amplifier activation timing signal mlez to L level after a predetermined time has elapsed. Upon detecting this, the sense amplifier selection circuit 780 outputs the sense amplifier drive signals lex and lez, turns off the transistors 805 and 807, and deactivates the sense amplifier 806.
[0087]
Further, in synchronization with the falling of the sense amplifier activation timing signal mlez, the bit line control circuit 730 generates a bit line short-circuiting timing signal blrpz (not shown in FIG. 7), and Output to the selection circuit 740. The block selection circuit 740 detects this, sets the bit line short control signal brsx to the H level, and short-circuits the bit lines BL and / BL.
[0088]
In the semiconductor memory device according to the first embodiment described above, when a read operation is performed after an operation mode having a long write cycle, the read operation is performed prior to the refresh operation to prevent collision. Was composed.
[0089]
In the operation mode of the semiconductor memory device, a write operation may be performed after a long-cycle write operation. In that case, it is necessary to perform a refresh operation before the next write operation.
[0090]
Here, the operation of the semiconductor memory device according to the first embodiment when a write operation is further performed after a long cycle write operation will be described with reference to a timing chart showing timings of main signals of the refresh / command determination circuit 100a. It will be described using FIG.
[0091]
FIG. 10 is a timing chart for explaining the operation of the semiconductor memory device when writing is performed after a long-cycle write operation.
When the read operation is performed after the write operation, as shown in FIG. 4 described above, when the write operation is completed and the internal read command rdpx is output, the node C becomes H level and the refresh after the write operation is inhibited. Then, the refresh operation is performed after the end of the read operation. For this reason, when the write operation is further performed after the write operation, the node B remains at the H level even if the write operation in the cycle 1 ends and the signal icsx rises to the H level as shown in FIG. The refresh operation cannot be started forever.
[0092]
The semiconductor memory device according to the second embodiment of the present invention improves this point.
Hereinafter, a semiconductor memory device according to a second embodiment of the present invention will be described.
[0093]
FIG. 11 is a block diagram of a part of the control system of the semiconductor memory device according to the second embodiment of this invention.
Note that the same circuits as those in the first embodiment are denoted by the same reference numerals and description thereof will be omitted.
[0094]
This control system includes a refresh / command determination circuit 100b, a command decode circuit 200, an RAS operation control circuit 300, a command control circuit 400, and a command standby signal generation circuit 500. Further, unlike the first embodiment, It has a write command delay circuit 600 that receives an internal write command wrpx and delays it.
[0095]
The refresh / command determination circuit 100b according to the second embodiment, like the refresh / command determination circuit 100a according to the first embodiment, detects a falling edge of the chip enable signal / CE and issues a state transition. It has a function of determining which of the detection signal atdpz and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is later than the refresh request signal srtz, the refresh command refpz is output, and the refresh signal refz is set to the H level. Also, a signal icsx from the RAS operation control circuit 300, an internal read command rdpx from the command control circuit 400, and a command standby signal bicsz from the command standby signal generation circuit 500 are input.
[0096]
Further, different from the first embodiment, the refresh / command determination circuit 100b inputs the internal write command wrpx.
Based on these signals, the relationship between the end of the write operation and the start of the command operation in the next cycle is determined. Here, if the write operation does not end before the start of the command operation in the next cycle, and if the command operation in the next cycle is the write operation, the internal write command wrpx is input, the refresh command refpz is output, and the refresh operation is performed. The refresh operation is performed by setting the signal refz to H level.
[0097]
When the command operation in the next cycle is a read operation, the same operation as in the first embodiment shown in FIG. 1 is performed.
The write command delay circuit 600 delays the internal write command wrpx, and outputs the write command delay signal wrpdx in synchronization with the fall when the refresh signal refz is at the L level. The write command delay signal wrpdx is input to the RAS operation control circuit 300 and the bit line control circuit 730 shown in FIG.
[0098]
FIG. 12 is a circuit diagram of the write command delay circuit.
The write command delay circuit 600 includes an inverter 601, a NAND circuit 602, an FF circuit 603, and two delay circuits 604 and 605. The FF circuit 603 includes NAND circuits 603a and 603b. Further, the write command delay circuit 600 receives the refresh signal refz and the internal write command wrpx, and the refresh signal refz is input to one input terminal of the NAND circuit 602 via the inverter 601. The internal write command wrpx is delayed by the delay circuit 604, and is input to one input terminal of a NAND circuit 603a included in the FF circuit 603. An output signal of the FF circuit 603 output from the NAND circuit 603a is input to the other input terminal of the NAND circuit 602. The output signal of the NAND circuit 602 is input to one input terminal of the NAND circuit 603b included in the FF circuit 603, and is output outside the write command delay circuit 600 as a write command delay signal wrpdx.
[0099]
Next, the operation of the control system shown in FIG. 11 will be described with reference to the timing chart of each signal.
In the following, a case will be described in which the write operation is further performed after the write operation.
[0100]
FIG. 13 is a timing chart illustrating an operation in a control system of the semiconductor memory device according to the second embodiment.
The operation in cycle 1 is the same as that in the first embodiment, and thus the description is omitted, and the description will be started from cycle 2.
[0101]
When the chip enable signal / CE goes low, the operation in cycle 2 starts. At this time, since the write operation in the cycle 1 is continuing, the command standby signal bicsz is at the H level, and the output of the next internal write command wrpx is waited. When the write operation in cycle 1 ends, the command wait signal bicsz goes low, and the internal write command wrpx is output.
[0102]
When the internal write command wrpx in cycle 2 is output, the refresh / command determination circuit 100b according to the second embodiment detects the fall and generates a refresh request signal srttz during the write operation in cycle 1. If so, the refresh command refpz is output, the refresh signal refz is set to the H level, and the refresh operation is performed.
[0103]
When the refresh operation ends and the signal icsx goes high and the refresh signal goes low, the write command delay circuit 600 outputs a write command delay signal wrpdx in synchronization with the fall. This signal is input to the RAS-related operation control circuit 300, and sets the row address strobe signal rasz to the H level to start the write operation in cycle 2.
[0104]
Next, details of the refresh / command determination circuit 100b in the semiconductor memory device of the second embodiment will be described.
FIG. 14 is a circuit configuration diagram of the refresh / command determination circuit in the semiconductor memory device according to the second embodiment.
[0105]
Note that the same parts as those of the refresh / command determination circuit 100a of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
The refresh / command determination circuit 100b of the second embodiment receives the internal write command wrpx, unlike the refresh / command determination circuit 100a of the first embodiment shown in FIG.
[0106]
The internal write command wrpx is input to the NAND circuit 120 together with the internal read command rdpx, and the output is input to one input terminal of the NAND circuit 102b included in the FF circuit 102 via the inverter 121. Further, the inverters 104 and 109 of the refresh / command determination circuit 100a according to the first embodiment are replaced with NAND circuits 122 and 123. One input terminal of the NAND circuits 122 and 123 receives an internal write command wrpx. The configuration has been entered.
[0107]
Here, a node A indicates an output signal of the inverter 108, and a node B indicates an output signal of the NAND circuit 105. Further, a node C indicates an output signal of the FF circuit 102, and a node D indicates an output signal of the NAND circuit 122.
[0108]
Next, the characteristic portion of the operation of the refresh / command determination circuit 100b in FIG. 13 will be specifically described with reference to a timing chart showing timings of main signals. FIG. 15 is a timing chart illustrating the operation of the refresh / command determination circuit in the semiconductor memory device according to the second embodiment.
[0109]
The time axis of the timing chart of FIG. 15 coincides with the timing chart of the control system of FIG.
The operation in cycle 1 is the same as that in the first embodiment, and thus the description thereof will be omitted, and description will be made from cycle 2.
[0110]
When the chip enable signal / CE goes low, the node A goes high in synchronization with the detection of the state transition detection signal atdpz. At this time, since the write operation in the cycle 1 is continuing, the command standby signal bicsz is at the H level, so that the node C also goes to the L level in synchronization with the detection of the state transition detection signal atdpz. Here, as shown in the figure, when the write operation in the cycle 2 is completed and the signal icsx goes to the H level, the node C holds the L level as in the first embodiment.
[0111]
On the other hand, when a single L-level pulse of the internal write command wrpx, which is generated in synchronization with the command standby signal bicsz that becomes L-level at the end of the write operation, is input to the node D in synchronization with this, A single pulse is generated, and an L-level single pulse is generated at node B.
[0112]
The standby refresh command refpz is output in synchronization with the fall of the node B, the refresh signal refz is set to the H level, and the refresh operation is performed.
[0113]
When the refresh operation ends and the signal icsx goes high and the refresh signal refz goes low, the write command delay circuit 600 outputs a write command delay signal wrpdx in synchronization with the fall. This signal is input to the RAS-related operation control circuit 300, and sets the row address strobe signal rasz to the H level to start the write operation in cycle 2.
[0114]
As described above, according to the second embodiment of the present invention, if the write operation is not completed before the start of the write operation in the next cycle, the refresh operation can be performed before the write operation in the next cycle. it can.
[0115]
Note that the configuration outside the control system of the first embodiment shown in FIG. 1 shown in FIG. 7 is also applicable to the control system of the first embodiment. However, in the second embodiment, a write command delay signal wrpdx is input instead of the internal write command wrpx among the internal command signals input to the bit line control circuit 730 of FIG.
[0116]
In the refresh / command determination circuit 100b according to the second embodiment, the case where the write operation is further performed next to the write operation has been described. However, the semiconductor memory device according to the first embodiment has been described. When the read operation is performed after the write operation, that is, after the write operation, the refresh operation in the standby state can be similarly performed after the read operation.
[0117]
Finally, the overall configuration of the semiconductor memory device of the present invention will be described.
FIG. 16 is an overall configuration diagram of the semiconductor memory device.
The semiconductor memory device includes input buffers 906, 907, 908, 909 connected to an address input terminal 901, command input terminals 902, 903, 904, a data input / output terminal 905, an address input terminal 901 and command input terminals 902 to 904, respectively. , A refresh control circuit 910, an input / output buffer 911, an address latch / decode circuit 912, a control circuit 913, a data control circuit 914, a memory cell array 915, and a write amplifier / sense buffer circuit 916.
[0118]
Here, the address latch / decode circuit 912 includes the address latch circuit 710 and the address decode circuit 720 shown in FIG. The control circuit 913 includes the control system according to the first embodiment shown in FIG. 1 or the control system according to the second embodiment shown in FIG. 11, and further includes the control system shown in FIG. Of the present embodiment, each of which does not include the address latch circuit 710 and the address decode circuit 720. Memory cell array 915 includes the configuration shown in FIG. Write amplifier / sense buffer circuit 916 includes a write amplifier and a sense amplifier buffer connected to internal data buses DB and / DB shown in FIG.
[0119]
The refresh control circuit 910 includes a timer and the like, generates a refresh request signal srtz, and outputs the refresh request signal srtz to the control circuit 913. The data control circuit 914 controls data input / output under the control of the control circuit 913.
[0120]
Hereinafter, the operation of the semiconductor memory device shown in FIG. 15 will be briefly described.
When the external address ADD is input to the address input terminal 901, the external address ADD is input to the address latch / decode circuit 912 via the input buffer 906. Thus, the decoded row address and column address are designated, and the word line and the column in the memory cell array 915 are selected.
[0121]
On the other hand, when external control signals (chip enable signal / CE, write enable signal / WE, output enable signal / OE) are input, these are sent to control circuit 913 via input buffers 907, 908, 909. Is entered. Based on these control signals, the above-described write operation and read operation are performed on the memory cell array 915, and data is transferred via the input / output buffer 911 under the control of the data control circuit 914 at the selected address. , Input and output. Refresh is performed by inputting a refresh request signal srtz generated by the refresh control circuit 910 to the control circuit 913.
[0122]
【The invention's effect】
As described above, according to the present invention, after a long write operation, a collision between refresh during standby and a read operation as the next command operation can be prevented, and the write recovery time can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a part of a control system of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining an operation in a control system of the semiconductor memory device according to the first embodiment;
FIG. 3 is a circuit configuration diagram of an example of a refresh / command determination circuit;
FIG. 4 is a timing chart illustrating the operation of the refresh / command determination circuit.
FIG. 5 is a circuit configuration diagram of a command control circuit.
FIG. 6 is a circuit configuration diagram of a command standby signal generation circuit.
FIG. 7 is a block diagram showing an external configuration of the control system of FIG. 1;
FIG. 8 is a circuit diagram illustrating a configuration example of a part of a core circuit.
FIG. 9 is a timing chart illustrating an operation of the semiconductor memory device according to the embodiment of the present invention;
FIG. 10 is a timing chart for explaining an operation of the semiconductor memory device according to the first embodiment in a case where a write is performed after a long cycle write operation;
FIG. 11 is a block diagram of a part of a control system of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 12 is a circuit diagram of a write command delay circuit.
FIG. 13 is a timing chart illustrating an operation in a control system of the semiconductor memory device according to the second embodiment.
FIG. 14 is a circuit configuration diagram of a refresh / command determination circuit in a semiconductor memory device according to a second embodiment;
FIG. 15 is a timing chart illustrating the operation of the refresh / command determination circuit in the semiconductor memory device according to the second embodiment;
FIG. 16 is an overall configuration diagram of a semiconductor memory device.
FIG. 17 is a block diagram of a part of a control system of a conventional DRAM.
FIG. 18 is a timing chart showing an operation of a conventional semiconductor memory device when refreshing is performed first.
FIG. 19 is a timing chart showing an operation of a conventional semiconductor memory device when a read or write operation is performed first.
[Explanation of symbols]
100a refresh / command decision circuit
200 Command decode circuit
300 RAS operation control circuit
400 Command control circuit
500 Command wait signal generation circuit

Claims (5)

In a semiconductor memory device performing an internal refresh operation,
A command control circuit that generates an internal command signal for performing a command operation;
When the write operation is long, a command standby signal generation circuit that generates a command standby signal that waits for the internal command signal that performs the next command operation,
Based on the command standby signal, determine the relationship between the end of the write operation and the start of the next command operation. If the write operation does not end until the start of the next command operation, the next command If the operation is a read operation, a determination circuit that outputs a standby refresh command after the end of the read operation;
A semiconductor memory device comprising: The determination circuit has a flip-flop circuit that takes NAND logic of the state transition detection signal and the command standby signal and holds the NAND logic to inhibit the internal refresh operation. 2. The semiconductor memory device according to claim 1, wherein the holding is released by inputting the internal command signal to be performed. If the next command operation is a write operation, the determination circuit releases the flip-flop circuit that holds refresh inhibition, and outputs the standby refresh command before the start of the write operation. The semiconductor memory device according to claim 2. 4. The semiconductor memory device according to claim 3, further comprising: a write command delay circuit that inputs the internal command signal corresponding to the write operation, and delays the detection so as to detect and output the end of the internal refresh operation. . 2. The semiconductor memory device according to claim 1, wherein when the write operation is completed up to the start of the next command operation, the refresh command in a standby state is output regardless of the next command operation.

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