JPH0287244A - Memory controller - Google Patents

Abstract

PURPOSE:To increase the speed of processing by obtaining the constitution of plural banks for an external memory and providing a control circuit, which inputs and outputs the memory data of the plural banks by one time of a memory access with time division, in a BIT-BLT control device. CONSTITUTION:External memories 2A and 2B are composed of the plural banks and a same high-order address is inputted to each bank. Then, the external memories 2A and 2B can read and write the data of the respective banks with the time division during the period of one time of the memory access by a control signal which is inputted from a BIT-BLT control device 1. In the BIT- BLT control device 1, a control part 5 is provided to generate various timing signals, latches 6A and 6B are provided to respectively take in the data of the respective banks read from the external memories 2A and 2B with the time division and a selector 7 is provided to switch the data in order to write the data to the respective banks of the external memories 2A and 2B with the time division. Thus, an interleave access is executed to the respective memories. Thus, the processing can be executed at the high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory control device using BIT-BLT control for high-speed data transfer.

(Description of Prior Art) BIT-BLT is bit boundary bl
ocktrans is an abbreviation for "ar" and refers to the function of specifying a block area in memory bit by bit and transferring it to another location.

Conventionally, Di
rect Memory Access (hereinafter referred to as DMA)
) In a memory system having a BIT-BLT controller that performs transfer, an external memory with a single bank configuration is often used in the same data bits as the BIT-BLT controller has. In such a memory system, the DMA by the BIT-BLT controller is
During transfer, the amount of data (number of bits) that can be handled in one memory access depends on bit t9 of the data bus of the BIT-BLT control device and external memory. For example, if a BIT-BLT control device with 32 bits of data bits is used, the external memory will inevitably have a configuration of 1132 bits of data bits, and the amount of data that can be handled in one access will also be 32 bits.
It becomes 2 bits. In this example, external memory is
The memory access timing when configured using M is shown in FIGS. 4 and 5.

Figures 4 and 5 show that external memory reads and writes by the BIT-BLT controller require 2 basic clocks per 32 bits.

(Problems to be Solved by the Invention) In the conventional system, the data transfer rate is determined by the amount of data that the BIT-BLT control device can handle in one access, that is, the data bit [i].

In order to further improve the performance, it is possible to increase the number of data bits in the BIT-BLT control device and external memory, or to speed up the basic clock. There were problems such as speed limits.

The present invention has been made in view of the above-mentioned drawbacks, and has an external memory configured in multiple banks, and a control circuit that inputs and outputs memory data of multiple banks in a time-sharing manner in a single memory access within a BIT-BLT control device. By providing
It is an object of the present invention to provide a memory control device that can perform MA transfer faster than conventional methods.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an external memory composed of a plurality of memory banks, and a DMA for data blocks on the external memory.
In memory data composed of a DMA control device that performs transfer, each bank of the external memory is given an upper address generated by the DMA control device, and bank select and memory control signals are generated based on the lower address to control each bank. means for accessing data in a time-division manner; a memory control section for generating various timing signals including the bank select signal and memory control signal; It consists of a latch and a select that switches data in order to time-divisionally write data into each bank of the external memory.

(Function) As described above, the present invention is composed of a plurality of memory banks, each bank is manually supplied with the same upper address, and one memory access is performed by a control signal manually supplied from the BIT-BLT control device. An external memory is provided that can read and write data in each bank in a time-division manner during the period, and a control unit that generates various timing signals is provided within the BIT-BLT control device, and a control unit that can read and write data in each bank in a time-division manner from the external memory. Interleaf access is performed to each part's memory by providing latches for taking in data respectively, and selectors for switching data in order to time-divisionally write data to each bank of external memory. As shown in the timing diagrams in Figures 2 and 3, external memory read and write by the BIT-BLT control device requires 3 basic clocks per 64 bits, compared to the conventional method shown in Figures 4 and 5. It is clear that the transfer speed improves.

As a result, processing speed can be increased without increasing the data bit width between the BIT-BLT control device and external memory or speeding up the basic clock for operation.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a BIT-BLT control device, which is a unit that reads and writes data to and from an external memory. 2A to 2B are external memories, and multiple D
It uses a RAM and is composed of two banks, each having 32 bits of data [11.3 is an address generation section, which generates addresses to be output to the external memories 28 to 2B. 4 is a data generation section, which generates data to be written to the external memories 2A to '2B. It also takes in data read from the external memories 2A to 2B. A control section 5 generates control signals to be output to the external memories 2A to 2B and others.

Numerals 6A and 6B are latches that latch each 32-bit data read from the external memories 2A and 2B. Reference numeral 7 denotes a selector, which time-divisionally switches the 32-bit data to be output to each external memory 2A, 2B. 8A
is an output buffer, and D created by the address generator 3
Outputs the ROW address to RAM to the outside of the unit.

8B is an output buffer 7, which outputs the COLUMN address for the DRAM created by the address generation section 3 to the outside of the unit. 9 is a bidirectional buffer, and external memory 2A
2B and the data generation unit 4. Reference numeral 10 denotes an output buffer, which outputs a bank select signal for validating the data of each external memory 2A, 2B. 11 is an output buffer, Row Address 5tro to external memory 2A12B
be (hereinafter referred to as RAS) signal, Column Address
ss 5trobe (hereinafter CAS) signal, Write
e Enable (WE) signal and other DRAMs
Outputs control signals. 12 is a selector;
Memory access unit 1 to ROW address, COL
Switch UMN address.

FIGS. 2 and 3 are diagrams cited to explain the operation of the embodiment of the present invention, and show read/write timings.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. To explain the memory read operation in Fig. 1, first the BI
A memory address is generated by an address generator 3 inside the T-BLT control device 1, and is input to the selector 12 through output buffers 8A and 8B. In selector 12, D
ROW address to be supplied to RAM (abbreviation in the figure “
R'') and Co1usn address (abbreviated as 'C'' in the figure) are multiplexed and output to external memories 28 to 2B. −
On the other hand, the DRAM control signal generated by the control section 5 inside the BIT-BLT control device 1 is manually input to the external memories 2A and 2B through the output buffer 11. Further, a bank select signal for validating data for each node in the external memories 2A and 2B is manually input to the external memories 2A and 2B through the output buffer 10. With this DRAM address, control signal, and bank select signal, only reading by the two external memories is enabled, and data is taken into latch 6A through bidirectional buffer 9.

Next, by switching the bank select signal output from the output buffer 710, only the read data of the external memory 2B becomes valid, and the data is taken into the latch 6B through the bidirectional buffer 9. As described above, 64 bits can be read in one memory access.

During a memory write operation, an address is output in the same manner as during the read operation, and write data is sent from the data generation unit 4 through the selector 7 and the bidirectional buffer 9 to the external memories 2A and 2B in that order according to the bank select signal. Output in parts. As a result of the above, in one memory access, 6
Write 4 bits. This transfer is then continued continuously.

[Effects of the Invention] As explained above, according to the present invention, processing can be performed without using techniques such as increasing the bit width between the BIT-BLT control device and external memory or speeding up the basic clock for operation. can be accelerated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are timing charts showing the operation of the embodiment of the present invention,
4 and 5 are timing charts showing the operation of the conventional example. DESCRIPTION OF SYMBOLS 1... BIT-BLT control device, 2... External memory, 3... Address generation part, 4... Data generation part, 5
...Control section, 6...Latch circuit, 7, 12
... Selector, 8.9, 10.11... Buffer. Applicant's Representative Patent Attorney Suzue Takehiko Atsushi Diagram

Claims (1)

[Claims] In a memory system consisting of an external memory composed of a plurality of memory banks and a DMA control device that performs DMA transfer to data blocks on this external memory, each bank of the external memory has an upper-level memory generated by the DMA control device. A means for giving an address and generating bank select and memory control signals based on the lower address to access data in each bank in a time-sharing manner, and a memory control that generates various timing signals including the bank select signal and memory control signal. It is equipped with a latch for capturing the data of each bank read from the external memory in a time-division manner, and a select for switching the data in order to write the data to each bank of the external memory in a time-division manner. A memory control device characterized in that it performs interleaf access to memory.