JPH0371484A - Dynamic ram - Google Patents

Abstract

PURPOSE:To provide a sequential access function without adding any special constitution by discontinuing the use of a refresh-only counter and controlling a row address counter and a column address counter by utilizing originally provided control timing. CONSTITUTION:The dynamic RAM consists of a memory cell array 1, the row address counter 2, a 1st multiplexer 3 which selects an external row address signal and the output of the row address counter 2, a row address decoder 4, the column address counter 5, a 2nd multiplexer 6 which selects an external column address signal and the output of the column address counter 5, a column address decoder 7, and an I/O buffer 8. The RAM is equipped with no refresh- only counter and refreshed by the row address counter 2. Timing control over the row address counter 2 and column address counter 5 is facilitated by utilizing the originally provided control timing. Consequently, the sequential access function is provided by the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION B) Industrial Application Field The present invention relates to a dynamic RAM provided with a sequential access function.

(σ) Conventional technology Most conventional sequential access memories are designed for image information processing, and have large chip sizes, such as having multiple data registers in the data input/output section to support high-speed operation. It's also expensive. Therefore, the general-purpose Dynamic R
AM is used.

First, please refer to Figure 2 for image information! A sequential/random access, ginoual data memory designed for Il processing is described.

This memory chip (20) includes a memory cell array (21
), address counter (22), refresh counter (23), multiplexer (24), row address decoder (25), m 1 to 4 S/P decoders (26° to (26,), 4 sets of m-stage shift registers ( 27,)～
(274), and a 4t01P/S decoder (28), which operates as a sequential access memory when the row address decoder (25) is connected to the address counter (22) by the multiplexer (24), and the external address hole When connected to 0 to A1, it operates as a random access memory, and further connected to a refresh counter (23) to perform a refresh operation.

Serial data from four memo cells including a selected memory cell (not shown), which is input to the 1to4S/P decoder (26+), is transferred to four sets of m-stage shift registers (27,
) to (2L), respectively, and the serial data from the four memory cells input to the 1to4S/P decoder (261) are input to the 27.degree. bits of the shift register, respectively. t ~ 274° bits, and so on, and 4 of these shift registers (27,) to (27a)
The bit output is serially converted by a 4toI P/S decoder (28) and output.

Although this type of memory is capable of high-speed operation, it has a complex circuit configuration as shown in the figure, and is not suitable for applications such as audio recording.

Next, an example of a FIIi sequential access memory system using a general-purpose dynamic RAM will be described with reference to FIG.

The general-purpose dynamic RAM chip (30) converts the row address signal and column address signal inputted in a time-division manner to the memory cell array (31).
), a row address decoder (3
4), column address decoder (35), refresh counter (33), multiplexer (32) for selecting refresh counter output and external row address signal, and I
It consists of 10 buffers (36). Note that a row address counter is not provided.

In addition, the external circuit is a multi-address type dynamic R
Two counters (37) (38) adapted to the AM address input and generating sequential address signals
, a multiplexer (39), and a shift register (40) that converts data from parallel to serial.

In this system, each time the count value of the external circuit counter (37) is incremented by 1, the other counter (37) is incremented by 1.
38) is incremented from O to full count,
Moreover, each time another counter (38) is incremented by 1, R A S ' is supplied to the dynamic RAM.
(row address 5trobe), CA
S” (column address 5trobe), the output of the counter (37) and the counter (38)
The outputs of are alternately addressed to the dynamic RAM (30).

(...) Problems to be Solved by the Invention When using a multi-address type dynamic RAM as a sequential access memory, it is natural to multiplex the circuits that generate sequential row address confirmation and column address signals and their outputs. However, the timing control of these circuits is more complicated.

The present invention is characterized in that a dynamic memory does not require a refresh cycle when it operates as a sequential access memory, and that a multi-address type dynamic RAM is inherently suitable for controlling row address signal and column address signal generation circuits. The purpose of this method is to provide a dynamic RAM with a sequential access function using a relatively simple configuration.

(d) Means for Solving the Problems The dynamic RAM of the present invention includes a memory cell array,
A row address counter that operates as a refresh counter in random access mode, a first multiplexer that selects an external row address signal and the output of the row address counter, a row address decoder, a column address counter that operates in sequential access mode, and an external column. It consists of a second multiplexer that selects an address signal and the output of a column address counter, and a column address decoder.

(,1) Effect The configuration in which the row address counter and column address counter for sequential access are built into the dynamic RAM is a multi-address type dynamic RAM.
To simplify the timing control of a row address counter and a column address counter by making it possible to use control timing that is inherently provided in M and not outputted from the outside.

In addition, by using the row address counter as a refresh counter in random access mode,
ll 戊 is simplified.

(f) Example Hereinafter, the present invention will be explained in detail with reference to FIG.

The dynamic RAM of the present invention has a memory cell array (1)
, a row address counter (2), a first multiplexer (3) for selecting an external row address signal and the output of the row address counter (2), a row address decoder (4),
Column address counter (5), external column address signal and column address counter (5) select the output of the second
multiplexer (6), column address decoder (7)
), and an I10 buffer (8). Note that a refresh-only counter is not provided, and refresh is performed by a row address counter (2).

Note that when comparing the dynamic RAM of the present invention and a general-purpose dynamic RAM in terms of constituent elements, the dynamic RAM of the present invention has a column address counter (5) and a second column address counter (5).
The advantages of using the dynamic RAM of the present invention to implement a sequential access memory system are:
That is, there are obvious advantages such as eliminating the need for one address counter and timing circuit.

Next, the operation of the embodiment will be explained separately in random access mode and sequential access mode.

1. Random access mode Dynamic R of the present invention in random access mode
In the AM, the first multiplexer (3) and the second multiplexer (6) selectively output the row address signal and column address signal input from the outside in a time-division manner to the row address decoder (4) and column address decoder (7), respectively. controlled to do so. Therefore, the general-purpose dynamic R
Similar to AM, activation of RAS” and CAS”
The row address signal and column address signal are taken in to select the word line and bit line, and the I10 buffer (8)
Input and output data via.

Further, by setting CAS to a low level in advance at the falling edge of RAS, the row address counter (2) generates a refresh address and refreshes each word line.

2. Sequential access mode In the dynamic RAM of the present invention in sequential access mode, the first multiplexer (3) and the second multiplexer (6) output the output of the row address counter (2) and the output of the column address counter (5). They are controlled to selectively output to the row address decoder (4) and column address decoder (7), respectively.

Each word line is sequentially selected by counting the count value of the row address counter (2) from O to the full count, and the count value of the column address counter (5) is incremented every time the row address counter (2) counts full. As a result, the data of the memory cells associated with the bit line specified by the column address counter (5) are read out in order. Therefore, since the row address counter (2) makes a full count for each count value of the column address counter (5), a refresh cycle is not necessary in this sequential access mode. Note that for data writing in this mode, J-tomodified write is used in which writing is performed following a read cycle.

(G) Effects of the Invention As described above, according to the present invention, the refresh-only counter is eliminated and the row address counter and column address counter are By being able to control the dynamic RAM, a sequential access function can be provided to the dynamic RAM without adding any special configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a conventional image information processing memory, and Fig. 3 is a block diagram of a sequential access memory system using a general-purpose dynamic RAM. be. DESCRIPTION OF SYMBOLS 1... Memory cell array, 2... Row address counter (refresh counter), 3... First multiplexer, 4... Row address decoder, 5...
・Column address counter, 6... Second multiplexer, 7... Column address decoder, 8...
...1/'0 batshua.

Claims (1)

[Claims] (1) A memory cell array, a row address counter that operates as a refresh counter in random access mode, a first multiplexer that selects an external row address signal and the output of the row address counter, and a row address decoder that operates in sequential access mode. a column address counter; and a second multiplexer and column address decoder that select an external column address signal and the output of the column address counter.