JPH0282038U - - Google Patents
Info
- Publication number
- JPH0282038U JPH0282038U JP1988162932U JP16293288U JPH0282038U JP H0282038 U JPH0282038 U JP H0282038U JP 1988162932 U JP1988162932 U JP 1988162932U JP 16293288 U JP16293288 U JP 16293288U JP H0282038 U JPH0282038 U JP H0282038U
- Authority
- JP
- Japan
- Prior art keywords
- film carrier
- overlapping
- lead terminals
- same plane
- conductive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Description
第１図は、本考案のフイルムキヤリヤを表す説
明図であり、第１図ロはフオーミング前の断面説
明図、第１図ハは、フオーミング後の断面説明図
である。第２図イ〜リは、本考案のフイルムキヤ
リヤの製造例を行程順に示す断面説明図である。
第２図ヌ，ルはリード端子のフオーミング方法を
表す断面説明図である。第３図はイ〜ヌは、本考
案のフイルムキヤリヤの他製造例を行程順に示す
説明図である。第４図は、従来及び本考案のフイ
ルムキヤリヤのリード断面の比較を示す説明図で
ある。第５図は、従来のフイルムキヤリヤの断面
説明図である。
FIG. 1 is an explanatory diagram showing the film carrier of the present invention, FIG. 1B is a cross-sectional explanatory view before forming, and FIG. 1C is a cross-sectional explanatory view after forming. FIGS. 2A to 2I are explanatory cross-sectional views showing an example of manufacturing the film carrier of the present invention in the order of steps.
FIGS. 2A and 2B are cross-sectional explanatory views showing a method of forming lead terminals. FIGS. 3A to 3C are explanatory diagrams illustrating another manufacturing example of the film carrier of the present invention in the order of steps. FIG. 4 is an explanatory diagram showing a comparison of the lead cross sections of the conventional film carrier and the film carrier of the present invention. FIG. 5 is an explanatory cross-sectional view of a conventional film carrier.
Claims (1)
該導体回路のリード端子が重なり合う事なく同一
平面に配置されてなる事を特徴とするフイルムキ
ヤリヤ。 ２ 導体回路が絶縁フイルムの片面に設けられた
フイルムキヤリヤを、請求項１記載のフイルムキ
ヤリヤの少なくとも片面に貼り合わせ、リード端
子が重なり合う事なく同一平面に配置されてなる
事を特徴とする多層フイルムキヤリヤ。[Claims for Utility Model Registration] 1. A conductor circuit is provided on both sides of an insulating film,
A film carrier characterized in that lead terminals of the conductive circuit are arranged on the same plane without overlapping. 2. A film carrier having a conductive circuit provided on one side of an insulating film is bonded to at least one side of the film carrier according to claim 1, and the lead terminals are arranged on the same plane without overlapping. Multilayer film carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988162932U JPH0282038U (en) | 1988-12-14 | 1988-12-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988162932U JPH0282038U (en) | 1988-12-14 | 1988-12-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282038U true JPH0282038U (en) | 1990-06-25 |
Family
ID=31447208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988162932U Pending JPH0282038U (en) | 1988-12-14 | 1988-12-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282038U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09306947A (en) * | 1996-05-10 | 1997-11-28 | Nec Corp | Semiconductor device |
| JP2005079581A (en) * | 2003-09-03 | 2005-03-24 | Samsung Electronics Co Ltd | Tape substrate, semiconductor chip package using tape substrate, and lcd device using semiconductor chip package |
-
1988
- 1988-12-14 JP JP1988162932U patent/JPH0282038U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09306947A (en) * | 1996-05-10 | 1997-11-28 | Nec Corp | Semiconductor device |
| JP2005079581A (en) * | 2003-09-03 | 2005-03-24 | Samsung Electronics Co Ltd | Tape substrate, semiconductor chip package using tape substrate, and lcd device using semiconductor chip package |
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