JPS59121860U - printed wiring board - Google Patents
printed wiring boardInfo
- Publication number
- JPS59121860U JPS59121860U JP1983013824U JP1382483U JPS59121860U JP S59121860 U JPS59121860 U JP S59121860U JP 1983013824 U JP1983013824 U JP 1983013824U JP 1382483 U JP1382483 U JP 1382483U JP S59121860 U JPS59121860 U JP S59121860U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- resistor
- utility
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図乃至第３図は従来における基板を説明するための
図面であって、第１図は単層の場合の断面図、第２図は
積層の場合の断面図、第３図はレーザトリミングを説明
する平面図、第４図乃至第７図は本考案にかかる印刷配
線基板の実施例を説明するための図面であって、第４図
は第１実施例の断面図、第〉図は第２実施例の断面図、
第６図Ｉ乃至■は第３実施例の製作工程図、第７図は第
６図■の■−■線断面図である。
なお、図面中において用いられている符号において、３
４．４Ｂ、５４．６３・・・・・・抵抗層、Ｍ。
５８・・・・・・開口部、３５． ４９． ５５． ６
４・・・・・・高融点ガラス層である。Figures 1 to 3 are drawings for explaining conventional substrates, where Figure 1 is a cross-sectional view of a single layer, Figure 2 is a cross-sectional view of a laminated layer, and Figure 3 is a laser trimming diagram. FIG. 4 to FIG. 7 are diagrams for explaining an embodiment of the printed wiring board according to the present invention, FIG. 4 is a sectional view of the first embodiment, and FIG. A sectional view of the second embodiment,
FIGS. 6I to 6 are manufacturing process diagrams of the third embodiment, and FIG. 7 is a sectional view taken along the line 2--2 of FIG. 6. In addition, in the symbols used in the drawings, 3
4.4B, 54.63...Resistance layer, M. 58...Opening, 35. 49. 55. 6
4...High melting point glass layer.
Claims (1)
線基板において、前記抵抗体上に設けられる絶縁層に、
開口部が形成されることを特徴とする印刷配線基板。 ２ 実用新案登録請求の範囲第１項において、前記絶縁
層が高融点ガラス層であることを特徴とする印刷配線基
板。[Claims for Utility Model Registration] 1. In a printed wiring board in which at least a resistor is printed on a substrate, an insulating layer provided on the resistor,
A printed wiring board characterized in that an opening is formed. 2 Utility Model Registration The printed wiring board according to claim 1, characterized in that the insulating layer is a high melting point glass layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983013824U JPS59121860U (en) | 1983-02-02 | 1983-02-02 | printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983013824U JPS59121860U (en) | 1983-02-02 | 1983-02-02 | printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59121860U true JPS59121860U (en) | 1984-08-16 |
| JPH0219980Y2 JPH0219980Y2 (en) | 1990-05-31 |
Family
ID=30145201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983013824U Granted JPS59121860U (en) | 1983-02-02 | 1983-02-02 | printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121860U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020021948A (en) * | 2015-02-17 | 2020-02-06 | ローム株式会社 | Resistor and manufacturing method thereof |
-
1983
- 1983-02-02 JP JP1983013824U patent/JPS59121860U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020021948A (en) * | 2015-02-17 | 2020-02-06 | ローム株式会社 | Resistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0219980Y2 (en) | 1990-05-31 |
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