JPH0262113A - Buffer circuit - Google Patents

Abstract

PURPOSE:To suppress a through current flowing through a bus between a power source and a ground to minimum, to reduce the energy consumption and to obtain the buffer circuit optimum to a CMOS gate array and so forth by stopping that respective transistors attain simultaneously the on condition when the level of an input signal is changed. CONSTITUTION:When an input signal voltage I is changed from a low level to a high level, a signal voltage I bar inverted by an inverter INV is changed to a low level, simultaneously, the potential of a connecting point (a) of N channel transistors N1 and N2 is also changed from low to high and a transistor N2 is made from the on condition to the off condition. Next, based on the level change of the I bar and the potential change of a contact (a), a P channel transistor P1 is turned on, a transistor N1 is turned off and an output voltage 'O' bar is changed from low to high. Next, when the input signal voltage is changed from high to low, the reverse action is executed, the voltage 'O' bar is made into the low level, a through current and the 'O' bar are suppressed to the minimum limit.

Description

[Detailed Description of the Invention] (Summary) This invention relates to a buffer circuit that shapes the waveform of an input signal and outputs it.The purpose of this invention is to prevent the formation of a DC bus on the output side and the flow of through current when the input signal level changes. , an input terminal is supplied to one end of the P-channel transistor, the input voltage is supplied to one end of the first N-channel transistor via a second N-channel transistor, and the P-channel transistor and the first . An inverted voltage of the input voltage is supplied to each gate of the second N-channel transistor, and the other ends of the P-channel transistor and the first N-channel transistor are commonly connected, and the connection point becomes an output terminal. It is configured as follows.

[Industrial application field]

The present invention relates to a buffer circuit that shapes the waveform of an input signal and outputs it, and particularly to a buffer circuit that prevents through current from flowing to the output side when the input signal level changes.

[Conventional technology]

FIG. 4 shows an example of a buffer circuit as a conventional technique, in which a CMOS inverter 11 consisting of a P-channel transistor P1" and an N-channel transistor N1",
By cascade-connecting a CMOS inverter I2 consisting of a P-channel transistor P2° and an N-channel transistor N2'', the input signal I is waveform-shaped and taken out as an output signal.

Such a CMO3 semiconductor device is characterized by low power consumption, but its output circuit consists of a PMO3l-transistor and an N
Since it is configured in a pair with Mo5 transistor, the power supply and ground (
A DC bus is generated between V oo V ss), and as shown in FIG. shows. In particular, in the output circuit of the inverter 2 in the latter stage, the driving ability of the transistor that drives the output circuit is increased in consideration of the wiring capacitance on the load side. There was a problem in that the current also increased, leading to an increase in power consumption.

[Problem to be solved by the invention] The present invention has been made to solve the problem,
A DC bus is formed on the output side to prevent through current from flowing when the input signal level changes, thereby reducing power consumption.

[Means for Solving the Problems] In order to solve the above problems, according to the present invention, ■) An input voltage is supplied to one end of the channel transistor, and a second voltage is supplied to one end of the first N-channel transistor. The input voltage is supplied through an N-channel transistor, and 3
1 p-channel I transistor and the first. second N
A buffer circuit is provided in which an inverted voltage of the input voltage is supplied to each gate of the channel transistor, and the other ends of the P-channel transistor and the first N-channel transistor are commonly connected, and the connection point is an output terminal. provided.

[Function] According to the above configuration, when the input signal changes from a low level to a high level, the inverted voltage is applied to the gate of each of the transistors, so that the second N-channel transistor is first turned off. Then, the P-channel transistor is turned on and the first N-channel transistor is turned off, so that the high-level input signal is transmitted to the output side.

On the other hand, when the input signal changes from high level to low level, the inverted voltage is applied to the gate of each transistor, first turning on the second N-channel transistor, and then turning on the second N-channel transistor. By the time the No. 1 N-channel transistor is turned on, the P-channel transistor is turned off, and a low-level input signal is transmitted to the output side.

In this way, it is possible to prevent each transistor from turning on simultaneously when the level of the input signal changes, thereby minimizing the current passing through each transistor.

〔Example〕

FIG. 1 shows a buffer circuit as an embodiment of the present invention, in which an input voltage I is supplied to one end (source side) of a P-channel transistor N1, and one end of a first N-channel transistor N1. (source side) has a second N
The input voltage l is supplied via the channel transistor N2, and the P-channel transistor P1 and the first . An inverted voltage T of the input voltage I is supplied to each gate of the second N-channel transistors Nl and N2 via an inverter INV, and the other terminals of the P-channel transistor P1 and the first N-channel transistor N1 (drain side) are commonly connected, and an output voltage of 100 is taken out from this connection point.

FIG. 2 is a timing chart showing changes in signal levels in each section shown in FIG. 1. First, when the input signal voltage ■ changes from low level to high level, the signal voltage The bottom is the low level (see Figure 2 ■). Further, the potential at the connection point a between the N-channel transistors Nl and N2 changes from low level to high level, and first, the transistor N2 changes from the on state to the off state (see FIG. 2).

Next, based on the level change under the inverted voltage and the potential change at the connection point a, the P-channel transistor P1 is turned on, and the N-channel transistor N1 is turned on.
turns off, and the output voltage -07 changes from low level to high level (see Figure 2).

Next, when the input signal voltage changes from high level to low level, the signal voltage T inverted by the inverter INV becomes high level (see FIG. 2). As a result, the N-channel transistor N2 first changes from the off state to the on state, and the potential at the connection point a changes from a high level to a low level (see FIG. 2). Based on the level change of the inversion voltage T and the potential change of the connection point a, the P-channel transistor P1 is turned off and the N-channel transistor N1 is turned on. In this case, by providing the transistor N2, the timing at which the transistor N1 is turned on is delayed, and the transistor P1 is turned on after the transistor N2 is turned on and before the transistor N1 is turned on. When the transistors N1 and N2 are turned on, the output voltage -0- changes from high level to low level (see FIG. 2).

In this way, the transistors are prevented from turning on at the same time when the level of the input signal changes, and thereby the current flowing through each transistor can be suppressed to a minimum.

FIG. 3 shows the 1-0 characteristic and I-I when the input signal level changes, obtained by the circuit shown in FIG. 1.

This shows the characteristic that almost no through current flows when the input signal level changes.

〔Effect of the invention〕

According to the present invention, when the input signal level changes, the through current flowing through the bus between the power supply and the ground can be suppressed to a minimum, thereby sufficiently reducing power consumption. A suitable buffer circuit can be used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a buffer circuit as an embodiment of the present invention, FIG. 2 is a timing diagram showing potential changes in various parts when the input signal level changes in the circuit of FIG. 1, and FIG. , a characteristic diagram when the input signal level changes in the circuit of FIG. 1, FIG. 4 is a diagram illustrating a buffer circuit as a conventional technology, and FIG. 5 shows a characteristic diagram when the input signal level changes in the circuit of FIG. 4. It is a characteristic diagram. (Explanation of symbols) Nl, N2. Nl', N2': N-channel transistor, Pi, Pi", l'2': P-channel transistor, TNV: inverter.

Claims (1)

[Claims] 1. An input voltage is supplied to one end of the P-channel transistor, and the input voltage is supplied to one end of the first N-channel transistor via a second N-channel transistor, and the input voltage is supplied to one end of the P-channel transistor and the first N-channel transistor. , an inverted voltage of the input voltage is supplied to each gate of the second N-channel transistor, and the other ends of the P-channel transistor and the first N-channel transistor are commonly connected, and the connection point is an output terminal. A buffer circuit characterized in that: