JP3052433B2 - Level shift circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a level shift circuit 12 is used for converting logic signal levels of a 5V logic circuit 11 and a 12V logic circuit 13 in an integrated circuit 30.
Normally, when the voltage of the 5V system decreases, the input signal SI is also output by the 5V system POC (power-on-clear) circuit 14 which outputs the reset signal SR for initialization.
O is also fixed at the “L” level.

The power supply 12V of the conventional level shift circuit 12
As shown in FIG. 4, the system circuit 20a includes a MOS inverter 1 in which an N-type MOS transistor N1 and a P-type MOS transistor P1 are cascaded via a common drain terminal D1.
And a MOS inverter 2 having the same structure as
It is connected in parallel between the V power supply terminal T12 and the ground potential point G.

The two common drain terminals D1 and D2 are connected to the gate terminals G2 and G1 of P-type transistors P2 and P1, respectively, which are upper stages of the opposing MOS inverters 1 and 2, respectively.
To perform a cross feedback operation. Gate terminals GN1 and GN2 of the lower-stage N-type transistors N1 and N2 are connected via the inverter I of the power supply 5V system circuit 10.

Next, the operation of the circuit will be described. When the input signal SI supplied from the 5 V logic circuit 10 is at "L" level, the transistors N1 and P2 of the cross pair are turned off and the transistors N2 and P1 are turned on. So the output terminal TO
Output signal SO attains an "L" level.

On the other hand, when the input signal SI is at the "H" level of the 5V system, N1 and P2 of the transistor pair are turned off and N2 and P1 of the transistor pair are turned on. Level, and the input signal “H” 5V is level-shifted to “H” 12V of the 12V power supply.

[0007]

In this conventional level shift circuit, when the potential of the low-voltage power supply does not rise sufficiently at the time of turning on, the low-potential inverter inserted between the gate terminals of the lower-stage MOS transistor. Does not work,
There is a problem that the lower MOS transistors of both MOS inverters are turned off at the same time and the operation becomes unstable.

An object of the present invention is to provide a level shift circuit which operates stably even when power is turned on.

[0009]

A level shift circuit according to the present invention is connected in parallel between a high-voltage power supply terminal and a ground potential point, and each common dollar-in terminal is connected to the gate terminal of an upper stage transistor opposed to each other. In a level shift circuit having two MOS inverters connected in a cross feedback connection and inputting a low-level signal to a gate terminal of a lower transistor and outputting a high-level signal from the common drain terminal, an output side of the high-level signal A small current bypass circuit is added between the common drain terminal and the ground potential point.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention. The power supply 12V system circuit 20 of the conventional level shift circuit shown in FIG.
A current bypass circuit 3 having a high resistance R1 is added between the common drain terminal D2 of the output side MOS inverter 2 and the ground potential point G.

Next, the operation of the circuit will be described. During normal operation, when the input signal SI is "L", the N
1 and P2 are off, and N2 and P1 of the transistor pair are on, so that the output signal SO becomes "L" and
When the input signal SI is "H", N1, P
2 is turned on and the transistors N2 and P1 of the transistor pair are turned off, so that the output signal SO becomes "H" at the level of VD which is the first high potential side.

If the power supply voltage supplied to the inverter I does not reach 5 V, the inverter I does not operate. Therefore, even when the N-type MOS transistors N1 and N2 are off simultaneously, the current bypass circuit 3 is provided. Output terminal T
The potential of O is fixed in the initial direction “L”.

The current bypass circuit 3 is shown in FIGS. 2 (a) and 2 (b).
The same operation is performed in the case of the constant current bypass circuits 3a and 3b shown in FIG. The constant current bypass circuits 3a and 3b of this embodiment can set the bypass current more stably than the current bypass circuit 3 of FIG.

[0014]

As described above, according to the present invention, a current bypass circuit is added between the ground potential point and the output terminal. This has the effect of stabilizing the output signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIGS. 2A and 2B are circuit diagrams of another embodiment of the current bypass circuit of FIG. 1;

FIG. 3 is a block diagram of an example of an integrated circuit having a level shift circuit.

FIG. 4 is a circuit diagram of an example of a conventional level shift circuit.

[Explanation of symbols]

 1, 2 MOS inverter 3 Current bypass circuit 3a, 3b Constant current bypass circuit 10 Power supply 5V system circuit 20 Power supply 12V system circuit N1 to N5 N-type MOS transistor P1, P2 P-type MOS transistor G Ground potential point T12 12V power supply terminal I Inverter D1, D2 Common drain terminal R1 High resistance G1, G2 Gate terminal SI input signal SO output signal

Claims (2)

(57) [Claims] 1. Two MOS inverters are connected in parallel between a high-voltage power supply terminal and a ground potential point, and each common drain terminal is cross-feedback-connected to a gate terminal of an upper transistor opposed to each other. A level shift circuit that inputs a low-level signal to the gate end of the lower transistor and outputs a high-level signal from the common drain end;
A level shift circuit, wherein a minute current bypass circuit is added between the common drain terminal on the output side of the high-level signal and the ground potential point. 2. The level shift circuit according to claim 1, wherein said current bypass circuit has a transistor constant current circuit.