JPH0258346U - - Google Patents
Info
- Publication number
- JPH0258346U JPH0258346U JP1988137144U JP13714488U JPH0258346U JP H0258346 U JPH0258346 U JP H0258346U JP 1988137144 U JP1988137144 U JP 1988137144U JP 13714488 U JP13714488 U JP 13714488U JP H0258346 U JPH0258346 U JP H0258346U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- transistor
- mos
- active layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Description
第１図は一実施例を示す平面図、第２図は第１
図のＡ―Ａ線位置での断面図、第３図Ａから同図
Ｆは一実施例の製造方法を示す断面図、第４図は
他の実施例を示す断面図である。
４……下部電極、６……下部ゲート酸化膜、８
……活性層、１０……ソース、１２……ドレイン
、１４……上部ゲート酸化膜、１６……上部電極
。
FIG. 1 is a plan view showing one embodiment, and FIG. 2 is a plan view showing one embodiment.
3A to 3F are sectional views showing a manufacturing method of one embodiment, and FIG. 4 is a sectional view showing another embodiment. 4... Lower electrode, 6... Lower gate oxide film, 8
...Active layer, 10... Source, 12... Drain, 14... Upper gate oxide film, 16... Upper electrode.
Claims (1)
を介して第１のゲート電極が設けられて第１のＭ
ＯＳトランジスタが形成されており、前記半導体
活性層の他方の側に第２のゲート絶縁膜を介して
第２のゲート電極が設けられて第２のＭＯＳトラ
ンジスタが形成されており、かつ、第１のＭＯＳ
トランジスタと第２のＭＯＳトランジスタはオン
電流値が異なつており、第１のＭＯＳトランジス
タと第２のＭＯＳトランジスタのオン・オフの組
合せにより４値をとる半導体装置。 A first gate electrode is provided on one side of the semiconductor active layer with a first gate insulating film interposed therebetween.
An OS transistor is formed, a second gate electrode is provided on the other side of the semiconductor active layer via a second gate insulating film to form a second MOS transistor, and a second MOS transistor is formed. MOS
A semiconductor device in which the transistor and the second MOS transistor have different on-current values, and take on four values depending on the on/off combination of the first MOS transistor and the second MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988137144U JPH0258346U (en) | 1988-10-20 | 1988-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988137144U JPH0258346U (en) | 1988-10-20 | 1988-10-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0258346U true JPH0258346U (en) | 1990-04-26 |
Family
ID=31398303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988137144U Pending JPH0258346U (en) | 1988-10-20 | 1988-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0258346U (en) |
-
1988
- 1988-10-20 JP JP1988137144U patent/JPH0258346U/ja active Pending