JPH0254926A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0254926A JPH0254926A JP20698388A JP20698388A JPH0254926A JP H0254926 A JPH0254926 A JP H0254926A JP 20698388 A JP20698388 A JP 20698388A JP 20698388 A JP20698388 A JP 20698388A JP H0254926 A JPH0254926 A JP H0254926A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- oxygen gas
- burrier
- metal
- tiw
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 11
- 239000011261 inert gas Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 24
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 2
- 229910052736 halogen Inorganic materials 0.000 abstract description 2
- 150000002367 halogens Chemical class 0.000 abstract description 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910000714 At alloy Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
バリアメタルを有する半導体装置の配線導電層の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a wiring conductive layer of a semiconductor device having a barrier metal.
[従来の技術]
従来の技術は工FJEE TRASAOT工ONS
ON 乙LKGTRON DKV工OKS 。[Conventional technology] Conventional technology is FJEE TRASAOT ONS
ON LKGTRON DKV OKS.
vOL、FD−54,NO,3,+987 P。vOL, FD-54, NO, 3, +987 P.
599に示゛されているようにバリアメタルとして窒化
チタン(以下TiNと呼ぶ)を反応性スパッタ法により
形成し、その後同−スバッタ装置内で真空を破らずにA
t配線層を形成するというものであった。As shown in No. 599, titanium nitride (hereinafter referred to as TiN) is formed as a barrier metal by reactive sputtering, and then A is applied in the same sputtering device without breaking the vacuum.
The idea was to form a t-wiring layer.
[発明が解決しようとする課題]
上述の従来技術では同じ文献中にもあるようにAt配線
層として純AAを用いた場合、TiNの膜厚が1ooo
X以下になると、熱処理によりAtが81基板中へ拡散
し接合破壊を起こすという課題を有する。またTiNの
膜厚を厚くすれば接合破壊は起こさないが、At配線層
と合わせた段差が高くなり、上層の保護絶縁膜やAt多
層配線の層間絶縁膜の被覆性が低下するという課題を有
する。[Problems to be Solved by the Invention] In the above-mentioned conventional technology, as mentioned in the same document, when pure AA is used as the At wiring layer, the film thickness of TiN is 100 mm.
When the temperature is less than X, there is a problem that At diffuses into the 81 substrate due to heat treatment, causing bonding breakdown. In addition, if the TiN film thickness is increased, junction breakdown will not occur, but there is a problem in that the level difference in combination with the At wiring layer becomes higher, and the coverage of the upper protective insulating film and the interlayer insulating film of the At multilayer wiring decreases. .
そこで本発明の目的とするところは、熱処理により接合
破壊の起こらない安定した配線層の製造方法を提供する
ところにある。Therefore, an object of the present invention is to provide a method for manufacturing a stable wiring layer that does not cause junction breakdown due to heat treatment.
〔課題を解決するための手段]
本発明は、バリアメタルとその上の配線導電層とを形成
する工程を含む半導体装置の製造方法において、バリア
メタルとして窒化チタンあるいはチタンタングステンを
形成する工程と、該窒化チタンあるいはチタンタングス
テンを不活性ガスと酸素ガスとを含む雰囲気中で高速熱
処理する工程と、その後配線導電層を形成する工程とを
含むことを特徴とする。[Means for Solving the Problems] The present invention provides a method for manufacturing a semiconductor device including a step of forming a barrier metal and a wiring conductive layer thereon, including a step of forming titanium nitride or titanium tungsten as the barrier metal; The method is characterized by including the steps of subjecting the titanium nitride or titanium tungsten to high-speed heat treatment in an atmosphere containing an inert gas and oxygen gas, and then forming a wiring conductive layer.
[作用]
本発明の上記の構成によれば、パ〕ノアメタルとしてT
INまたはチタンタングステン(以下T1Wと呼ぶ)を
形成した後、該TiNまたはTiWを不活性ガスと酸素
ガスとを含む雰囲気中で高速熱処理することにより、該
TiNまたはTiWの粒界には酸素がとり込まれ、なお
かつ該TiNまたはTiWそのものも緻密になる。粒界
にとり込まれた酸素はTiNまたはTiN中を電極金属
のAtが拡散するのを防止する。また、TiNまたはT
iWそのものも緻密になることにより、その粒子中をA
tが拡散しにくくなる。[Operation] According to the above structure of the present invention, T as a
After forming IN or titanium tungsten (hereinafter referred to as T1W), the TiN or TiW is subjected to high-speed heat treatment in an atmosphere containing an inert gas and oxygen gas, so that oxygen is trapped in the grain boundaries of the TiN or TiW. In addition, the TiN or TiW itself also becomes dense. The oxygen taken into the grain boundaries prevents At of the electrode metal from diffusing in TiN or in TiN. Also, TiN or T
As the iW itself becomes denser, A
t becomes difficult to diffuse.
[実施例コ
以下、図面に沿って本発明の詳細な内容を説明する。第
1図は本発明の実施例における製造工程図である。最初
に81基板上101に被着された絶縁膜102に開口部
を設ける。(第1図(α))その後バリアメタル103
をスパッタ法により形成する。バリアメタルの材料とし
てはTiN。[Embodiment] The detailed contents of the present invention will be explained below along with the drawings. FIG. 1 is a manufacturing process diagram in an embodiment of the present invention. First, an opening is provided in the insulating film 102 deposited on the 81 substrate 101. (Fig. 1 (α)) After that, the barrier metal 103
is formed by sputtering. The barrier metal material is TiN.
Tie、またはシリサイド(MOSi2 、WSi□、
Ttsiz)等が用いられるが、最近はTiNまたはT
iWが広く用いられている。TiNは、通常純T1ター
ゲットを基板加熱しつつ、窒素を含む雰囲気中でスパッ
タすることにより得られる。本発明ではバリアメタルと
して上記方法によりスパッタしたTiNを例として示す
。(第1図(b))次に上記TiNをハロゲンランプア
ニール装置等の高速熱処理が可能な装置を用いて不活性
ガスと酸素ガスとを含む雰凹気104中で高速熱処理す
る。この際の温度はあまり低いと効果がなく、通常70
0℃以上が用いられる。また酸素ガスの流量があまり多
いとTiNが醸化されるためできる限り少ない方が良い
。(第1図(C))次にAt合金等の配線導電層105
をスパッタ法により形成する。この際、段差被覆性を向
上させるため、基板にバイアスを印加するバイアススパ
ッタ法を用いてもよい。(第1図(d))第2図は上記
の様に形成したフンタクトのN+/P−接合リーク特性
を示した図である。試料はN ” / P−コンタクト
が10000個直列に接続されており、電極側に+5v
を印加した時の?!流値を測定した。グラフは横軸が′
成流値の対数、たて軸が度数分布である。配線導電ノー
形成後450℃、1時間の熱処理を行なった。従来の、
TiNとAt合金を同一装置内で連続的に形成したもの
は第1図(α)に示すよ5に、N+/P−接合リークを
起こすものが50%程度発生するが、TINを不活性ガ
スと酸素ガスの混合気体中で高速熱処理することKより
、第2図(b)に示すように接合リークを起すものはな
くなり、良好なバリア性を示している。本発明による試
料はこの後、480℃、30分の熱処理′を加えたが、
接合リークを起したものは数%で、製造マージンも十分
ある上記実施例はTiNを例として述べたが、TiWで
も同様の効果が得られる。TiNと同様粒界に酸素が取
シ込まれ、かつTIWそのものも緻密になるため、熱を
加えても接合リークを起こしにくい、安定したコンタク
トが得られる。Tie, or silicide (MOSi2, WSi□,
TiN or Ttsiz) etc. are used, but recently TiN or T
iW is widely used. TiN is usually obtained by sputtering a pure T1 target in an atmosphere containing nitrogen while heating the substrate. In the present invention, TiN sputtered by the above method is used as an example of the barrier metal. (FIG. 1(b)) Next, the TiN is subjected to high-speed heat treatment in an atmosphere 104 containing inert gas and oxygen gas using a device capable of high-speed heat treatment such as a halogen lamp annealing device. If the temperature at this time is too low, it will not be effective, and it is usually 70°C.
A temperature of 0°C or higher is used. Furthermore, if the flow rate of oxygen gas is too large, TiN will be fermented, so it is better to keep the flow rate as low as possible. (FIG. 1(C)) Next, a wiring conductive layer 105 made of At alloy, etc.
is formed by sputtering. At this time, a bias sputtering method in which a bias is applied to the substrate may be used to improve step coverage. (FIG. 1(d)) FIG. 2 is a diagram showing the leakage characteristics of the N+/P- junction of the contact formed as described above. The sample has 10,000 N”/P- contacts connected in series, and +5V is applied to the electrode side.
When applying ? ! The flow value was measured. The horizontal axis of the graph is ′
The logarithm of the stream value, the vertical axis is the frequency distribution. After forming the conductive wire, heat treatment was performed at 450° C. for 1 hour. Traditional,
When TiN and At alloys are formed continuously in the same equipment, about 50% of them cause N+/P- junction leakage, as shown in Figure 1 (α). As a result of the high-speed heat treatment in a mixed gas of K and oxygen gas, there is no junction leakage as shown in FIG. 2(b), indicating good barrier properties. The sample according to the present invention was then subjected to heat treatment at 480°C for 30 minutes.
Although the above embodiment has been described using TiN as an example in which the number of junction leaks is only a few percent and there is a sufficient manufacturing margin, the same effect can be obtained with TiW. Like TiN, oxygen is incorporated into the grain boundaries, and the TIW itself is dense, so a stable contact that is less likely to cause junction leakage even when heat is applied can be obtained.
また上記不活性ガスとしては、窒素ガス、アルゴンガス
等が用いられる。Further, as the inert gas, nitrogen gas, argon gas, etc. are used.
〔発明の効果コ
以上述べたように本発明によれば、バリアメタルとして
被着したTiNあるいはTiW・を不活性ガスと酸素ガ
スとを含む雰囲気中で高速熱処理することにより、後工
程で熱が加わっても接合リークの起こらない安定したコ
ンタクトが得られるという効果を有する。[Effects of the Invention] As described above, according to the present invention, TiN or TiW deposited as a barrier metal is subjected to high-speed heat treatment in an atmosphere containing inert gas and oxygen gas, so that heat can be removed in the subsequent process. This has the effect of providing a stable contact that does not cause junction leakage even when the contact is applied.
第1図(α)〜(d)は本発明の一実施例を示す製造工
程図。
101・・・・・・S1基板
102・・・・・・絶縁膜
103・・・・・・バリアメタル
104・・・・・・不活性ガスと酸素ガスとを含む雰囲
気
105・・・・・・配線導電層
第2図(α)(h)は本発明の一実施例による効果を示
すグラフ。
第2図(α)・・・・・・従来方法によるコンタクトの
接合リーク電流の度数分布
第2図(b)・・・・・・本発明によるコンタクトの接
合リーク電流の度数分布
Jl’J
【−10侮
翠9FIGS. 1(α) to (d) are manufacturing process diagrams showing one embodiment of the present invention. 101...S1 substrate 102...Insulating film 103...Barrier metal 104...Atmosphere 105 containing inert gas and oxygen gas - Wiring conductive layer FIG. 2 (α) and (h) are graphs showing the effects of one embodiment of the present invention. Fig. 2 (α) ... Frequency distribution of junction leakage current of contacts according to the conventional method Fig. 2 (b) ... Frequency distribution of junction leakage current of contacts according to the present invention Jl'J [ -10 Insui 9
Claims (1)
含む半導体装置の製造方法において、バリアメタルとし
て窒化チタンあるいはチタンタングステンを形成する工
程と、該窒化チタンあるいはチタンタングステンを不活
性ガスと酸素ガスとを含む雰囲気中で高速熱処理する工
程と、その後配線導電層を形成する工程とを含むことを
特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device including a step of forming a barrier metal and a wiring conductive layer thereon, a step of forming titanium nitride or titanium tungsten as the barrier metal, and a step of forming the titanium nitride or titanium tungsten with an inert gas and an oxygen gas. 1. A method for manufacturing a semiconductor device, comprising the steps of performing high-speed heat treatment in an atmosphere containing the following: and thereafter forming a wiring conductive layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20698388A JPH0254926A (en) | 1988-08-19 | 1988-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20698388A JPH0254926A (en) | 1988-08-19 | 1988-08-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0254926A true JPH0254926A (en) | 1990-02-23 |
Family
ID=16532234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20698388A Pending JPH0254926A (en) | 1988-08-19 | 1988-08-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0254926A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0545602A1 (en) * | 1991-11-26 | 1993-06-09 | STMicroelectronics, Inc. | Method for forming barrier metal layers |
JPH06260446A (en) * | 1993-03-05 | 1994-09-16 | Sony Corp | Manufacture of wiring structure |
-
1988
- 1988-08-19 JP JP20698388A patent/JPH0254926A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0545602A1 (en) * | 1991-11-26 | 1993-06-09 | STMicroelectronics, Inc. | Method for forming barrier metal layers |
JPH06260446A (en) * | 1993-03-05 | 1994-09-16 | Sony Corp | Manufacture of wiring structure |
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