JPH0250244A - Adapter for input and output control - Google Patents

Abstract

PURPOSE:To effectively execute recovery processing or abnormal processing to a data buffer, in which an error is generated, by prohibiting an access from a line control part to a local memory when the error is detected in data on an internal bus, with which data transferring is executed between the local memory and line control part. CONSTITUTION:A local memory 3 and a line control part 4, which controls the data transferring between the local memory 3 and a line, are provided. Then, detecting means 6 and 61 are provided to detect the error in the data on an internal bus 100 as an adapter for input and output control, to which the local memory 3, the line control part 4 and a processor 2 are connected by the internal bus 100. A prohibiting means 62 is provided to prohibit the access from the line control part 4 to the local memory 3 when the error is detected by these detecting means 6 and 61. Thus, it can be clearly grasped that which data buffer the data are transferred from when the error is generated. Then, the recovery processing or abnormal processing can be effectively executed to the data buffer, in which the error is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control adapter, and more particularly to an error handling method in an input/output control adapter.

Conventional input/output control adapters consist of a line control unit that controls the line, a local memory that is accessed by the line control unit, and a processor that controls data transfer with the host device. ing.

The processor interprets and executes commands from a host device, controls data transfer between the host device and local memory, and reports execution results and state transitions to the host device in accordance with a microprogram.

Further, the line control section executes data transfer between the data buffer in the local memory and the line according to the data in the control data section of the local memory, and stores the execution result in the control data section of the local memory.

The local memory has a control data section that stores control data exchanged between the processor and the line control section, and a data buffer that stores transfer data. Furthermore, since the local memory is accessed by both the processor and the line control section, some kind of arbitration circuit is required to coordinate access from both the processor and the line control section.

When data from a host device is output to the line,
When the processor activates data transfer from the host device to the local memory, the data from the host device is transferred to the local memory by hardware or firmware.

At this time, the processor needs to obtain exclusive rights to the data buffer in question based on the data in the control data section regarding the data buffer to be used. Furthermore, the processor writes the control data (such as the start address of the data buffer) of the corresponding data buffer into the control data section of the local memory, and also writes the predetermined data into the control data section to control the control data of the corresponding data buffer. Indicates that the exclusive right to be passed to the line control unit.

During this time, the line control section accesses the control data section at appropriate intervals to check whether there is a data buffer to which the line control section has been given exclusive rights.

When the line control section accesses the control data section and finds a data buffer to which exclusive rights have been handed over, it sequentially reads out the data in the data buffer and outputs it to the line.

When the data transfer from the local memory to the line under the control of the line control unit is completed, the line control unit writes the completion status to the control data unit, hands over exclusive rights to the data buffer to the processor, and issues a transfer end interrupt to the processor. Output.

When the processor learns the end of data transfer from the local memory to the line by sense or trap, it reads the end status of the line control unit from the control data area of the local memory and reports the result to the host device.

Through the processing operations described above, data from the host device is output to the line. Data transfer between the host device and local memory is controlled by the processor, and data transfer between the local memory and the line is controlled by the line control unit. The data transfer between the two is executed asynchronously.

Therefore, even if some error does not occur during data transfer between the local memory and the line controller, this error cannot be detected by the processor because it is not directly related to the processing operation of the processor. Can not.

Furthermore, even if the processor were to detect the error, the processor would still be performing processing related to another data buffer.

Grosse-y? From the side, when detecting an error like the one above, there is no convenient timing to sense it, and even if an error is to be trapped, the line control unit does not know which data buffer to perform data transfer. There is no way to directly know what is happening.

In such conventional input/output control adapters, data transfer between the line control unit and local memory is performed asynchronously with the operation of the processor. Even if an error occurs, the processor cannot clearly determine from which of the multiple data buffers the error occurred during data transfer, so The disadvantage is that it is not possible to take timely measures such as executing some kind of recovery process.

Furthermore, the method and timing of detecting the occurrence of an error itself is a difficult problem when it comes to microprogram processing of a processor.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to clearly understand from which data buffer an error occurred during data transfer, and to eliminate the error. An object of the present invention is to provide an input/output control adapter that can effectively execute recovery processing and abnormality processing for a data buffer in which an error has occurred.

An input/output control adapter according to the present invention is an input/output control adapter in which a local memory, a line control unit that controls data transfer between the local memory and a line, and a processor are connected by an internal bus. The control adapter includes a detection means for detecting an error in data on the internal bus, and a prohibition means for prohibiting access from the line control unit to the local memory when the error is detected by the detection means. It is characterized by having the following.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, an adapter according to an embodiment of the present invention includes a bus control section 1, a processor 2, a local memory 3, An internal bus 100 connected to each line control unit 4
A bus control unit 1 is connected to this internal bus 100 to exchange data with a higher-level device (not shown).

The local memory 3 includes a control data section 31 and a data buffer section 32, and is accessible from both the processor 2 and the line control section 4. Therefore, when the processor 2 and the line control unit 4 access the local memory 3, they output internal bus request signals 101 and 103 for using the internal bus 100 to the bus arbitration circuit 5, and Use permission signals 102, 104
must be received.

Furthermore, while the line control unit 4 is transferring data to and from the local memory 3, the parity check of the data on the internal bus 100 is performed by the parity check circuit 6, and a parity error is detected by the parity check circuit 6. Then, "1" is set in the error register 62 via the AND circuit 61, indicating that an error has occurred.

The error detection signal 105 from the error register 62 is input to the interrupt input terminal (INT) of the processor 2, and is input to the error (ERR) bit of the register 7, and "1'° is set to this error bit. .

In the processor 2, the processing being executed is interrupted by the input of the error detection signal 105 from the error register 62, and the contents of the register 7 are read into the processor 2 by this interruption. This allows the processor 2 to recognize that an error has occurred in data transfer between the line control unit 4 and the local memory 3.

When the processor 2 recognizes the occurrence of this error, it sets the INH (1nbibition) bit of the register 7 to “
1''.The output from the INH bit of this register 7 is inverted by the inverter 71, and the inhibit signal 1 is set.
It is output to the AND circuit 51 as 06.

In the AND circuit 51, prohibition number 16 from the inverter 71
06, the internal bus request signal 103 from the line control unit 4
From now on, the line control unit 4 disables the internal bus 100.
occupancy becomes impossible, and data transfer to and from the local memory 3 becomes impossible. Therefore, the data transfer between the line control unit 4 and the local memory 3 ends abnormally.

When the processor 2 recognizes that the data transfer between the line control unit 4 and the local memory 3 has ended abnormally based on the transfer end interrupt signal from the line control unit 4, it checks the control data section 31 of the local memory 3 and stores the data buffer. Among the plurality of data buffers of the unit 32, the data buffer in which the error has occurred is recognized by finding the data buffer occupied by the line control unit 4 immediately before the abnormal termination of data transfer.

When the processor 2 recognizes a data buffer in which an error has occurred, it performs appropriate processing (abnormality processing, try processing, etc.) on the data buffer.

FIG. 2 is a flowchart showing the operation of one embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

When outputting data from a higher-level device onto the line, the processor 2 starts data transfer from the higher-level device to the data buffer section 32 of the local memory 3 via the bus control section 1, and transfers the data from the higher-level device to the data buffer section 32 of the local memory 3. 32 (step 11 in FIG. 2).

When the transfer process from the host device to the data buffer unit 32 is completed, the processor 2 writes control data such as the start address of the data buffer used in the transfer process to the control data unit 31 of the local memory 3 (step 2 in FIG. 12) Transfer ownership of the data buffer to the line control unit 4. As a result, the line control unit 4 transfers data to and from the local memory 3.

In the processor 2, the song is processed until the transfer end interrupt signal from the line control unit 4 becomes valid (step 13 in FIG. 2), but before the transfer end interrupt signal becomes valid, an error is detected from the error register 62. When the signal 105 is input, an interrupt is applied to other processes being executed, and this v1
The contents of register 7 are read into processor 2 by the input.

Note that if no error is detected in the parity check circuit 6 before the transfer end interrupt signal from the line control unit 4 becomes valid, the data transfer between the line control unit 4 and the local memory 3 ends normally ( Figure 2 step 14).

As a result, when the processor 2 recognizes that an error has occurred in the data transfer between the line control unit 4 and the local memory 3 (step 15 in FIG. 2), it sets the INH bit of the register 7 to 1'' ( Figure 2 Step 16
), prohibiting access from the line control unit 4 to the local memory 3.

The processor 2 indicates that the data transfer between the line control unit 4 and the local memory 3 has ended abnormally due to the prohibition of access from the line control unit 4 to the local memory 3.
When it is recognized by the transfer end interrupt signal from the line control unit 4 (step 17 in FIG. 2), the control data section 31 of the local memory 3 is checked, and among the plurality of data buffers of the data buffer section 32, abnormal termination of data transfer is detected. The data buffer in which the error occurred is recognized by finding the data buffer occupied by the line control unit 4 immediately before (step 18 in FIG. 2).

At this time, the processor 2 also accesses the line control unit 4 and analyzes the error information detected by the line control unit 4 (second
In step 19 of the figure, if no error is detected by the line #control unit 4, the processor 2 retries the data buffer because the only error that has occurred in the data buffer is the parity error detected by the parity check circuit 6. Processing is performed (step 22 in FIG. 2).

If the line control unit 4 detects an error, the processor 2 performs abnormality processing or trial processing for each data buffer depending on the content of the error (steps 20 to 22 in FIG. 2).

In this way, when an error is detected in the data on the internal bus 100 by the parity check circuit 6 during data transfer between the line control unit 4 and the local memory 3 via the internal bus 100, the line control unit 4 The internal bus request signal 103 of the line controller 4 is disabled, and the local memory 3
By prohibiting access to the line controller 4, the data transfer between the line controller 4 and the local memory 3 can be terminated abnormally. You can check the situation.

Here, even if the line control section 4 operates asynchronously with the processor 2, by checking the control data section 31 of the local memory 3 when data transfer ends abnormally, it is possible to determine which data buffer the error was detected in. can be recognized, and recovery processing and abnormality processing for the data buffer in which the error has occurred can be effectively executed.

In one embodiment of the present invention, when the error detection signal 105 from the error register 62 is input to the processor 2, the contents of the register 7 are read by interrupt processing. It is also possible to read the contents of 7.

In addition, the INH bit of register 7 is enabled after the processor 2 recognizes the occurrence of an error, but when an error occurs, the INH bit of the register 7 is enabled.
It is also possible to invalidate the internal bus request signal 103 from the line control unit 4 using hardware, but the present invention is not limited to this.

As explained above, when an error is detected in the data on the internal bus where data is being transferred between the local memory and the line control unit, the present invention enables the transfer of data from the line control unit to the local memory. By prohibiting access to the data buffer, it is possible to clearly understand which data buffer the error occurred during data transfer, and enable recovery processing and abnormality processing for the data buffer where the error occurred. The effect is that it can be executed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the invention, and FIG. 2 is a flowchart showing the operation of the embodiment of the invention. Explanation of symbols of main parts 2...Processor 3...Local memory 4...Line control unit 5...Bus arbitration circuit 6... Parity check circuit 7...Register 31...Control data section 32...Data buffer section 51.61...AND circuit 62...Error Register 100...Internal bus

Claims (1)

[Claims] (1) An input/output control adapter in which a local memory, a line control unit that controls data transfer between the local memory and a line, and a processor are connected by an internal bus, and the adapter is configured to control data on the internal bus. for input/output control, comprising: a detection means for detecting an error; and a prohibition means for prohibiting access from the line control unit to the local memory when the error is detected by the detection means. adapter.