JP2599971B2 - Bus error detection processing method of communication processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a bus error detection processing method of a communication processor for transmitting data information collected from a lower device to a higher device. In order to prevent erroneous data from being transmitted, a reception data unit for receiving and processing data from a lower-level device, a transmission data unit for transmitting and processing this received data to a higher-level device, In a communication processor comprising a main data unit executing data transfer to a transmission data unit, a local bus abnormality detection circuit for detecting an abnormal state of data on a local bus provided in the transmission / reception data unit, and a system provided in the main data unit System bus error detection circuit that detects an abnormal state of data on the bus And a data transfer processing device stop circuit for immediately stopping the driving of the data transfer processing device that executes data transfer processing between the local bus and the system bus when the bus abnormality detection circuit detects an abnormal state. The configuration is as follows.

[Industrial applications]

The present invention relates to a bus abnormality detection processing method of a communication processor that transmits data information collected from a lower device to a higher device.

The communication processor collects data from a number of lower-level devices via a low-speed line, reassembles the collected data, and transmits the data to a higher-level device via a high-speed line. In a communication processor that performs such processing, it is necessary to provide a function for preventing erroneous data from being transmitted to a higher-level device.
When executing this function, it is necessary to prevent the original high-speed data transmission processing from being harmed.

[Conventional technology]

The communication processor receives and processes data from the lower-level device, a transmission data unit that transmits the received data to the higher-level device, and a transmission data unit from the reception data unit to execute its own processing. A main data unit for transferring data to the units is provided, and data transfer between these units is performed using DMA. With the communication processor configured as described above, when an error in data on the bus of the transmission / reception data unit or the main data unit is detected by the conventional parity check or ECC error check, the transmission / reception Processing was performed to notify the CPU of the data unit and the main data unit of that fact. Then, upon receiving this abnormality detection notification,
The CPU employs a method in which the cause of the bus error is analyzed by a program and the corresponding process is executed.

[Problems to be solved by the invention]

However, according to such prior art, CP
Since U enters the bus error analysis processing after the end of DMA data transfer, erroneous data may be transmitted from the transmission data unit to the host device. Moreover, while the CPU is analyzing the cause of a bus error, there is a possibility that serious damage such as destruction of a program or source code may be caused to the system.

The present invention has been made in view of such circumstances,
If there is an error in the data on the bus of the communication processor, erroneous data is prevented from being transmitted to the host device, and the bus error detection processing method of the communication processor that does not cause serious damage to the system. It is intended to be provided.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

In the figure, reference numeral 1 denotes a communication processor, which collects data information from many lower-level devices via a low-speed line,
Processing for reassembling the collected data information and transmitting it to a higher-level device via a high-speed line;
Is a low-speed line connecting the communication processor 1 and the lower-level device 2;
And 5, a high-speed line connecting the communication processor 1 and the high-order device 4. The communication processor 1 includes a reception data unit 10, a transmission data unit 20, and a main data unit 30. The reception data unit 10 receives data sent from the lower-level device 2, and the transmission data unit 20 reassembles the data received by the reception data unit 10 for a high-speed line and transmits the data to the higher-level device 4. 30 executes the transfer of data from the reception data unit 10 to the transmission data unit 20. 11, 12, 1
Reference numerals 3, 14, 15, and 16 denote a local CPU, a local RAM, a local bus, a data transfer processing device, a local bus abnormality detection circuit, and a data transfer processing device stop circuit included in the reception data unit 10, respectively. This data transfer processing device 14
Performs a data transfer process between the local bus 13 and the system bus 33 provided in the main data unit 30, a local bus error detection circuit 15 detects an error in the data on the local bus 13, and The stop circuit 16 executes a process of stopping the driving of the data transfer processing device 14. twenty one,
22, 23, 24, 25, and 26 are transmission data units 20 respectively.
, A local RAM, a local bus, a data transfer processing device, a local bus abnormality detection circuit, and a data transfer processing device stop circuit. This data transfer processor
24 performs a data transfer process between the local bus 23 and the system bus provided in the main data unit 30; a local bus abnormality detection circuit 25 detects an abnormality of data on the local bus 23; The stop circuit 26 executes a process of stopping the driving of the data transfer processing device 24. 31,
Reference numerals 32, 33, and 35 denote a main CPU, a system RAM, a system bus, and a system bus abnormality detection circuit included in the main data unit 30, respectively. The system bus abnormality detection circuit 35 detects an abnormality of data on the system bus 33.

[Operation] In the present invention, the data transfer processing device stop circuits 16, 26
If one of the local bus abnormality detection circuits 15, 25 and the system bus abnormality detection circuit 35 detects an abnormal state on condition that the abnormality detection circuit is a bus having a bus use right, the corresponding data transfer processing is performed. Processing is performed to immediately stop driving the devices 14 and 24.

As described above, in the present invention, when a bus error occurs, the drive of the data transfer processing device is immediately stopped according to the hardware circuit, so that erroneous data is not transferred. This prevents erroneous data from being transmitted to the host device and does not cause any serious damage to the system.

Moreover, since the data transfer processing devices 14 and 24 are configured to stop instead of resetting, the CPU refers to the address registers of the stopped data transfer processing devices 14 and 24 to determine the cause of the bus abnormality. Be able to analyze.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 2 is an explanatory diagram for explaining a use state of the communication processor 1. As shown in this figure, the communication processor 1 converts data collected by a plurality of lower-level devices 2 into, for example,
In addition to receiving the data in a low-speed transmission procedure such as CDT, these data are reassembled into a high-speed transmission procedure such as HDL and transmitted to the host device 4.

In order to execute this processing, the communication processor 1 receives a data from the lower-level device 2 and processes the received data unit.
10, a transmission data unit 20 for transmitting the received data to the host device 4, and a main data unit 30 for transferring data from the reception data unit 10 to the transmission data unit 20. ,
It is configured to execute data transfer from the reception data unit 10 to the main data unit 30 and data transfer from the main data unit 30 to the transmission data unit 20 by using DMA.

FIG. 3 shows a configuration diagram of an embodiment of the communication processor 1 according to the present invention. In the figure, the same components as those described in FIG. 1 are indicated by the same symbols. In this figure, the embodiment of the present invention is disclosed in the relationship between the reception data unit 10 and the system bus 33 of the main data unit 30, but the embodiment is implemented in the relationship between the transmission data unit 20 and the system bus 33 of the main data unit 30. The configuration of the example is basically the same.

14a is a DMA controller corresponding to the data transfer processing device 14 in FIG. 1, and 16a is a DMA stop circuit corresponding to the data transfer processing stop circuit 16 in FIG. This DMA
The stop circuit 16a includes a first switching circuit 41, as shown in FIG.
Second switching circuit 42, switching control circuit 43, first AND gate 4
4. It comprises a second AND gate 45 and an OR gate 46.

The first switching circuit 41 performs a switching process to send a bus request signal from the DMA controller 14a to either the local bus 13 or the system bus 33, and the second switching circuit 42
Performs switching processing to return the bus use permission signal returned from the local bus 13 and the system bus 33 to the DMA controller 14a, and the switching control circuit 43
The switching process of the switching circuit 42 is controlled. And the first
The AND gate 44 sends an output when the system bus abnormality detection circuit 35 detects an abnormality in data on the system bus 33, provided that the bus use permission signal from the system bus 33 is returned. The second AND gate 45 outputs a signal when the local bus abnormality detection circuit 15 detects a data abnormality on the local bus 13 on condition that the bus use permission signal from the local bus side 13 is returned. The OR gate 46 sends an output to stop driving the DMA controller 14a when there is an output from either the first AND gate 44 or the second AND gate 45.

Next, the processing content of the embodiment configured as described above will be described.

When the receiving data unit 10 receiving the data from the lower-level device 2 transfers the received data to the main data unit 30, the local CPU 11
A start command is sent to 14a, and a process is performed via the switching control circuit 43 to switch the first and second switching circuits 41 and 42 to the local bus 13 side. The DMA controller 14a activated in this way sends a bus request signal via the first switching circuit 41 and confirms that the bus use permission signal has returned from the local CPU 11 via the second switching circuit 42. If confirmed, processing is performed to read data from the lower-level device 2 stored in the local RAM 12. When this reading is completed, the local CPU 11 performs processing to switch the first and second switching circuits 41 and 42 to the system bus 33 side. Subsequently, the DMA controller 14a
When the bus request signal is transmitted via the system bus 33 and the bus use permission signal is returned from the main CPU 31 via the second switching circuit 42, the data read via the system bus 33 is transferred to the system bus RAM 32. Process to write.
In this way, data transfer is realized.

During processing of data transfer from the receiving unit 10 to the main data unit 30 executed by the DMA controller 14a, when the local bus abnormality detecting circuit 15 detects data abnormality on the local bus 13 being transferred, the OR gate 46 When the output signal of the DMA controller 14a immediately stops driving the DMA controller 14a and the system bus abnormality detection circuit 35 does not detect a data abnormality on the system bus 33 being transferred,
The output signal from the OR gate 46 allows the DMA controller 1
4a will be stopped. As described above, according to the present invention, when a bus error is detected, the processing is immediately performed according to the DMA stop circuit 16a so as to stop driving the DMA controller 14a. Then, after that, the CPU on the bus side having the data abnormality refers to the address register of the DMA controller 14a to analyze at which address the bus abnormality has occurred, and to perform necessary processing. Become. It should be noted that a bus error during a data transfer process from the main data unit 30 to the transmission data unit 20 is also processed in the same manner.

In order to clarify the difference between the present invention and the prior art, a time chart of the processing content of the present invention is shown in FIG. 4, and a time chart of the processing content of the conventional technology is shown in FIG. As shown in the time chart of FIG. 5, in the prior art,
Even if a bus error occurred many times during data transfer, the CPU did not enter the bus error process until the data transfer was completed.

Although the illustrated embodiment has been described above, the present invention is not limited to this. For example, the number of transmission / reception units included in the communication processor is not limited to one, but may be plural. Various specific methods for detecting a bus error, such as a parity check and an ECC error check, can be used.

〔The invention's effect〕

As described above, according to the present invention, when a bus error occurs, the drive of the data transfer processing device is immediately stopped according to the hardware circuit, so that erroneous data is not transferred. As a result, erroneous data is not transmitted to the host device, and the system is not seriously damaged.

Moreover, since the DMA is configured to be stopped instead of being reset, the CPU can analyze the cause of the bus abnormality by referring to the address register or the like of the stopped DMA.

In particular, when a bus error occurs due to a DMA operation, the bus error often continues continuously thereafter, so the present invention is effective.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is an explanatory diagram of a communication processor, FIG. 3 is a diagram illustrating an embodiment of the communication processor of the present invention, and FIG. 4 is a time chart illustrating processing contents of the present invention. FIG. 5 is a time chart for explaining the processing content of the prior art. In the figure, 1 is a communication processor, 2 is a lower device, 3 is a low-speed line, 4 is a higher-level device, 5 is a high-speed line, 10 is a reception data unit, 11 and 21 are local CPUs, 13 and 23 are local buses, 14 and 24 is a data transfer processing device, 15 and 25 are local bus abnormality detection circuits, 16 and 26 are data transfer processing device stop circuits, 20 is a transmission data unit, 30 is a main data unit, 31 is a main CPU, 32 is a system RAM, 33 is a system bus, and 35 is a system bus abnormality detection circuit.

Claims (1)

(57) [Claims] A local CPU and a local bus;
A reception data unit for receiving data from a lower-level device, a local CPU and a local bus, a transmission data unit for transmitting data received by the reception data unit to a higher-level device, a main CPU and a system bus; A communication processor configured to transfer data from the reception data unit to the transmission data unit, and to transfer data between the local bus and the system bus using a data transfer processing device A local bus abnormality detection circuit provided in association with the local bus of the reception data unit and the local bus of the transmission data unit to detect a data abnormality on the paired local bus; System bus error detection that detects data errors on the system bus And road, provided in association with said local bus abnormality detection circuit,
The detection value of the local bus abnormality detection circuit and the detection value of the system bus abnormality detection circuit, which are a pair, are input, and one of the two abnormality detection circuits which is associated with the bus having the right to use the bus is a data abnormality. And a data transfer processing device stop circuit for immediately stopping the driving of the paired data transfer processing devices when detecting the error.