JPH0234055A - Cell mis-synchronization detection system - Google Patents

Abstract

PURPOSE:To discriminate the case of detection of dissidence between bit patterns as out of synchronism by providing a header comparison section and a data comparison section or the like and comparing the bit pattern of a synchronizing cell stored in advance with the bit pattern of a synchronizing cell sent continuously periodically. CONSTITUTION:A receiver 2 is provided with a header comparison section 9, a data comparison section 10 and a buffer 8 or the like, an input signal is stored in the buffer 8 and the synchronizing cells are compared by referencing the bit pattern with the bit patterns of the sections 9, 10. That is, a control section 18 operates a timer 15 when input signals are occupied in the buffer 8, the bit pattern in the buffer 8 is compared with the bit patterns in the sections 9, 10. As a result, when the header part is dissident and the data part is coincident, the control section 18 discriminates it to be out of synchronism and whether or not the synchronization is deviated in the unit of cells is identified. Thus, erroneous detection is reduced and out of synchronism is detected accurately.

Description

Detailed Description of the Invention (Objective of the Invention) (Industrial Field of Application) The present invention provides cell mis-synchronization detection for early detection of mis-synchronization in a transmission system that establishes frame synchronization using fixed-length synchronized cells. Regarding the method.

(Prior Art) An example of a frame format in a conventional transmission system is shown in FIG. In the conventional frame synchronization method, frame bits having synchronization information are periodically outputted onto a transmission path, and frame synchronization is established by detecting the frame bits.

In other words, this method uses bit-by-bit synchronization. There is a close relationship between this frame period, the error rate on the transmission path, and the transmission efficiency, and once the error rate on the transmission path is determined,
The frame period that maximizes transmission efficiency is uniquely determined. However, in the conventional frame synchronization method, the frame period is fixed.

The drawback is that it cannot respond to changes in the error rate.

Therefore, there is a method that establishes frame synchronization by storing information for frame synchronization in cells (cells with this synchronization information will be referred to as synchronization cells from now on) instead of in synchronization bits, and transmitting these synchronization cells at regular intervals. Conceivable. In this method, it is possible to change the frame period by changing the transmission interval of cell synchronization cells, but since one cell is used as synchronization information, in addition to sending an information cell containing information, synchronization information is also transmitted. The disadvantage is that the transmission efficiency is greatly degraded since the transmission must be transmitted. Therefore, in order to eliminate this drawback, we took advantage of the feature that the interval between synchronized cells can be changed, and detected when there was no information to be communicated.
By transmitting synchronous cells, it is possible to suppress deterioration in transmission efficiency.

When this method is used, it is impossible to know in advance at what timing a synchronous cell will appear, so it is necessary to determine whether all cells are synchronous cells. In other words, if a synchronized cell is transmitted at a constant cycle while in an erroneous synchronization state, the erroneous synchronization state continues only if a synchronous cell happens to appear where a synchronous cell should appear next. When the interval between synchronized cells is made variable, there is a drawback that if a synchronized cell happens to appear in some cell, the missynchronized state will continue, and the missynchronized state will continue for a long time.

(Problems to be Solved by the Invention) As described above, since synchronization is achieved by cells, it is necessary to identify for each cell whether it is a synchronization cell or a data cell carrying information. Even if it is a data cell,
If a cell has the same bit string as a synchronous cell, it will be incorrectly identified as a synchronous cell and will be determined to be out of synchronization.

Another drawback is that even if synchronized cells that are periodically transmitted become slightly out of synchronization due to bit delays caused by transmission lines, equipment, etc., this out-of-synchronization cannot be recognized.

The present invention has been made in view of these points, and compares the bit pattern of a synchronous cell stored in advance with the bit pattern of a synchronous cell that has been periodically and continuously transmitted. It is an object of the present invention to provide a cell synchronization error detection method that determines that synchronization is out of synchronization when a 癲→婆嬆i4 mismatch is detected.

[Structure of the invention]

(Means for solving problems) In order to achieve the above object, the present invention provides.

The transmitting device includes a data cell forming section for forming a data cell consisting of a header section and a data section, and a synchronous cell for forming a synchronous cell consisting of a header section and a data section in which all bits are set to values of the same sign. The synchronous cell forming section includes a forming section and a transmitting section for transmitting the synchronous cells formed by the synchronous cell forming section at regular intervals. In a cell synchronization system in which a receiving device receives the output of the transmitter of the transmitting device, detects synchronized cells, and performs frame synchronization, the receiving device includes means for detecting an out-of-synchronization state from a synchronized state. ing. The means for detecting an out-of-synchronization state from this synchronization state is that the memoranda section for storing the values of the header section and data section of a synchronized cell do not match, and if the data sections match, the out-of-synchronization will occur. The present invention is characterized by comprising a determination unit that determines that the state is.

(Function) In the transmitter, an information data cell is formed in the data cell forming section. Further, the synchronous cell forming section forms a synchronous cell in which all bits are set to a value of the same sign, for example, all bits are set to a value of 1. This synchronization cell is then transmitted from the transmitter at regular intervals. The receiving device detects the synchronization cell transmitted from the transmitting device and synchronizes. In this way, even if the synchronization is achieved, there may be a case where the synchronization becomes out of synchronization due to loss in the transmission line or equipment.

In order to detect this out-of-synchronization state, the receiving device is equipped with means for detecting an out-of-synchronization state from a synchronized state. This means operates as follows.

A comparison unit compares the values of the header part and the data part of the synchronization cell previously stored in the memory with the values of the header part and the data part of the received synchronization cell.

The comparison unit compares the synchronized cells that are received sequentially, and the output from the comparison unit indicates that the header section does not match.
When the data portions match, the determining section determines that synchronization is out of synchronization.

Through the above operations, it is possible to identify whether or not the synchronization of each cell is out of order.

(Example) FIG. 1 shows an example of a transmission system to which the present invention is applied. FIG. 1 shows a diagram in which a transmitting device 1 and a receiving device W2 are connected via a transmission path. The synchronous cell forming unit 3 of the transmitting device 1 in FIG. 1 stores a synchronous cell pattern consisting of a unique bit pattern in a data cell, and the synchronous cell forming unit 3 refers to the pattern. This generates synchronous cells. The timing at which the transmitter 1 transmits the synchronization cell is when either of the following two conditions is satisfied. ■The transmitting side does not have any cells to output; ■A certain amount of time has passed since the previous synchronous cell was sent. Assuming that the system has now started up, the transmitter 1 causes the transmitter 6 to output synchronous cells onto the transmission path based on the above operations. The pattern of this synchronization cell is broadly composed of a header part and other parts (hereinafter this part will be referred to as data).On the other hand, a data cell also consists of a header part and a data part, and the data cell The pattern of the header portion is different from that of the header portion of the synchronous cell. The pattern of the header section different from this synchronization cell is determined by the data cell forming section 5.
A data cell is formed by referring to the registered pattern.

Next, the operation of the receiving device 2 after receiving the cell transmitted from the transmitting device 1 will be explained. Hereinafter, the term "stage number" will appear, and this represents 1, for example, in bit units. The receiving device 2 includes a buffer 8 in which signals input from a transmission path are stored, and a header comparison section 9 and a data comparison section 10 that compare the pattern in the buffer 8 with the pattern of a synchronization cell.

A timer 15 is set to the time required to input a 1-bit signal to the buffer, and a timer 1 is set to the time required to input a 1-cell signal to the buffer 8.
8 and a timer 17 in which the maximum interval of synchronization cells is set.
and a control section 16 that controls each of these sections, and the header comparison section 9 and data comparison section 10 are under the control of a timer 15 and a timer 18, and when either of these two timers is started, Compare patterns in the buffer.

Further, this buffer 8 is composed of a shift register, and its length is equal to the length of one cell. The control unit also has a forward stage number memory and a backward stage number memory for storing the number of forward protection stages and the number of backward protection stages.

Next, the operation at system startup will be described below. The control unit 16 has a function of knowing how many bits of signal are stored in the buffer 8, and knows whether the buffer is full of signals input from the transmission path. -Start the operation of the timer 15 when the timer reaches the limit. This timer 15
, the header comparison section 9 and the data comparison section 10 are activated.
performs a comparison with the pattern in buffer 8. Comparison with synchronous cells follows the procedure below. The pattern of the synchronous cell is fixed and consists of a header section and a data section at the beginning of the cell, and the header comparison section 9 compares the header section, and the data comparison section 1o compares the data section.

These comparison units store therein the patterns of the header section and data section of the synchronous cell, and perform comparison with the synchronous cell by referring to the patterns.

The result of the comparison is input to the control unit 16, and the control unit 16 determines whether the cell is a synchronous cell or not based on the result of the comparison. As a result of the comparison, if it is determined that the cell is different from the synchronous cell, the control unit 16 takes no action.

Therefore, the header comparator 9 and the data comparator 10 compare the patterns with the synchronous cell every time a 1-bit signal is input to the buffer 8 based on the operation of the timer 15, and determine that the cell is a synchronous cell as a result of the comparison. If this happens, it is assumed that 1 stage synchronization has been achieved, 1 is set in the backward stage number memory, and timer 15 is set.
and starts the timer 18. By activating timer 18 instead of timer 15, the content of buffer 8 is now compared with the synchronous cell pattern every time a 1-bit signal is input to buffer 8. Every time there is a change, that is, every time the next cell is input into the buffer 8, a comparison with the synchronous cell pattern is performed. Further, the control unit 16 also starts the timer 17 at the same time as the timer 18 . When a new cell enters the buffer 8, it is compared with the synchronous cell, and if it is determined that it is the same as the synchronous cell, 1 is added to the backward stage number memory and the timer 17 is reset. the result,
When the value in the memory reaches a certain value, it is assumed that synchronization has been achieved, a certain value is set in the backward stage number memory, and the state shifts to a busy state. If the detection of the synchronous cell pattern fails before the value in the backward stage number memory reaches a certain value, the value in the backward stage number memory is decreased by 1 (this failure to detect the synchronous cell pattern will be discussed later). As a result, if the value in the memory becomes 0, the timer 8 is stopped, the timer 15 is started, and the state becomes the same as when the timer was started again. However, at this time, since one cell's worth of signals has already been stored in the buffer 8, there is no need to wait for the buffer 8 to become full, and even if synchronization is achieved,
Detection of patterns with synchronous cells is continued, and each time a synchronous cell is detected, 1 is added to the forward stage number memory (however, if the contents of the forward stage number memory has reached a certain value, do not add it). Each time the detection of a synchronous cell fails, 1 is decremented from the forward stage number memory.

As a result, when the contents of the forward stage number memory become 0, the contents of the backward stage number memory are reset to O, the timer 18 is stopped, and the timer 5 is started, and the state becomes the same as when starting up again. However, at this time, since one cell's worth of signals has already been stored in the buffer 8, there is no need to wait for the buffer 8 to become full.

The above describes how to establish synchronization and how to remove synchronization when using synchronized cells. continuation,
A process in which the control unit considers a cell to be the same as a synchronous cell and a process in which the detection of a synchronous cell fails will be explained. When the comparison results are input to the control unit 16 from the header comparison unit 9 and the data comparison unit IO, the following operations are performed according to these signals. Note that both the header comparison unit 9 and the data comparison unit 10 If the pattern in the buffer 8 matches the pattern it owns, an ON signal is output to the control section 16, and if they do not match, an OFF signal is output to the control section 16.

■ Both header comparison section output and data comparison section output are ON.
.

In this case, the pattern in the buffer is the same as the pattern of the synchronous cells.

■ The output of the header comparison section is ON, and the output of the data comparison section is OFF.

In this case, it is assumed that the detection of the synchronous cell was successful.

■ Header comparison section output is OFF.

At this time, nothing is done regardless of the output of the data comparison section.

Furthermore, if the above condition (2) continues and the timer 17 turns ON, it is assumed that the detection of the synchronous cell has failed.

Therefore, the first stage of synchronization is considered to be lost if: ■ If a synchronized cell cannot be detected after a certain period of time has elapsed, ■ The header part is the same as the synchronized cell pattern, but the data part is the same as the synchronized cell pattern. There are two cases where they are not the same.

Next, a second embodiment will be described using FIG. 2.

A synchronous cell is formed from the synchronous cell forming section 3 in the transmitter 1 according to the synchronous cell pattern described above and is input to the clock 4. At clock 4.

The synchronization cells are sent to the transmitter 6 at intervals of transmission time of the synchronization cells. On the other hand, between these synchronous cells,
Data cells formed by the data cell forming section 5 and consisting of information data, etc. are sent from the data cell forming section to the transmitting section 6, and these cells are transmitted from the transmitting section 6. The cells transmitted from the transmitter 6 are received by the receiver 7 in the receiver 2, and these cells received by the receiver 7 are sequentially stored in the buffer 8. Then, the synchronization cell is divided into a header part and a data part, and this header part is sent to the header comparison section 9.

The data portion is input to the data comparison section 10. The header comparison section 9 and the data comparison section 10 each store in advance a header section and a data section of a synchronization cell formed by the synchronization cell formation section 3 in the transmitting device [1. The header section and data section input from the buffer 8 are compared respectively. When the result of this comparison satisfies the above-mentioned conditions, the determination section 11 determines that the synchronization is out of synchronization, and a signal indicating this fact is sent to the control section 12. When this signal is sent, the control unit 12 controls the clock 13 and uses the clock 13 to shift the detection time of the synchronous cell input into the buffer 8 by, for example, one bit of time. Adjust the time as you like. Each time the above operations are performed sequentially, the header comparison unit 9 and data comparison unit 10
and operating the determination unit 11.

How to change from out of synchronization to synchronization - Control the order 0
By performing the above operations, the header part and data part match,
If there is a discrepancy, a synchronization error can be identified and corrected to a synchronized state.

〔Effect of the invention〕

As described in detail above, according to the present invention, due to the environment inside and outside the system of the present invention, synchronization may be slightly off, or the same bit pattern as the bit pattern of the synchronized cell may erroneously appear on the data cell. However, out-of-synchronization is determined based on whether or not the header and data portions stored in the memory match the header and data portions of the sequentially transmitted synchronous cells. Therefore, it is possible to reduce erroneous detection, such as when the same bit pattern as a synchronous cell appears on a data cell due to an accidental synchronization shift or a bit error, and this is identified as a synchronous cell. Therefore, the loss of synchronization can be determined without erroneously determining that the state has changed from a synchronized state to an out-of-synchronization state. Also, by varying the interval between synchronized cells,
Even if a synchronized cell happens to appear somewhere, the synchronization shift can be detected accurately.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional example. 3... Synchronous cell forming section 5... Data cell forming section 8... Buffer 9... Header comparing section 10... Data comparing sections 11, 16... Judgment section 12... Control section 4 .13...Clock Figure 1 Agent Patent Attorney Noriyuki Chika Mitsuyuki Matsuyama Figure 3

Claims (1)

[Claims] A data cell forming section that forms a data cell consisting of a header section and a data section, and a synchronization cell consisting of the header section and the data section in which all bits are set to values of the same sign. a transmitting device comprising a synchronous cell forming section for transmitting the synchronized cells, a transmitting section for transmitting the synchronized cells formed by the synchronized cell forming section at regular intervals, and an output of the transmitting section of the transmitting device; In the cell synchronization system, the cell synchronization method includes a receiving device configured to perform frame synchronization by detecting the synchronized cell and performing frame synchronization, wherein the receiving device stores in advance values of the header section and the data section of the synchronized cell. and the values of the header section and the data section of the synchronization cell sent from the transmitting device match the values of the header section and the data section stored in the memory, respectively. and a determining unit that determines that the synchronization is out of synchronization when the header section does not match and the data section matches. Cell missync detection method.