JPH0227762A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To add the function of an EEPROM to that of a static RAM in a cell having the same area as that of a conventional E/R type static RAM cell by composing to interpose a floating gate between an electrode layer and a resistance layer through a tunnel insulating film. CONSTITUTION:Floating gates 9a, 9b for altering the values of load resistances by charge are added to a resistance load type static RAM cell in which a polysilicon high resistance element is employed, for example, as a load 1a, the gates 9a, 9b are operated like the gate electrode of a MOSFET thereby to vary a load resistance value. When a load resistor is further connected to a driver transistor to form an FF as a whole, if a power source is applied, previous data are automatically obtained at the memory node of the FF.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention provides a static random access memory (
RAM) and electrically rewritable non-volatile memory (EE
Pl? The present invention relates to a semiconductor memory device having a configuration in which the RAM is combined with a power source (ON), and is particularly used as a static type RAM that can retain memory semi-permanently even in the absence of a power supply.

(Prior Art) Generally, in a static RAM, the stored data is destroyed when the power is turned off, so if it is desired to retain the previous data, a separate backup power source has been used.

(Problem to be solved by the invention) In this case, a separate backup power supply is required, so when considering combining static RAM and EEFROM in order to retain stored data semi-permanently even without a power supply, it is difficult to simply use RAM If you just add EEPROM to the
Requires ROM. Accordingly, the size of devices that use these memories as components becomes larger and the manufacturing cost increases accordingly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can be configured as a static RAM that also has the functions of an EEPROM, and can semi-permanently retain stored data even without a power supply.

(Means and Effects for Solving the Problems) The present invention provides a flip-flop circuit including a load resistor and a driver transistor, a floating gate that changes the value of the load resistor depending on electric charge, and a structure in which the floating gate is connected to the flip-flop circuit with a tunnel insulating film interposed therebetween. and means for injecting the charge or releasing the charge from the floating gate.

That is, in the present invention, a floating gate is added to a resistive load type static RAM cell using, for example, a polysilicon high resistance element as a load, and the floating gate acts like a gate electrode of a MOSFET to increase the load resistance value. is changed so that when the flip-flop is powered on, the previous data is automatically obtained in each storage node of the flip-flop.

(Example) An example of the present invention will be described below with reference to the drawings. A circuit diagram of a typical resistive load type static RAM cell is shown in FIG. In this figure, 1 a + 1 b is the load element, 2
A and 2b are driver transistors, A and B are data holding nodes, and these constitute a flip-flop. 2c.

2d is a transfer element for data transfer. In FIG. 4, when data is held, one of the two data holding nodes A and B is at a potential close to the power supply Vdd, and the other is at the ground potential.

FIG. 5 shows a pattern plan view of a typical resistive load type static RAM cell using polysilicon high resistance elements as load elements 1a and lb, which is applied to the present invention. In this figure, region 3 (including diffusion layer regions 3a, 3a', 3b and 3b') is an element region, and the other region F is an element isolation region. Regions 4, 4a, and 4b represent first polysilicon electrodes. Region 5 (including regions 5a, 5b and 5C) represents the second polysilicon film. The regions (5a, 5b, and 5c) indicated by dotted lines in region 5 are heavily doped with impurities and serve as wiring, and the other regions are not doped with impurities (or are lightly doped). plays the role of a high-resistance element in the 6a
, 6b are contacts connecting the first polysilicon electrode and the diffusion layer region, and 7g and 7b are contacts connecting the second polysilicon film and the first polysilicon electrode.

Correspondence with the circuit diagram shown in FIG. 4 is, for example, in the transistor 2a, the diffusion layer 3a is the source, 3a' is the drain,
It is constructed using polysilicon electrode 4a as a gate.

Further, the data holding node A is composed of a diffusion layer 3a', a first polysilicon electrode 4b, and a second polysilicon electrode 5a. Here, the diffusion layer 3a' and the electrode 4b are connected to the contact 6
In a, electrodes 4b and 5a are connected by a contact 7a, respectively. The transistor 2b uses the diffusion layer 3b as a source,
The electrode 3b' is a drain and the electrode 4b is a gate. Data holding node B is symmetrical to A and is composed of a diffusion layer 3b' and electrodes 4a and 5b. Electrode 4
are the gate electrodes of the trassofa MOS elements 2c and 2d, and the wiring 5C is a part that connects the resistors la and lb.

FIG. 1 shows a cell according to an embodiment of the present invention corresponding to FIG. This is the static RAM cell shown in FIG. 5 with the addition of tunnel insulating film regions 8a and 8b and floating gates 9a and 9b. FIG. 2 shows a cross-sectional view of the portion taken along the line CC in FIG. 1, and the portions of the tunnel insulating film 8a and floating gate 9a also correspond to FIG. In FIG. 2, polysilicon film 1
a (5) is, for example, an N-type (high resistance) layer with a very low impurity concentration. Further, 8 and 11 are insulating films, and 10 is a silicon substrate. The above polysilicon films la, 5b, 5
c, the insulating film 8 and the floating gate 9b can be considered as a type of MOSFET, and depending on whether or not electrons are injected into the floating gate 9b, the resistance value of the polysilicon resistor Nib can be increased. , you can make it smaller. The same applies to the resistive film 1b.

The electrical operation will be explained below using FIGS. 1 and 2.

First, consider a case where data holding node A is at the power supply Vdd potential. In this case, data holding node B is at ground potential. Therefore, the first polysilicon electrode 4a and the second polysilicon electrode 5b are at ground potential. A power supply potential Vdd is applied to the second polysilicon electrode 5c.

In this state, no charge is stored in floating gate 9b. Now, here is the appropriate Vdd for the electrode 5C.
When a higher potential is applied, electrons are injected from the electrode 4a through the tunnel insulating film 8b, and the floating gate 9
b becomes negatively charged. When this positive potential is applied to the electrode 5c, the electric field applied to the other tunnel insulating film 8a is small, and no electron injection occurs. That is, the first polysilicon electrode 4b (namely node A) is at Vdd potential,
This is because the potential difference between both sides of the tunnel insulating film 8a is small. In this way, a potential at which a tunnel current flows in one tunnel insulating film and does not flow in the other tunnel insulating film is referred to as the "potential higher than the appropriate power supply Vdd". According to the above principle, one bit of information can be stored depending on which floating gate is charged.

Now, this information is read out as follows.

That is, the power supply is turned off at -degrees, and both nodes A and B are placed in a state where no charge is stored (ground potential). Next, when the power is turned on, the conductance of the high-resistance element differs depending on whether negative charge is stored in the floating gate below, and the high-resistance element with high conductance is connected to the power supply. The potential of the node increases faster than the potential of the other node. The node (A or B) whose potential rose faster becomes data 01°, which means that information has been read. In the above read operation, P is applied to the high resistance element.
This means that it is operating as a channel MO8PET. Therefore, it is desirable that the second polysilicon electrode 5C serving as the source electrode be doped to be P-type.

Note that when the above write/read operation is performed (once), the data is inverted. The above write operation is the first write after manufacturing this memory device, and from the second time onwards, if opposite data has been written previously, the same amount of negative charge will be stored in both floating gates. and information is lost. Therefore, rewriting is not possible in this state. However, after injecting electrons into the required floating gate in the above method, the charges stored in the opposite floating gate can be released.

This charge discharge method will be explained using FIG. 3.

FIG. 3 shows a pair of floating gates 9a in the cell,
9b and their upper and lower electrodes are schematically shown. Now, a negative charge -Q is already stored in the floating gate 9b by the method described above (applying an appropriate potential higher than Vdd to the electrode 5), and a state in which the previously injected charge remains in the floating gate 9a. think. When a suitable negative potential is applied to the electrode 5 in this state, a high electric field is applied to the tunnel insulating film 8a, a tunnel current flows, and the negative charge (i1! child) stored in the floating gate 9a is released. Such a high electric field is not applied to the tunnel insulating film 8b, and the negative charge -Q of the floating gate 9b is preserved. At this time, the first polysilicon electrode 4b
The potential Vdd of is maintained by the charge stored in the capacitance associated with the data holding node A. Therefore, the negative charges (electrons) of the floating gate 9a pass through the tunnel insulating film 8a to 1! The potential of the electrode 4b decreases as the charge is discharged to the pole 4b, but since the positive charge stored in the data holding node is larger than Q, a sufficient amount of negative charge can be discharged from the floating gate 9b. In this way, rewriting is possible.

Next, a method for forming the main parts of the storage device will be explained.

A conventional resistive load type static RAM (E/R type SRAM) process technology using a polysilicon high resistance element as a load element is used to form up to the first polysilicon electrode. Next, for example, 3,000 5i02 films are deposited by the CVD method, and holes in the pattern for the tunnel insulating films 8a and 8b in FIG. 1 are formed using photolithography.
Form into two films. Next, for example, oxidation of 50 people is performed. This forms the tunnel insulating film. Next, a polysilicon film is deposited by, for example, 700 layers, and the floating gates 9a and 9b shown in FIG.
A polysilicon film with a pattern is left. Next, the surface of the floating gate is oxidized, for example, by 250 oxides. Thereafter, the steps after forming the high resistance element are performed again using the conventional E/R type SRAM process technology.

[Effects of the Invention] As explained above, according to the present invention, since the floating gate is sandwiched between the electrode layer and the resistance layer via the tunnel insulating film, it is different from the conventional E/R type thrust static RAM cell. A semiconductor memory device having a cell having the same area as that of a static RAM and an EEFROM can be realized.

[Brief explanation of the drawing]

FIG. 1 is a pattern plan view showing one embodiment of the present invention, and FIG.
The figure is a cross-sectional view taken along line C-C in Figure 1, Figure 3 is a cross-sectional configuration diagram for explaining the operation of Figure 1, Figure 4 is a circuit diagram of a conventional static RAM cell, and Figure 5. is a pattern plan view of the same cell. la, lb...load element, 2a, 2b...driver transistor, 3 (3a, 3a' 3b and 3b'
)...element region, 3a, 3a', 3b. 3b'... Diffusion layer region, 4.4a, 4b... First polysilicon electrode, 5 (including 5a, 5b and 5C)...
・Second polysilicon film, 5 a * 5 b, 5 c
...Highly doped portion of the second polysilicon film, 5a, 5b... Contacts connecting the first polysilicon electrode and the diffusion layer region, 7a, 7b... Second polysilicon film and a contact connecting the first polysilicon electrode, 8... Insulating film% 8a, 8b... Tunnel insulating film, 9a, 9b... Floating gate, 1
0...Silicon substrate. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 1

Claims (3)

[Claims] (1) A flip-flop circuit equipped with a load resistor and a driver transistor, a floating gate that changes the value of the load resistor with charge, and the charge is injected into the floating gate through a tunnel insulating film or the charge is charged from the floating gate. What is claimed is: 1. A semiconductor memory device comprising means for emitting . (2) The tunnel insulating film is a thin insulating film that injects charges into or releases charges from the floating gate by flowing a tunnel current therethrough. semiconductor storage device. (3) the load resistor is made of high resistance polysilicon;
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device faces the floating gate with a thin insulating film interposed therebetween.