JPH0226051A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0226051A JPH0226051A JP17603288A JP17603288A JPH0226051A JP H0226051 A JPH0226051 A JP H0226051A JP 17603288 A JP17603288 A JP 17603288A JP 17603288 A JP17603288 A JP 17603288A JP H0226051 A JPH0226051 A JP H0226051A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- melting point
- high melting
- present
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 238000002844 melting Methods 0.000 claims description 13
- 230000008018 melting Effects 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- -1 oxygen ions Chemical class 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing wiring for a semiconductor device.
従来の半導体装置の製造方法は特開昭61−14273
9の様に、絶縁膜上およびコンタクト開孔部表面上に高
融点金属層を形成後、熱処理して金属表面を窒化金属に
し、次に窒化金属上に配線金属を形成するものであった
。The conventional method for manufacturing semiconductor devices is disclosed in Japanese Patent Application Laid-Open No. 14273/1986.
9, after forming a high melting point metal layer on the insulating film and the surface of the contact opening, heat treatment was performed to make the metal surface a metal nitride, and then a wiring metal was formed on the metal nitride.
近年、半導体装置の微細化が進み、コンタクト開孔部も
縮少化されている。これに伴いコンタクト開孔部の配線
金属の被覆性を向上させるためバイアススパッタ法が用
いられているが、この方法では、基板にバイアスを印加
することに゛より基板温度が上昇する。これにより配線
金属(例えばA」)がその下の接合を突き抜け、リーク
電流が増大する。In recent years, as semiconductor devices have become smaller, contact openings have also become smaller. Accordingly, a bias sputtering method has been used to improve the coverage of the wiring metal in the contact opening, but in this method, the temperature of the substrate increases due to the application of a bias to the substrate. This causes the wiring metal (eg, A'') to penetrate the underlying junction, increasing leakage current.
また、近年、半導体装置の配線の多層化も進んでおり、
配線間の眉間絶縁膜や上層の配線を形成する時の熱によ
り、上記と同じ様にリーク電流が増大する。In addition, in recent years, the wiring of semiconductor devices has become more multilayered.
The leakage current increases in the same way as described above due to the heat generated when forming the glabellar insulating film between the wirings and the upper layer wiring.
前記従来技術は、以上のような工程の熱に対し配線金属
が接合を突き抜けるのを防止する作用が弱いという課題
を有する。即ち配線中の金属が、後工程の熱により窒化
金属中を拡散し、接合を突き抜け、リーク電流が増大す
る。The above-mentioned conventional technology has a problem in that the effect of preventing the wiring metal from penetrating the bond due to the heat of the process described above is weak. That is, the metal in the wiring diffuses into the metal nitride due to the heat of the subsequent process, penetrates the junction, and increases leakage current.
そこで本発明は、このような課題を解決するもので、そ
の目的とするところは、後工程等で熱が加わっても配線
金属が拡散せず、接合のリーク電流も増大しない、量産
性と信頼性の高い電極の製造方法を提供するところにあ
る。The present invention has been developed to solve these problems, and its purpose is to achieve mass productivity and reliability by preventing wiring metal from diffusing even when heat is applied in post-processing, and preventing junction leakage current from increasing. The purpose of the present invention is to provide a method for manufacturing an electrode with high properties.
本発明の半導体装置の製造方法は、絶縁膜上およびコン
タクト開孔部表面上に高融点金属層を形成した後、熱処
理して、次に該高融点金属層にシリコンまたは酸素をイ
オン打ち込みした後、該高融点金属層上に導電配線を形
成することを特徴とする。The method for manufacturing a semiconductor device of the present invention includes forming a high melting point metal layer on the insulating film and the surface of the contact opening, heat-treating the layer, and then ion-implanting silicon or oxygen into the high melting point metal layer. , a conductive wiring is formed on the high melting point metal layer.
第1図(a)〜(c)は本発明の実施例における製造工
程図である。以下、第1図に沿って本発明を説明する。FIGS. 1(a) to 1(c) are manufacturing process diagrams in an embodiment of the present invention. The present invention will be explained below with reference to FIG.
まずシリコン基板103の表面に拡散層108を形成す
る0本実施例では103はP形シリコン基板、108は
N膨拡散層として説明する0次に絶縁膜102を形成し
、コンタクトの開孔部を形成した後、絶縁膜上およびコ
ンタクト開孔部表面上に高融点金属層101を形成する
0本実施例では高融点金属としてチタンをスパッタした
。(第1図(a))
次に熱処理を行なう、熱処理は通常の横型酸化炉でも行
なえるが、本実施例では高速熱処理炉としてランプアニ
ール炉を用いた。これによりコンタクト開孔部のN型拡
散層上のチタンは表面が窒化チタン105、基板との界
面にはチタンシリサイド106が形成される。さらに窒
化チタン表面にシリコンまたは酸素104をイオン打ち
込みする。この時のドーズ量は10 ′4〜10 ”c
s−’、加速電圧は20〜40KeVを用いた。これに
より窒化チタン105中のシリコンまたは酸素濃度はl
Q l 8〜1020am−3となる。(第1図(b
))その後、イオン打ち込みした窒化チタン105上に
導電配線107を形成する0本実施例ではAjをスパッ
タした。(第1図(C))
本発明の上記実施例において、スパッタされたチタン1
01はランプアニール炉で熱処理することにより、窒化
チタン105となる。従来技術ではこの窒化チタンは柱
状晶をなし、これのダレインにそって配線中の金属が後
工程の熱によって拡散し接合リークに至る0本発明にお
いては、上記窒化チタンにシリコンまたは酸素をイオン
打ち込みによって導入する。このシリコンまたは酸素は
窒化チタンの上記ダレインに存在し、本実施例で言えば
A1の拡散を防止する役割をはなす。First, a diffusion layer 108 is formed on the surface of a silicon substrate 103.In this embodiment, 103 is a P-type silicon substrate, and 108 is an N-swelled diffusion layer.Next, an insulating film 102 is formed, and a contact opening is formed. After the formation, a high melting point metal layer 101 is formed on the insulating film and the surface of the contact opening.In this example, titanium was sputtered as the high melting point metal. (FIG. 1(a)) Next, heat treatment is performed.Although the heat treatment can be performed in a normal horizontal oxidation furnace, in this example, a lamp annealing furnace was used as the high-speed heat treatment furnace. As a result, titanium nitride 105 is formed on the surface of the titanium on the N-type diffusion layer in the contact opening, and titanium silicide 106 is formed at the interface with the substrate. Further, silicon or oxygen 104 is ion-implanted into the titanium nitride surface. The dose at this time is 10'4~10''c
s-', an acceleration voltage of 20 to 40 KeV was used. As a result, the silicon or oxygen concentration in titanium nitride 105 is 1
Q l 8 to 1020 am-3. (Figure 1(b)
)) Thereafter, a conductive wiring 107 was formed on the ion-implanted titanium nitride 105 by sputtering. (FIG. 1(C)) In the above embodiment of the present invention, sputtered titanium 1
01 becomes titanium nitride 105 by heat treatment in a lamp annealing furnace. In the conventional technology, this titanium nitride forms a columnar crystal, and the metal in the wiring is diffused along the dale line by heat in a subsequent process, leading to junction leakage.In the present invention, silicon or oxygen is ion-implanted into the titanium nitride. Introduced by This silicon or oxygen exists in the drain of titanium nitride, and in this embodiment, plays the role of preventing diffusion of A1.
第2図は本発明により、リーク電流が低減されることを
示した図である。Aj配線を形成後450℃、3Hの熱
処理を加えた後の接合のリーク電流分布を示している。FIG. 2 is a diagram showing that leakage current is reduced by the present invention. It shows the leakage current distribution of the junction after the Aj wiring was formed and heat treated at 450° C. for 3 hours.
試料は10000個のコンタクト開孔部を持つN” /
P−接合であり、グラフの縦軸は度数、横軸はリーク電
流の対数を現わしている。従来技術によるコンタクトの
接合リーク電流分布は10%〜20%のリークが発生し
ている(第2図(a))が、本発明によるものはリーク
が発生していない、(第2図(b))上記実施例では導
電配線としてAjを用いたが、タングステン等の高融点
金属配線を用いても、同等の効果を有する。また、上記
実施例ではN”/P−拡散層に対して効果があることを
示したが、P” /N−拡散層に対しても同等の効果を
有する。The sample has 10,000 contact holes.
It is a P-junction, and the vertical axis of the graph represents the frequency, and the horizontal axis represents the logarithm of the leakage current. The junction leakage current distribution of the contact according to the prior art shows that 10% to 20% leakage occurs (Fig. 2(a)), but no leakage occurs in the contact according to the present invention (Fig. 2(b)). )) In the above embodiment, Aj was used as the conductive wiring, but the same effect can be obtained even if high melting point metal wiring such as tungsten is used. Further, in the above embodiment, it was shown that the present invention is effective for the N''/P- diffusion layer, but the same effect can be obtained for the P''/N- diffusion layer.
また本発明によると導電配線の形成にスパッタ法を用い
た場合、導電配線と高融点金属配線とのぬれ性が良くな
り、コンタクト開孔部の段差被覆性が向上するという効
果も合わせ持つ。Further, according to the present invention, when a sputtering method is used to form the conductive wiring, the wettability between the conductive wiring and the high melting point metal wiring is improved, and the step coverage of the contact opening is also improved.
その結果この部分でのエレクトロマイグレーションの不
良が起こりにくくなり、半導体装置の信頼性が向上する
。As a result, electromigration defects in this portion are less likely to occur, improving the reliability of the semiconductor device.
以上述べたように本発明によれば、絶縁膜上およびコン
タクト開孔部表面上に高融点金属層を形成した後、熱処
理して、次に該高融点金属層にシリコンまたは酸素をイ
オン打ち込みすることにより、配線形成後の熱工程で配
線金属が拡散するのを防止して接合リークを防ぎ、安定
したコンタクトが得られるという効果を有する。また、
上層の配線金属とのぬれ性が向上し、段差被覆性が良く
なり、その結果エレクトロマイグレーション特性が向上
するという効果も有する。As described above, according to the present invention, a high melting point metal layer is formed on the insulating film and the surface of the contact opening, and then heat treated, and then silicon or oxygen ions are implanted into the high melting point metal layer. This has the effect of preventing wiring metal from diffusing during a thermal process after wiring formation, preventing junction leakage, and providing stable contact. Also,
It also has the effect of improving wettability with the upper layer wiring metal, improving step coverage, and improving electromigration characteristics as a result.
第1図(a)〜(c)は本発明の一実施例を示す製造工
程図。
第2図(a)、(b)は本発明の効果を表わす接合リー
ク電流分布のグラフで第2図(a)が従来技術、第2図
(b)が本発明によるもの。
・チタン
・絶縁膜
・P形シリコン基板
・シリコンまたは酸素
・窒化チタン
・チタンシリサイド
・Aj
・N膨拡散層
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉(他1名)稟10(c
)FIGS. 1(a) to 1(c) are manufacturing process diagrams showing one embodiment of the present invention. FIGS. 2(a) and 2(b) are graphs of junction leakage current distributions showing the effects of the present invention, with FIG. 2(a) being the conventional technique and FIG. 2(b) being the graph according to the present invention.・Titanium・Insulating film・P-type silicon substrate・Silicon or oxygen・Titanium nitride・Titanium silicide・Aj ・N expansion diffusion layer and above Applicant: Seiko Epson Corporation Representative Patent attorney Masatoshi Kamiyanagi (1 other person) Rin 10 ( c.
)
Claims (1)
を形成した後、熱処理して、次に該高融点金属層にシリ
コンまたは酸素をイオン打ち込みした後、該高融点金属
層上に導電配線を形成することを特徴とする、半導体装
置の製造方法。After forming a high melting point metal layer on the insulating film and the surface of the contact opening, heat treatment is performed, and then silicon or oxygen ions are implanted into the high melting point metal layer, and then conductive wiring is formed on the high melting point metal layer. 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17603288A JPH0226051A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17603288A JPH0226051A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0226051A true JPH0226051A (en) | 1990-01-29 |
Family
ID=16006533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17603288A Pending JPH0226051A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0226051A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5356835A (en) * | 1991-03-29 | 1994-10-18 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
US5849634A (en) * | 1994-04-15 | 1998-12-15 | Sharp Kk | Method of forming silicide film on silicon with oxygen concentration below 1018 /cm3 |
US5877031A (en) * | 1994-07-07 | 1999-03-02 | Hyundai Electronics Industries Co, Ltd | Method for forming a metallic barrier layer in semiconductor device |
US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
US6207558B1 (en) | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
US6605531B1 (en) | 1997-11-26 | 2003-08-12 | Applied Materials, Inc. | Hole-filling technique using CVD aluminum and PVD aluminum integration |
-
1988
- 1988-07-14 JP JP17603288A patent/JPH0226051A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5356835A (en) * | 1991-03-29 | 1994-10-18 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
US5849634A (en) * | 1994-04-15 | 1998-12-15 | Sharp Kk | Method of forming silicide film on silicon with oxygen concentration below 1018 /cm3 |
US6091152A (en) * | 1994-04-15 | 2000-07-18 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
US5877031A (en) * | 1994-07-07 | 1999-03-02 | Hyundai Electronics Industries Co, Ltd | Method for forming a metallic barrier layer in semiconductor device |
US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6355560B1 (en) | 1995-11-21 | 2002-03-12 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6743714B2 (en) | 1995-11-21 | 2004-06-01 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
US6605531B1 (en) | 1997-11-26 | 2003-08-12 | Applied Materials, Inc. | Hole-filling technique using CVD aluminum and PVD aluminum integration |
US6207558B1 (en) | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
US6368880B2 (en) * | 1999-10-21 | 2002-04-09 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
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