JP2001229074A - Memory controller and information processor and memory control chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems that even when a plurality of buffers are simply prepared, or the capacity is increased, sufficient effects can not be obtained, or the control is made to be complicated in quickening memory access by look- ahead in a conventional technique, and that performance is more damaged due to the execution of look-ahead in some cases. SOLUTION: In a memory controller 10 connected through a bus to bus masters 31 and 32 for controlling access to a memory 20, read buffers 11 and 12 for temporality holding the data read from the memory 20 are prepared just for the number of bus masters corresponding to the bus masters 31 and 32, and when a memory read request is received from the bus master 31 or 32, the requested data and the succeeding data are read from the memory 20, and preserved in the read buffer 11 or 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, an information processing device, and a memory control chip. More particularly, the present invention relates to memory access by prefetching subsequent data in a burst transfer for transferring continuous data collectively. Related to technology for speeding up.

[0002]

2. Description of the Related Art When a bus master such as a CPU or an I / O controller that accesses a memory reads data from the memory, the read operation is often performed at a continuous address. Access is faster. Along with this, many memory devices corresponding to burst transfer have been produced.

In order to further speed up memory access, data subsequent to requested data is read from the memory in advance and temporarily stored in a buffer. There is known a pre-reading operation for speeding up by returning the data. In this case, the buffer needs to additionally have a capacity necessary for burst transfer by prefetch.

Further, since each bus master accesses a different address in many cases, for example, when the bus master A accesses the address A and then the bus master B accesses the address B, the A + N address (A + N) read by the prefetch of the bus master A is used. N indicates the size of the burst transfer) and is invalidated by the subsequent bus master B because it is unnecessary,
Further, reading of address B may be delayed due to pre-reading.

[0005] In order to avoid this, a method of increasing the buffer capacity so as to keep it from being invalidated by another subsequent bus master, or providing a plurality of buffers to be used in accordance with the requested address is provided. However, when the access of each bus master temporarily concentrates on a specific buffer, sufficient effects cannot be obtained, or when the capacity is increased, the control for managing the data held in the buffer becomes complicated. Or was.

[0006]

As described above, in the prior art, in order to speed up memory access by prefetching,
Even if you simply have multiple buffers or increase the capacity,
There were problems that a sufficient effect could not be obtained and that the control became complicated. Further, there is a problem that performance may be impaired by executing prefetching.

A main object of the present invention is to provide a memory which can more reliably access a high-speed memory without performance degradation due to a prefetch operation even when a large number of bus masters simultaneously perform read access to a memory control device. A control device, an information processing device, and a memory control chip are provided.

[0008]

A first memory control device of the present invention is connected to a plurality of bus masters via a bus and controls access to a memory for storing a program or data in response to a request from the bus master. A plurality of read buffers for temporarily holding data read from the memory are provided corresponding to the number of the bus masters.

A second memory control device of the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing a program or data in response to a request from the bus master, and controls data read from the memory. Read buffers for temporarily holding the same number as the number of the bus masters corresponding to the bus masters. When a memory read request is received from the bus master, the requested data and subsequent data are read from the memory. Means for reading and holding the read buffer corresponding to the requested bus master in the read buffer.

A third memory control device of the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing programs and data in response to a request from the bus master, and stores data read from the memory. The number of read buffers that temporarily hold the number of bus masters corresponds to the number of the bus masters. When a memory read request is received from one bus master A of the bus masters, one of the read buffers Referring to the corresponding read buffer A, if there is requested data in the read buffer A, the data in the read buffer A is returned to the bus master A. If there is no requested data in the read buffer A, Read data from the memory and return it to the bus master A, and read subsequent data following the requested data from the memory. And means for temporarily holding the read buffer A reading.

According to a fourth memory controller of the present invention, in addition to the third memory controller, when a memory read request is received from one of the bus masters A, the bus master A is used by one of the read buffers. And means for invalidating the data held in the read buffer A when the data held in the read buffer A is not the requested data by referring to the read buffer A corresponding to.

A fifth memory control device of the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing programs and data in response to a request from the bus master, and controls data read from the memory. The number of read buffers that temporarily hold the number of bus masters corresponds to the number of the bus masters. When a memory read request is received from one bus master A of the bus masters, one of the read buffers Referring to the corresponding read buffer A, if there is requested data in the read buffer A, the data in the read buffer A is returned to the bus master A. If there is no requested data in the read buffer A, Read data from the memory and return it to the bus master A, and the memory read request is a burst transfer memory read. Subsequent data only subsequent to the requested data if the request was issued is read out from the memory comprises means for temporarily holding the read buffer A.

According to a sixth memory control device of the present invention, in addition to the fifth memory control device, when a memory read request is received from one of the bus masters A, the bus master A is used by one of the read buffers. , When the data held in the read buffer A is not the requested data and the memory read request is a burst transfer memory read request, the data is held in the read buffer A. Means for invalidating the data that has been set.

A seventh memory control device of the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing a program or data in response to a request from the bus master, and stores data read from the memory. The number of the read buffers for temporarily storing the data corresponds to the number of the bus masters corresponding to the bus masters, and one write buffer for temporarily storing the write data to the memory.

An eighth memory control device according to the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing programs and data in response to a request from the bus master, and stores data read from the memory. Have the same number of read buffers as the number of the bus masters corresponding to the bus masters, and when a memory read request for burst transfer is received from the bus master, the requested data and subsequent data Means for reading from the memory and holding the read buffer corresponding to the requested bus master, a write buffer for temporarily holding write data to the memory, and , Referring to all the read buffers, the read buffer holding the data at the same address as the write request. And means for disabling the data buffers.

A ninth memory control device according to the present invention is connected to a plurality of bus masters via a bus, controls access to a memory for storing programs and data in response to a request from the bus master, and controls data read from the memory. Have the same number of read buffers as the number of the bus masters corresponding to the bus masters, and when a memory read request for burst transfer is received from the bus master, the requested data and subsequent data Means for reading from the memory and holding the read buffer corresponding to the requested bus master, a write buffer for temporarily holding write data to the memory, and Writing the write data to the memory, and referring to all the read buffers, Also to read buffer that holds the data of the same address as requested write attempts and means for overwriting the write data.

An information processing device according to the present invention connects to a memory for storing programs and data, a memory control device for controlling access to the memory, a plurality of bus masters, and the memory control device and the plurality of bus masters. A bus, and the memory control device has the means of the first to ninth memory control devices.

A memory control chip according to the present invention mounts the first to ninth memory control devices.

[0019]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention, and also includes a memory control device and a memory control chip. The information processing apparatus includes a bus master 31, a bus master 32 connected to the bus X1,
It includes a memory control device 10, a bus arbiter 30 of a circuit for arbitrating the bus X1, and a memory 20 connected to the memory control device 10 and controlled by the memory control device 10. Other functions included in the information processing apparatus are not particularly shown because they are not particularly limited.

The bus masters 31 and 32 are a CPU for executing programs and executing calculations, and an IO for controlling transfer between an input / output device or an input / output control device and the memory 20 or the CPU.
A control unit and the like. A configuration is also conceivable in which the IO control unit performs control by providing a bus at a lower level. In FIG. 1, the bus master is 2
But the number of connections is not limited,
Any number of bus masters may be connected according to the needs of the device.

The information processing device operates as a main unit such as a mainframe or a personal computer, an information processing device connected to a main unit or a network such as an auxiliary storage device or a printing device, or a circuit shown in FIG. For specific applications, etc. It is also effective to implement the memory control device 10 by mounting it on a one-chip LSI (large-scale integrated circuit). However, the memory control device 10 may be separately mounted on a plurality of chips.

The memory control device 10 temporarily stores write data received in response to a write request from the bus master 31 or the bus master 32, and temporarily stores data read from the memory 20 in accordance with a read request from the bus master 31. A read buffer 11 for temporarily storing data read from the memory 20 in accordance with a read request from the bus master 32;
A switching circuit 14 for switching between the read buffer 11 and the read buffer 12, and a control unit 1 for controlling the memory control device 10
5 is included. The read buffers 11 and 12 have FIFOs (Files) having a plurality of entries so that read data can be continuously output to the common bus X1 in response to burst transfer.
st in first out).

The driver circuit 16 and the receiver circuit 17
The driver circuit 1 transmits and receives signals to and from the common bus X1.
9. The receiver circuit 18 transmits and receives signals to and from the memory 20. A signal line received from the common bus X1 includes a command (CMD) signal including a command and an address / data (A / D) signal including an address and data, and is received by the receiver circuit 17 and output as a signal X4. . Of the signal X4, data is connected to the write buffer 13, and commands and addresses are connected to the control unit 15. Although the number of write buffers 13 is one, a plurality of write buffers 13 may be provided.

Next, the configuration of the control unit 15 will be described with reference to FIG. The address register 51 and the address register 52 hold the addresses of data read in response to read requests from the bus master 31 and the bus master 32, respectively. When a plurality of read data are held in the read buffer 11 and the read buffer 12, the address of the previously read data is held, and when the data is output from the read buffer 11 or 12, the address register 5
The address value in 1 or 52 is updated. Common bus X1
When a new request is received from the
The address held in 1 or 52 and the requested address are compared by the comparison circuits 53 and 54, and the result is compared with the control circuit 5
Sent to 5. The signal X31 is a control signal or an address signal for the memory 20 created by the control circuit 55 based on the command signal X41 and the address / data signal X42.

The control circuit 55 is connected to the bus arbiter 30 by a signal X2 composed of several control signals, controls transmission and reception of signals to and from the common bus X1, and controls a command signal X4.
1 receives the command of the common bus X1, and controls the memory control device 10 in order to execute a series of procedures such as writing and reading to and from the memory 20 according to the request content of the command. The management circuit 61 manages the number of read data held in the read buffer 11.
2 is a circuit for managing the number of read data held in the read buffer 12. An empty buffer means that the number of data held is "0". These management circuits have a write pointer and a read pointer,
It is known that the circuit is configured by a circuit for detecting the number of data to be held from these differences, and thus a detailed description is omitted.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a timing chart for explaining the operation of the embodiment of the present invention. In FIG.
In a state where there is no request being processed by the memory control device 10, a read request for the address a is received from the bus master 31, then a read request for the address p is received from the bus master 32, and furthermore, an address that is continuous from the previous read request In the case where there is a read request for address e.

Here, the common bus X1 will be described.
The common bus X1 is a clock synchronous bus. Addresses and data are transferred in a time-division manner by a bidirectional address / data signal X12, and the maximum burst length of data is 4. The command transferred by the command signal X11 of the common bus X1 and the address are sent from the bus master 31 or 32 when the command start signal is active.
The timing from the transmission of the address and the command until the start of the write or read data transfer is variable, and the ready signal indicates the transmission timing. When writing to the memory 20, the bus master 31 or 32
Outputs a ready signal, and when reading from the memory 20, the memory controller 10 outputs a ready signal.

For the sake of simplicity, the width of the address / data signal of the common bus X1 and the data width of the signal X32 of the memory 20 are assumed to be 4 bytes, and the required address of the burst transfer is one burst transfer amount. The unit is 16 bytes, that is, a multiple of 16. The burst length is fixed at 4. However, the configuration of the common bus X1 is not limited to the configuration described here, and the present invention can be applied to another configuration.

First, the bus master 31 issues a bus use right request to the bus arbiter 30 to make a burst transfer read request from the memory 20, obtains the use right, and at a timing t1, a command start signal and an address. "a" and a memory read request command having a burst length of 4 are output. Control circuit 55 through receiver circuit 17
Receives the above command and address, and
The status of the read buffer 11 corresponding to 1 is checked. Here, the address held in the address register 51 and the information on the number of data held in the read buffer 11 are managed by the comparison circuit 53 in order to confirm whether or not the data to be read is held in the read buffer 11. Circuit 6
Confirm with 1.

In the request at t1, since all the preceding requests have been processed, the read buffer 11 is empty, and the control circuit 55 instructs the memory 20 to store the requested burst length 4 and the prefetch for a total of 8 burst lengths. Is read. The first four data (A to D) read out are stored in the read buffer 11 one after another at every clock, and subsequently output to the common bus X1 through the switching circuit 14. At this time, the control circuit 55 outputs a ready signal to the signal X2 to notify that the read data has been output. The bus master 31 receives read data (A to D) from the common bus X1 by a ready signal.

As described above, the first four read data (A to D) are immediately output to the common bus X1, and therefore, do not remain in the read buffer 11, but the remaining four read data (E to H). Are held in the read buffer 11, and the address "e" of the data "E" is held in the address register 51. Here, the address “e” has a value of “a + 16”.

Next, upon obtaining the right to use the bus, the bus master 32 outputs a command start signal at a timing t2, and at the same time, outputs a read request command having an address "p" and a burst length of 4. The memory control device 10 confirms the status of the read buffer 12 corresponding to the bus master 32, similarly to the operation of the request at the timing t1. Read buffer 12
Is empty, the control circuit 55 reads out the data corresponding to the required burst length 4 and the read-ahead amount for the memory 20 for a total of 8 burst lengths. The first four data (PS) read out are sequentially read out from the read buffer 12 every clock.
And then output to the common bus X1 through the switching circuit 14. At this time, the control circuit 55 simultaneously outputs the signal X
2 to output a ready signal to notify that read data has been output. The bus master 32 receives read data (PS) from the common bus X1 by a ready signal.

As described above, the first four read data (PS) are immediately output to the common bus X1, so that they do not remain in the read buffer 12, but the remaining four read data (T to W). Is stored and held in the read buffer 11, and the address of the data "T" is stored in the address register 52.
p + 16 "is held.

Next, the bus master 31 sends the previous address "
burst length 4 of address "e" (= a + 16) following "a"
And a command start signal are output at timing t3. Upon receiving the request, the memory control device 10 checks the status of the read buffer 11. In this case, since the read buffer 11 holds valid read data, the read request address “e” supplied at X42 and the address “e” held in the address register 51 are stored.
Are compared by the comparison circuit 53 and the control circuit 55 is notified that they match.

When the coincidence is notified, the management circuit 61 further confirms that data of the requested burst length 4 is held in the read buffer 11. In this case, since there is data corresponding to four burst lengths, the control unit 15 does not read the data into the memory 20, and simultaneously reads the ready signal with the read buffer 11.
(E to H) are output to the common bus X1 four times continuously through the switching circuit 14. The bus master 31 receives the data (E to H) from the common bus, and the operation of the read request for the address “e” is completed. The read buffer 11 becomes empty because it has output the data (E to H) it has held.

As described above, a read request for the address "e" can return read data from the read buffer 11 without accessing the memory 20, so that a read request to the memory 20 can be processed at a high speed. it can. In addition, the state of the read buffer 11 is held unchanged by the request of the address “p” from the bus master 32 received between the request of the address “a” and the address “e” from the bus master 31 and the data (E to H) is held. You can continue to do. This is realized by simple control by providing a read buffer for each bus master.

Although not shown in FIG. 3, the timing t3
A description will be given of a case where a read request of the burst length 4 of the address “z” that is not continuous with the address “a” is executed from the bus master 31. In this case, since the read buffer 11 holds valid data, the request address "z" is compared with the address register 51 by the comparison circuit 53, and a mismatch is notified to the control circuit 55. When the control circuit 55 knows that the data held in the read buffer 11 is not the requested data, it invalidates the data held in the read buffer 11. The control circuit 55 reads out the required data from the address “z” and reads out the burst length 8 from the address “z” by combining the burst length 4 of the request and the read-ahead amount, and sends the requested data to the bus master 31. The data is returned and the read-ahead data is held in the read buffer 11.

As described above, if the subsequent read addresses are not consecutive even after the pre-reading is executed, the pre-read data becomes invalid, and the pre-read processing for the memory 20 is unnecessary. Therefore, depending on the case, waiting for the end of the prefetch operation may delay the memory access executed later.

In the conventional configuration having only one read buffer, the prefetched data (E to H) is invalidated by receiving the request at the timing t2 of the bus master 32, and the memory access is delayed. However, in the present invention, since the read buffer is provided for each bus master, when reading is performed at a continuous address in each bus master, the read-ahead data is not invalidated by access of another bus master. In addition, the memory access can be speeded up by using the prefetch data efficiently.

Here, prefetching is performed only when there is no requested data in the read buffer. However, even when there is requested data in the read buffer, prefetching may be further performed. In addition, it is also possible to refer to whether or not there is a next memory access request on the common bus X1 and execute prefetch when there is no next memory access request. However, this requires the addition of dedicated control means, which complicates the control and makes the design difficult. However, the operation described above does not require any special control means and is easy to design.

According to the present invention, the read buffer is provided for each bus master, so that the overall buffer capacity is larger than when one buffer is shared by the bus masters. However, since the control is not complicated, the design is easy and short. It has the advantage that it can be developed in time. Further, in an information processing apparatus having a configuration in which a bus master has expandability, it is necessary to provide a read buffer even for an unmounted bus master, so that an information processing apparatus with less expandability of the bus master is more efficient. It is.

Next, the operation in response to a write request will be described. Specifically, an operation when a write request for the address “e” is received from the bus master 31 at the timing t2 in FIG. 3 will be described.

The bus master 31 outputs a command start signal at the timing t2 and simultaneously outputs a write request for the address "e". Upon receiving this, the control unit 15
Then, the comparison circuit 53 compares the requested address "e" with the address registers 51 and 52, respectively. In this case, since the read buffer 12 is empty, no match occurs regardless of the output of the comparison circuit 54. However, since the read buffer 11 is valid, the output of the comparison circuit 53 is valid and coincides.

If it is determined that the data matches, the read-ahead data held in the read buffer 11 is invalidated, and the read buffer 11 becomes empty. Thereafter, the write data is stored in the write buffer 13 in accordance with the ready signal output from the bus master 31, and the write buffer 13
Write data to

Thereafter, the address "
When a read request for e "is made, the read buffer 11 is empty, and the read is performed to the memory 20, so that the bus master 31 can obtain data in which the data rewrite by the bus master 31 is reflected. Even when the write request for the address "e" at the timing t2 is output not by the bus master 31 but by the bus master 32, the same processing is performed and the address "e" of the read buffer 11 is processed.
Is invalidated, so that subsequent accesses can read correct data.

As described above, since the status of all read buffers is confirmed in the write request, even if data is rewritten to the pre-read data held in the read buffer, the data before the rewrite is erroneously performed. The rewritten data can be read out from the memory 20 and returned correctly without being returned in subsequent access.

The operation for another write request is as follows.
There is a method of writing data to the memory 20 and overwriting the read buffer 11 to match the data. If described based on the operation description of the write request described above, the write request address and the read buffer 1
As a result of the comparison between 1 and 12, when the read buffers 11 match, the data is written from the write buffer 13 to the memory 20 and simultaneously written to the read buffer 11 without invalidating the read buffer 11 as described above. Also overwrites the same data. As a result, the data after rewriting can be read from the read buffer 11 and returned in response to a subsequent read request from the bus master 31.

In the above, the address "e" is sent from the bus master 31.
Has been described, the write request for each of the four bytes at addresses "e + 4 to e + 12" does not match even if the address register 51 is simply compared with the write request address. In the circuit 53, the addresses “e”, “e + 4”, “e + 8”, “e” holding the write request address in the address register 51 are stored.
e + 12 ", and it is necessary to check the number of data held from the information of the management circuit 61 to determine whether or not the write data is held in the read buffer 11.

However, for this purpose, it is necessary to add a circuit for determination. Therefore, in many cases, the requested address of the burst transfer is set to a multiple of 16 bytes which is the maximum burst length, and the burst length is set to 16 bytes. By fixing, the comparison circuit 53 compares only the upper bits excluding the lower 4 bits of the address. This is because the comparison circuit does not have to be complicated for the determination. In the embodiment of the present invention, there is no particular limitation on which of the above methods is used for determination.

As described above, even if a write request for the pre-read data held in the read buffer is executed, it is possible to avoid returning data before writing by mistake and return correct data after writing.

[0051]

As described above, according to the present invention,
By providing a read buffer for each of a plurality of bus masters in the memory control device, even when a plurality of bus masters execute data reading at consecutive addresses in parallel, the read-ahead data can be effectively used without invalidating the pre-read data. There is an effect that unnecessary access to the memory due to invalidation of the prefetch data is reduced, and the memory access can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention, which includes a memory control device and a memory control chip.

FIG. 2 is a block diagram of a control unit 15 according to the embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of the exemplary embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 memory control device 11 read buffer 12 read buffer 13 write buffer 14 switching circuit 15 control unit 20 memory 30 bus arbiter 31 bus master 32 bus master 51 address register 52 address register 53 comparison circuit 54 comparison circuit 55 control circuit 61 management circuit 62 management circuit

Claims (11)

[Claims] 1. A memory controller connected to a plurality of bus masters via a bus and controlling access to a memory for storing programs and data in response to a request from the bus master, temporarily holding data read from the memory. A memory control device comprising: a plurality of read buffers corresponding to the number of the bus masters corresponding to the bus masters. 2. A memory control device connected to a plurality of bus masters via a bus and controlling access to a memory for storing a program and data in response to a request from the bus master, wherein data read from the memory is temporarily held. Read buffers corresponding to the number of the bus masters corresponding to the bus masters, and when a memory read request is received from the bus master, the requested data and subsequent data are read from the memory and the requested data is read. A memory controller for storing the data in the read buffer corresponding to the bus master. 3. A memory controller connected to a plurality of bus masters via a bus and controlling access to a memory for storing programs and data in response to a request from the bus master, wherein the data read from the memory is temporarily held. Read buffers corresponding to the bus masters are provided in correspondence with the number of the bus masters. When a memory read request is received from one of the bus masters A, a read buffer A corresponding to the bus master A is used as one of the read buffers. , If there is requested data in read buffer A, the data in read buffer A is returned to bus master A, and read buffer A
If there is no requested data, the data is read from the memory and returned to the bus master A, and the subsequent data following the requested data is read from the memory and temporarily stored in the read buffer A. Memory control device. 4. When a memory read request is received from one bus master A of the bus masters, one of the read buffers refers to a read buffer A corresponding to the bus master A and is held in the read buffer A. 4. The memory control device according to claim 3, wherein when the data is not the requested data, the data held in the read buffer A is invalidated. 5. A memory controller connected to a plurality of bus masters via a bus and controlling access to a memory for storing programs and data in response to a request from the bus master, wherein data read from the memory is temporarily held. Read buffers corresponding to the bus masters are provided in correspondence with the number of the bus masters. When a memory read request is received from one of the bus masters A, a read buffer A corresponding to the bus master A is used as one of the read buffers. , If there is requested data in read buffer A, the data in read buffer A is returned to bus master A, and read buffer A
If there is no requested data, the data is read from the memory and returned to the bus master A, and the subsequent data following the requested data is read only when the memory read request is a burst transfer memory read request. A memory control device for reading data from a memory and temporarily storing the data in a read buffer A. 6. When a memory read request is received from one of the bus masters A, the one of the read buffers refers to the read buffer A corresponding to the bus master A and is held in the read buffer A. 6. The memory control according to claim 5, wherein when the data is not the requested data and the memory read request is a burst transfer memory read request, the data held in the read buffer A is invalidated. apparatus. 7. A memory control device connected to a plurality of bus masters via a bus and controlling access to a memory for storing a program or data in response to a request from the bus master, wherein data read from the memory is temporarily held. A memory control device comprising: a plurality of read buffers corresponding to the number of the bus masters corresponding to the bus masters; and a single write buffer for temporarily holding write data to the memory. 8. A memory controller connected to a plurality of bus masters via a bus and controlling access to a memory for storing a program or data in response to a request from the bus master, wherein data read from the memory is temporarily held. A plurality of read buffers corresponding to the bus masters, and when receiving a burst transfer memory read request from the bus master, reads out the requested data and subsequent data from the memory. A write buffer for holding the read buffer corresponding to the bus master that has made the request, and temporarily holding write data to the memory; And holds the data at the same address as the write request. Memory controller and wherein the disabling data output buffer. 9. A memory control device connected to a plurality of bus masters via a bus and controlling access to a memory for storing a program and data in response to a request from the bus master, wherein data read from the memory is temporarily held. A plurality of read buffers corresponding to the bus masters, and when receiving a burst transfer memory read request from the bus master, reads out the requested data and subsequent data from the memory. A write buffer for holding the write data to the memory temporarily in the read buffer corresponding to the bus master that has made the request; Write the data and refer to all the read buffers to Memory control apparatus characterized by also override the write data into the read buffer that holds the data of the same address as the write request. 10. An information processing device in which a memory control device for controlling access to a memory for storing programs and data and a plurality of bus masters are connected by a bus, wherein the memory control device is a memory control device according to claim 1. Information processing device that is a device. 11. The memory control device according to claim 1, wherein
A memory control chip mounted on one integrated circuit chip.