JPH0224035B2 - - Google Patents
Info
- Publication number
- JPH0224035B2 JPH0224035B2 JP59208011A JP20801184A JPH0224035B2 JP H0224035 B2 JPH0224035 B2 JP H0224035B2 JP 59208011 A JP59208011 A JP 59208011A JP 20801184 A JP20801184 A JP 20801184A JP H0224035 B2 JPH0224035 B2 JP H0224035B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- resin
- insulating member
- circuit board
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 49
- 239000011347 resin Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 238000006243 chemical reaction Methods 0.000 claims description 22
- 239000011342 resin composition Substances 0.000 claims description 18
- 229920001187 thermosetting polymer Polymers 0.000 claims description 13
- 239000000843 powder Substances 0.000 claims description 12
- 239000011230 binding agent Substances 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 150000002978 peroxides Chemical class 0.000 claims description 6
- 229920013716 polyethylene resin Polymers 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229920002589 poly(vinylethylene) polymer Polymers 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000004925 Acrylic resin Substances 0.000 claims description 2
- 229920000178 Acrylic resin Polymers 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229920001577 copolymer Polymers 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 239000010680 novolac-type phenolic resin Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 229920005749 polyurethane resin Polymers 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229920006337 unsaturated polyester resin Polymers 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- 239000004020 conductor Substances 0.000 description 7
- 238000007639 printing Methods 0.000 description 7
- 230000005855 radiation Effects 0.000 description 6
- CXWXQJXEFPUFDZ-UHFFFAOYSA-N tetralin Chemical compound C1=CC=C2CCCCC2=C1 CXWXQJXEFPUFDZ-UHFFFAOYSA-N 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- -1 paper-phenol boards Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000005062 Polybutadiene Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- JHIVVAPYMSGYDF-UHFFFAOYSA-N cyclohexanone Chemical compound O=C1CCCCC1 JHIVVAPYMSGYDF-UHFFFAOYSA-N 0.000 description 2
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920002857 polybutadiene Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- OAYXUHPQHDHDDZ-UHFFFAOYSA-N 2-(2-butoxyethoxy)ethanol Chemical compound CCCCOCCOCCO OAYXUHPQHDHDDZ-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 206010057040 Temperature intolerance Diseases 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000008543 heat sensitivity Effects 0.000 description 1
- 239000012456 homogeneous solution Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 239000012046 mixed solvent Substances 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000007666 vacuum forming Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は回路基板の製造方法に係り、特に網状
化反応により硬化する樹脂を用いた回路基板の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a circuit board, and more particularly to a method for manufacturing a circuit board using a resin that is cured by a reticulation reaction.
従来、樹脂を基材とした回路基板で実用化され
ているものでは、紙−フエノール基板、ガラスマ
ツト・ポリエステル基板、ガラス・エポキシ基板
等の熱硬化性樹脂を主体としたものが知られてい
る。そしてこの種の回路基板では従来、銅張の熱
硬化性樹脂板を用い、レジストを印刷しエツチン
グにより下要の銅を溶解・除去することにより回
路パターンを形成していた。
Conventionally, circuit boards based on resins that have been put to practical use include those based mainly on thermosetting resins, such as paper-phenol boards, glass matte polyester boards, and glass-epoxy boards. Conventionally, in this type of circuit board, a circuit pattern is formed by using a copper-clad thermosetting resin plate, printing a resist, and dissolving and removing the underlying copper by etching.
このように従来上記の如き熱硬化性樹脂を主体
としたものが一般的であつた主な理由は、熱可塑
性樹脂は、熱に弱いことである。すなわち、一般
的には回路基板は、部品との接続において半田付
けを必要とし、通常用いられるSnとPbの共晶組
成の半田では、220℃〜260℃に耐えることが要求
される。これに対して熱可塑性樹脂は、上述の温
度に耐えることができないためである。 The main reason why thermosetting resins such as those mentioned above have been common in the past is that thermoplastic resins are sensitive to heat. That is, circuit boards generally require soldering for connection with components, and commonly used solder with a eutectic composition of Sn and Pb is required to withstand temperatures of 220°C to 260°C. This is because thermoplastic resins, on the other hand, cannot withstand the above-mentioned temperatures.
一方、回路の実装密度を高めるため回路パター
ンの多層化が行なわれている。この場合、従来各
層間の回路パターンを接続するにあたり、無電解
メツキを応用した銅スルホールが多用されてい
る。すなわち、銅帳積層板をエツチングしたもの
とプリプレグとを交互に重ね合せ熱圧着後、穿孔
して得られた孔壁に無電解メツキを施し、表裏面
を所望パターンにエツチングして多層化するとい
う工程により各層間の回路パターンを接続するも
のである。しかし、この方法は工程が複雑である
ため、回路基板が高価となる欠点がある。 On the other hand, in order to increase the packaging density of circuits, circuit patterns are being multilayered. In this case, conventionally, copper through-holes using electroless plating have been frequently used to connect circuit patterns between layers. That is, etched copper foil laminates and prepreg are alternately layered and bonded under heat, then electroless plating is applied to the hole walls obtained by drilling, and the front and back surfaces are etched in a desired pattern to create a multilayer structure. This process connects the circuit patterns between each layer. However, this method has the disadvantage that the process is complicated and the circuit board is expensive.
多層回路基板の他の例としては、絶縁基板上に
導体ペーストを印刷・焼成し、次いで絶縁体ペー
ストを印刷・焼成するという工程を繰り返して多
層化する厚膜回路基板がある。この方式はスルー
ホール加工、つまり孔壁への導体被着という工程
が不要であるため工程的には簡単であるが、印刷
の繰り返しにより多層化するほど段差が蓄積さ
れ、4層以上の多層になると実際上印刷が困難と
なるという問題があつた。 Another example of a multilayer circuit board is a thick film circuit board that is made into multiple layers by repeating the process of printing and firing a conductive paste on an insulating substrate, and then printing and firing an insulating paste. This method is simple because it does not require through-hole processing, that is, the process of attaching a conductor to the hole wall. Then, there was a problem that printing became difficult in practice.
さらに、上述した多層回路基板はいずれも絶縁
性基板面と回路パターン面とが同一平面上にな
く、回路パターン面が基板面より数十μm程度突
出することが多い。従つて、回路基板と摺動を要
する部品、例えばコネクタとの結合動作あるいは
スイツチや可変抵抗器の接点の摺動において動作
が不安定となり易く、機械的摩耗や電気アークの
発生を伴うという問題があつた。 Furthermore, in any of the above multilayer circuit boards, the insulating substrate surface and the circuit pattern surface are not on the same plane, and the circuit pattern surface often protrudes from the substrate surface by several tens of micrometers. Therefore, there is a problem in that the operation of parts that require sliding on the circuit board, such as the coupling operation with connectors or the sliding of contacts of switches and variable resistors, tends to become unstable, which is accompanied by mechanical wear and the generation of electric arcs. It was hot.
本発明は、上記欠点に鑑みなされたもので、そ
の目的とするところは網状化反応によつて硬化す
る樹脂を用いることによつて簡単な製造工程によ
り得られる層数の制約のない回路基板の製造方法
を提供することにあり、更に詳しくは回路パター
ンが絶縁性基板の表面に突出しない回路基板の製
造方法を提供することにある。
The present invention was made in view of the above-mentioned drawbacks, and its purpose is to create a circuit board with no restrictions on the number of layers, which can be obtained through a simple manufacturing process by using a resin that hardens through a reticulation reaction. The object of the present invention is to provide a manufacturing method, and more specifically, to provide a method for manufacturing a circuit board in which a circuit pattern does not protrude from the surface of an insulating substrate.
他の目的は、網状化反応によつて硬化する樹脂
を用いることによつて簡単な製造工程で多層化が
容易に行なえ、また立体化配線が可能な回路基板
の製造方法を提供することにある。 Another object is to provide a method for manufacturing a circuit board that can be easily multilayered through a simple manufacturing process by using a resin that hardens through a reticulation reaction, and that also enables three-dimensional wiring. .
更に他の目的は、半田付けを必要とせずに部品
との接続が可能な回路基板の製造方法を提供する
ことにある。 Still another object is to provide a method for manufacturing a circuit board that can be connected to components without the need for soldering.
本発明は、Bステージ状態にある網状化反応を
おこして硬化する樹脂によつて第1の絶縁性部材
である基材を形成し、この基材上に同じくBステ
ージ状態の硬化性樹脂をバインダーとする導電性
樹脂組成物によつて回路パターンを形成し、この
回路パターン上にBステージもしくはCステージ
状態の第2の絶縁性部材を形成し、これら第1及
び第2の絶縁性部材を互いに熱圧着することによ
つてBステージ状態の硬化性樹脂を塑性変形さ
せ、回路パターンの一部を第2の絶縁性部材に設
けられた穿孔部もしくは切欠部を介して第2の絶
縁性部材の表面まで盛り上げるようにしたことを
特徴とする回路基板の製造方法である。
In the present invention, a base material, which is a first insulating member, is formed from a resin that is in a B-stage state and cures by causing a reticulation reaction, and a curable resin that is also in a B-stage state is placed on this base material as a binder. A circuit pattern is formed using a conductive resin composition, a second insulating member in a B-stage or C-stage state is formed on the circuit pattern, and the first and second insulating members are connected to each other. By thermocompression bonding, the curable resin in the B stage state is plastically deformed, and a part of the circuit pattern is inserted into the second insulating member through the perforation or notch provided in the second insulating member. This is a method of manufacturing a circuit board, characterized in that the circuit board is raised up to the surface.
本発明によれば、Bステージ状態の硬化性樹脂
で絶縁性部材を形成し、また同ステージ状態にあ
る硬化性樹脂をバインダーとする導電性樹脂組成
物で回路パターンを形成し、所定の部分に穿孔部
もしくは切欠部を有する絶縁性フイルムで回路パ
ターンを覆い、これらを熱圧着するようにしてい
るので、熱圧着によつてBステージ状態の硬化性
樹脂からなる基材とBステージ状態のバインダー
を含む回路パターンとは共に塑性変形し、回路パ
ターンの一部が上記穿孔部もしくは切欠部を介し
て断線することなく絶縁性フイルム表面まで盛り
上る。従つて孔壁に無電解メツキ等を施すことな
くスルーホールを形成することができ、また多層
にした場合の基板表面での回路パターンの突出も
ない。さらに他の電気部品との接続も半田付け工
程を用いることなく行なうことが可能となる。こ
のように本発明によれば、多層化が極めて容易で
かつ安価な回路基板の製造方法を提供することが
できる。
According to the present invention, an insulating member is formed with a curable resin in a B-stage state, a circuit pattern is formed with a conductive resin composition using a curable resin in the same stage as a binder, and a circuit pattern is formed in a predetermined portion. The circuit pattern is covered with an insulating film having perforations or notches, and these are bonded together by thermocompression, so that the base material made of the curable resin in the B-stage state and the binder in the B-stage state are bonded together by thermocompression bonding. The included circuit pattern is plastically deformed, and a part of the circuit pattern rises to the surface of the insulating film through the perforation or notch without being disconnected. Therefore, a through hole can be formed without electroless plating or the like on the hole wall, and there is no protrusion of the circuit pattern on the surface of the substrate when the substrate is multilayered. Furthermore, connections with other electrical components can be made without using a soldering process. As described above, according to the present invention, it is possible to provide a method of manufacturing a circuit board that can be extremely easily multilayered and is inexpensive.
以下、本発明の一実施例について第1図a〜d
を参照して説明する。
Hereinafter, one embodiment of the present invention will be explained in Figures 1a to d.
Explain with reference to.
本発明においては、網状化反応を起して硬化す
る樹脂が使用される。この樹脂は、常温ではBス
テージと呼ばれる半固体状で、熱を加えることに
よつて可塑性を呈するが、成形後は更に熱或いは
放射線を加えることにより、網状化反応を起して
硬化するものである。 In the present invention, a resin that is cured by causing a reticulation reaction is used. This resin is in a semi-solid state called B stage at room temperature and exhibits plasticity when heated, but after molding, further heat or radiation causes a reticulation reaction and hardens. be.
第1図aにおいて1はBステージの熱硬化性樹
脂からなる基材でこの基材1の一方の面上に第1
図bに示すように後で詳しく述べる方法により回
路パターン2が形成される。回路パターン2は基
材1と同種または異種のBステージの熱硬化性樹
脂をバインダとし、金属粉または半導電性粉を混
入させた導電性樹脂組成物で形成されている。 In FIG. 1a, 1 is a base material made of a B-stage thermosetting resin, and a first
As shown in FIG. b, a circuit pattern 2 is formed by a method described in detail later. The circuit pattern 2 is formed of a conductive resin composition using a B-stage thermosetting resin of the same type or different type as the base material 1 as a binder and mixed with metal powder or semiconductive powder.
ここで、基材1および回路パターン2に用いら
れる回路基板材料としては熱硬化樹脂に限定され
るものではなく紫外線等の放射線を照射して網状
化反応を起して硬化するものであつてもよい。実
用可能な電気絶縁性、耐湿性、耐熱性を兼ね備え
た熱硬化樹脂として例えばエポキシ樹脂、不飽和
ポリエステル樹脂、1,2ポリブタジエン樹脂、
熱硬化型アクリル樹脂、ポリウレタン樹脂、ノボ
ラツク型フエノール樹脂、ポリイミド樹脂、キユ
メンバーオキサイド等の過酸化物を含むスチレン
ージビニルベンゼン共重合体、過酸化物を含むポ
リエチレン系樹脂等が使用され、また放射線硬化
樹脂として例えばポリエチレン系樹脂が使用され
る。また、導電性樹脂組成物に使用する金属粉と
しては、金、銀、銅、ニツケル、タングステン、
モリブデン、白金、アルミニウム、錫およびこれ
らを主体とする合金あるいは複合粉等が挙げら
れ、半導電性粉としてはカーボン粉、炭化珪素
物、五酸化バナジウム粉等あるいはこれらの混合
粉が挙げられる。基材1と回路パターン2に使用
される熱硬化性樹脂は同種であることが最も望ま
しいが、必ずしも同種でなくともよく、上記に挙
げたプレポリマーとほぼ同等の性質を有するもの
であれば、異種の組合わせでもよい。導電性樹脂
組成物を所望パターンに形成する方法としては、
印刷による方法が好ましく、その例として導電性
組成物を溶剤に溶かしてペースト化し、スクリー
ン印刷、オフセツト印刷、インクジエツト方式に
よる印刷等の、所要の図形になるように移動させ
ながら描画を行なうデスペンサー方式、あるいは
導電性樹脂組成物を粉体状にして静電印刷する方
式、さらに導電性組成物に感熱性を付与せしめ選
択的に加熱してパターン化する方式等がある。 Here, the circuit board material used for the base material 1 and the circuit pattern 2 is not limited to thermosetting resins, but may also be materials that are cured by irradiating radiation such as ultraviolet rays to cause a reticulation reaction. good. Examples of thermosetting resins that have practical electrical insulation, moisture resistance, and heat resistance include epoxy resins, unsaturated polyester resins, 1,2 polybutadiene resins,
Thermosetting acrylic resins, polyurethane resins, novolac type phenolic resins, polyimide resins, styrene-divinylbenzene copolymers containing peroxides such as cube member oxide, polyethylene resins containing peroxides, etc. are used. For example, polyethylene resin is used as the cured resin. In addition, metal powders used in the conductive resin composition include gold, silver, copper, nickel, tungsten,
Examples of the semiconductive powder include molybdenum, platinum, aluminum, tin, and alloys or composite powders mainly composed of these. Examples of the semiconductive powder include carbon powder, silicon carbide, vanadium pentoxide powder, and mixed powders thereof. It is most desirable that the thermosetting resins used for the base material 1 and the circuit pattern 2 are of the same type, but they do not necessarily have to be of the same type, and as long as they have properties almost equivalent to the above-mentioned prepolymers, A combination of different types may also be used. As a method for forming a conductive resin composition into a desired pattern,
Preferred is a printing method, such as a dispenser method in which the conductive composition is dissolved in a solvent to form a paste and drawn while being moved to form the desired shape, such as screen printing, offset printing, or inkjet printing. Alternatively, there is a method in which a conductive resin composition is made into powder and electrostatically printed, and a method in which the conductive composition is imparted with heat sensitivity and selectively heated to form a pattern.
次に、第1図cに示すように回路パターン2の
上面をBステージの絶縁性フイルム3によつて覆
う。この絶縁性フイルム3はやはり熱もしくは放
射線によつて網状化反応を起こす硬化性樹脂から
あるものであり、基材1と同種であることが好ま
しいが、必ずしも同種である必要はなく、接着性
において組合せが悪い場合は接着剤層を形成した
絶縁性フイルムであつてもよい。また、この絶縁
フイルム3は予めシート状に形成しておき単に回
路パターン2上に静置してもよいし、印刷、プレ
ス、ラミネートなどにより形成してもよい。この
絶縁性シート3には、前記回路パターン2の特定
部分に対応する領域に穿孔4または切欠部5が形
成されている。 Next, as shown in FIG. 1c, the upper surface of the circuit pattern 2 is covered with a B-stage insulating film 3. This insulating film 3 is also made of a curable resin that causes a reticulation reaction when exposed to heat or radiation, and is preferably of the same type as the base material 1, but does not necessarily have to be of the same type, and may have adhesive properties. If the combination is unsuitable, an insulating film with an adhesive layer may be used. Further, the insulating film 3 may be formed in advance into a sheet shape and simply placed on the circuit pattern 2, or may be formed by printing, pressing, laminating, etc. This insulating sheet 3 has perforations 4 or cutouts 5 formed in areas corresponding to specific portions of the circuit pattern 2.
そして、第1図cの状態で基材1と絶縁性フイ
ルム3とを所望の温度と圧力で熱圧着することに
より、基材1、回路パターン2及び絶縁性フイル
ム3は塑性変形し、第1図dに示すように回路パ
ターン2の表面が絶縁性フイルム3の穿孔4また
は切欠部5を介して絶縁性フイルム3と同一平面
上に露出する。次いでさらに温度を上昇させもし
くは放射線を照射して網状化反応をおこなわせし
めることにより前記基材、回路パターン及び絶縁
性フイルムを硬化させ、回路板6が得られる。 Then, by thermocompression bonding the base material 1 and the insulating film 3 at a desired temperature and pressure in the state shown in FIG. As shown in FIG. d, the surface of the circuit pattern 2 is exposed on the same plane as the insulating film 3 through the perforations 4 or cutouts 5 in the insulating film 3. Next, the base material, circuit pattern, and insulating film are cured by further raising the temperature or irradiating with radiation to cause a reticulation reaction, thereby obtaining the circuit board 6.
尚、絶縁性フイルム3はCステージの熱硬化性
樹脂を用いてもよい。この場合は、上記熱圧着に
よつて基材1及び回路パターン2が塑性変形し、
回路パターン2の表面がCステージの絶縁性フイ
ルム3の穿孔又は切欠部を介して絶縁性フイルム
3と同一表面に露出する。 Note that the insulating film 3 may be made of C-stage thermosetting resin. In this case, the base material 1 and the circuit pattern 2 are plastically deformed by the thermocompression bonding,
The surface of the circuit pattern 2 is exposed on the same surface as the insulating film 3 through the perforation or notch of the C-stage insulating film 3.
第1図dに示す回路板6の断面領域(導電性露
出面)7および8を拡大した様子を第2図に示
す。すなわち第2図において、断面領域10の扇
形部分は第1図の絶縁性フイルム3に対応し、断
面領域11の台形部分は第1図の基材1と回路パ
ターン2に対応している。本図から明らかなよう
に断面領域10および11の境界領域12では回
路パターン2がなめらかな曲線を描いており、し
かも、ほぼ平滑な露出面(図の左上部)に連続し
て一体化形成されていることが判る。 FIG. 2 shows an enlarged view of the cross-sectional areas (conductive exposed surfaces) 7 and 8 of the circuit board 6 shown in FIG. 1d. That is, in FIG. 2, the fan-shaped portion of the cross-sectional area 10 corresponds to the insulating film 3 of FIG. 1, and the trapezoidal portion of the cross-sectional area 11 corresponds to the base material 1 and the circuit pattern 2 of FIG. As is clear from this figure, the circuit pattern 2 draws a smooth curve in the boundary area 12 between the cross-sectional areas 10 and 11, and is formed continuously and integrally on the almost smooth exposed surface (upper left of the figure). It can be seen that
以上説明したことから明らかなように、本発明
によれば、第1図dおよび第2図に示すごとく、
基材1、回路パターン2および絶縁性フイルム3
を網状化反応によつて硬化する樹脂を用いて一体
成形することにより、回路パターンと絶縁材との
境界領域で回路パターン2が断線することなく、
絶縁性フイルムと同一平面上まで盛り上つて電気
的接続を確保することができる。従つて第1図c
に相当するものを予め複数個用意しておき、それ
らを熱圧着することにより回路パターンを相互に
接続することができ、かつ平滑な面を保持するこ
とができる。 As is clear from the above explanation, according to the present invention, as shown in FIG. 1d and FIG.
Base material 1, circuit pattern 2 and insulating film 3
By integrally molding the circuit pattern 2 using a resin that hardens through a reticulation reaction, the circuit pattern 2 will not be disconnected at the boundary area between the circuit pattern and the insulating material.
It can be raised to the same plane as the insulating film to ensure electrical connection. Therefore, Figure 1c
By preparing a plurality of pieces corresponding to the above in advance and bonding them by thermocompression, the circuit patterns can be connected to each other and a smooth surface can be maintained.
このように本発明を多層回路基板に適用した実
施例を第3図を参照して説明する。 An embodiment in which the present invention is applied to a multilayer circuit board as described above will be described with reference to FIG.
まず、第3図aに示すように、第1図bで説明
した工程により得られた回路基板30,31,3
2を用意する。第1層目の回路基板30には、下
面側に回路パターン301,303が形成され、
右端側に穿孔302が形成されている。第2層目
の回路基板31には上下両面に回路パターン31
1,314および312,315が形成され、左
端側に穿孔313が形成されている。さらに第3
層目の回路基板32には上面側に回路パターン3
21,323,324,325が形成され、右端
側に穿孔322が形成されている。また、この例
では多層回路基板に付髄する個別部品として例え
ば第1層目と第2層目の回路基板30,31の回
路パターン303と314との間に抵抗33が介
在され、回路基板31,32の間にダイオード3
4が介在される。 First, as shown in FIG. 3a, circuit boards 30, 31, 3 obtained by the process explained in FIG.
Prepare 2. Circuit patterns 301 and 303 are formed on the lower surface side of the first layer circuit board 30,
A perforation 302 is formed on the right end side. The second layer circuit board 31 has circuit patterns 31 on both upper and lower surfaces.
1,314 and 312,315 are formed, and a perforation 313 is formed on the left end side. Furthermore, the third
The circuit board 32 of the layer has a circuit pattern 3 on the top side.
21, 323, 324, and 325 are formed, and a perforation 322 is formed on the right end side. Further, in this example, a resistor 33 is interposed between the circuit patterns 303 and 314 of the first and second layer circuit boards 30 and 31 as an individual component attached to the multilayer circuit board. , 32 between diode 3
4 is interposed.
この状態で3枚の回路基板30,31,32を
熱圧着により一体化すると、第3図bに示すよう
になる。すなわち、第2層目の回路基板31上の
回路パターン311および312は、穿孔302
および322をそれぞれ通して基板30および3
2の上面および下面と同一平面上に盛り上つて露
出する。また、回路パターン301および321
は回路基板31に設けられた穿孔313を通して
互いの方向に盛り上つてこの穿孔313内で接触
し、導通状態となる。また抵抗33の上電極33
1は回路パターン303に、そして下電極332
は回路パターン314に接続される。このとき、
抵抗33は第3図bに示すように回路基板30と
31に埋設されるような形態になる。一方、ダイ
オード34の左電極341は回路基板32の回路
パターン323と、また右電極342は回路パタ
ーン324とそれぞれ接続される。このとき、ダ
イオード34は抵抗33と同様に回路基板31と
32に埋設された形となる。そして、回路パター
ン315と325は上下に相対応する位置にある
ので、熱圧着時に一体化される。次いでこの塑性
変形後加熱もしくは放射線照射により硬化反応を
行わせしめる。 In this state, when the three circuit boards 30, 31, and 32 are integrated by thermocompression bonding, the result is as shown in FIG. 3b. That is, the circuit patterns 311 and 312 on the second layer circuit board 31 are
and 322 through substrates 30 and 3, respectively.
It is raised and exposed on the same plane as the upper and lower surfaces of 2. In addition, circuit patterns 301 and 321
are raised toward each other through a hole 313 provided in the circuit board 31 and come into contact within the hole 313 of the lever, resulting in a conductive state. Also, the upper electrode 33 of the resistor 33
1 is attached to the circuit pattern 303 and the lower electrode 332
is connected to the circuit pattern 314. At this time,
The resistor 33 is embedded in the circuit boards 30 and 31 as shown in FIG. 3b. On the other hand, the left electrode 341 of the diode 34 is connected to the circuit pattern 323 of the circuit board 32, and the right electrode 342 is connected to the circuit pattern 324, respectively. At this time, the diode 34 is embedded in the circuit boards 31 and 32 similarly to the resistor 33. Since the circuit patterns 315 and 325 are located in vertically corresponding positions, they are integrated during thermocompression bonding. Next, after this plastic deformation, a hardening reaction is caused by heating or radiation irradiation.
このように3枚の回路基板30,31,32を
一体化することによつて、回路基板3枚分の厚さ
とほぼ同等あるいはそれ以下の厚みで一体化され
た3層構造の回路基板が形成される。 By integrating the three circuit boards 30, 31, and 32 in this way, a three-layer circuit board is formed with a thickness that is approximately equal to or less than that of three circuit boards. be done.
このように本発明によれば回路パターンが熱圧
着時、断線を生じることなく塑性変形できるた
め、多層にした場合でも基板表面に回路パターン
が突出することがない。また半田付け工程を用い
ることなく他の電気部品を回路パターンに接続す
ることができる。 As described above, according to the present invention, the circuit pattern can be plastically deformed during thermocompression bonding without causing wire breakage, so that the circuit pattern does not protrude from the surface of the substrate even when multilayered. Further, other electrical components can be connected to the circuit pattern without using a soldering process.
尚、層数が増えて一回の工程で熱圧着ができな
い場合は、上或いは下の回路基板から順に位置合
せして圧着していくようにすればよい。 If the number of layers increases and thermocompression bonding cannot be performed in one step, the circuit boards may be aligned and pressure bonded in order starting from the upper or lower circuit board.
更にまた本発明によれば、回路基板の回路パタ
ーンが熱圧着時、断線を生じることなく塑性変形
が可能であるため、回路基板の立体化が可能にな
る。すなわち、Bステージの絶縁性フイルムを用
いて第4図aに示すような回路基板40を第1図
で説明した方法でつくる。図において、41は回
路パターンである。この回路基板40を加温状態
にして、塑性変形し得る状態にしてから、押し出
し或いは真空成形または冷間加工法等によつて、
第4図bに示すように所定形状に配線を立体化す
ることが可能になる。この立体配置は、一面側を
絶縁層、他面側を回路層とすれば、電子機器の筐
体として利用可能になり、実用的価値が極めて大
なる効果がある。 Furthermore, according to the present invention, the circuit pattern of the circuit board can be plastically deformed without causing disconnection during thermocompression bonding, so that the circuit board can be made three-dimensional. That is, a circuit board 40 as shown in FIG. 4a is made using a B-stage insulating film by the method explained in FIG. 1. In the figure, 41 is a circuit pattern. This circuit board 40 is heated to a state where it can be plastically deformed, and then extruded, vacuum formed, cold worked, etc.
As shown in FIG. 4b, it becomes possible to three-dimensionalize the wiring in a predetermined shape. If this three-dimensional arrangement has an insulating layer on one side and a circuit layer on the other side, it can be used as a casing for an electronic device, and has extremely great practical value.
以上説明した本発明の実施例をさらに具体的に
説明する。 The embodiments of the present invention described above will be described in more detail.
具体例 1
第1図の製造工程において、5%のジシアンジ
アミドを含む平均分子量2500のビスフエノールA
型のBステージ状態のエポキシ樹脂からなる3mm
厚の基材1に、これと同じBステージエポキシ樹
脂からなるプレポリマー100重量部に対してシク
ロヘキサノンとnブチルカルビトールを1対1に
配合した混合溶剤330重量部を加温下で均一溶液
となし、さらにこの溶液に850重量部の平均粒径
5μの銀粉を添加し、ペイントロールで混練して
導電性樹脂組成物を得た。これを前記基材1にス
クリーン印刷法により第1図bのように印刷した
後、常温・減圧下で1時間乾燥を行ない、回路パ
ターン2を形成した。次いで、0.1mm厚の前述と
同様のプレポリマよりなる絶縁性フイルム3の所
定個所に3mmφの孔をあけ、この絶縁性フイルム
3により基材1上に印刷された回路パターン2を
第1図cに示すごとく覆つて熱圧着を行なつた。
熱圧着の条件は80℃,5Kg/cm2(樹脂圧)で時間
は30分とした。次いで、これを網状化しCステー
ジに移行させるために同じ圧力で100℃,30分、
120℃,20分、150℃,1時間網状化反応を行なわ
しめた。この結果、第1図dに示したように絶縁
性フイルム3と回路パターン2の表面とが同一平
面上にある回路基板が得られた。また回路パター
ン2の露出部と内層部分の接続を測定したところ
接続は完全になされていた。また第5図に示すよ
うにフイルム状の絶縁性基板に2mmφの孔51を
あけ、これを10mmピツチで50個連続させ、これら
の孔51に端部が一部重なるように基板の表裏面
に1mm幅の回路パターン(導体路)52を交互に
印刷して熱圧着を行つたところ、表裏面の導体路
は各々基板に埋めこまれ、かつ表裏面の導体路が
孔51内で接続され、一端から他端まで連続した
導体路が形成された。そしてその抵抗値も25Ωと
十分に低かつた。また、この回路基板を変形・屈
曲させても抵抗値の変化はほとんど認められなか
つた。Specific example 1 In the manufacturing process shown in Figure 1, bisphenol A with an average molecular weight of 2500 containing 5% dicyandiamide
3mm made of epoxy resin in the B stage state of the mold
100 parts by weight of a prepolymer made of the same B-stage epoxy resin and 330 parts by weight of a mixed solvent containing cyclohexanone and n-butyl carbitol in a 1:1 ratio were added to a thick base material 1 under heating to form a homogeneous solution. None, plus 850 parts by weight of average particle size in this solution
Silver powder of 5μ was added and kneaded with a paint roll to obtain a conductive resin composition. This was printed on the base material 1 by screen printing as shown in FIG. 1b, and then dried at room temperature and under reduced pressure for 1 hour to form a circuit pattern 2. Next, holes of 3 mm diameter were made at predetermined locations in a 0.1 mm thick insulating film 3 made of the same prepolymer as described above, and a circuit pattern 2 printed on the base material 1 using this insulating film 3 was formed as shown in Fig. 1c. It was covered and thermocompression bonded as shown.
The thermocompression bonding conditions were 80°C, 5Kg/cm 2 (resin pressure), and 30 minutes. Next, in order to reticulate this and move it to the C stage, it was heated at 100°C for 30 minutes at the same pressure.
The reticulation reaction was carried out at 120°C for 20 minutes and at 150°C for 1 hour. As a result, a circuit board was obtained in which the insulating film 3 and the surface of the circuit pattern 2 were on the same plane as shown in FIG. 1d. Furthermore, when the connection between the exposed portion of the circuit pattern 2 and the inner layer portion was measured, the connection was found to be perfect. In addition, as shown in Fig. 5, holes 51 of 2 mmφ are drilled in a film-like insulating substrate, and 50 holes are made in a row at a pitch of 10 mm. When circuit patterns (conductor paths) 52 with a width of 1 mm were alternately printed and thermocompression bonded, the conductor paths on the front and back surfaces were embedded in the substrate, and the conductor paths on the front and back surfaces were connected within the holes 51. A continuous conductor path was formed from one end to the other. The resistance value was also sufficiently low at 25Ω. Moreover, even when this circuit board was deformed and bent, almost no change in resistance value was observed.
具体例 2
第6図aに示すように、0.5%のキユメンパー
オキサイドおよび重量比で50%の平均粒径10μm
のフユーズドシリカを含むBステージ1,2ポリ
ブタジエン樹脂(日本曹達社製ポロブタジエンB
−4000)をプレスで成型して得た0.8mm厚の基材
61に2.4×1.2mmの孔62,63をあけ、次いで
ここに第6図bに示すように、2.4×1.2×0.8mmの
チツプ抵抗64と、3.0×1.8×0.8mmのチツプコン
デンサ65を圧入し、表面を略平担化した。な
お、66a,66b,67a,67bは端子であ
る。次いで、Bステージ1,2ポリブタジエン樹
脂(日本曹達社製、ポリブタジエン樹脂B−
2000)に2%のキユメンパーオキサイドと平均粒
径5μmの銀粒を80%加え、若干量のテトラリンを
添加して3本ロールにて導電性樹脂組成物を調製
し、この導電性樹脂組成物を印刷し、減圧・乾燥
して第6図cに示す如く回路パターン68を形成
した。次に、第6図dに示すように基材61と同
じ樹脂のプレポリマからなるプレポリマシートの
特定位置に孔70をあけた絶縁性フイルム69を
回路パターン68の上に積み重ね、さらに裏面に
絶縁フイルム71(0.1mm厚)を置いて、加熱お
よび加圧できる型内に収容し、常温で10Kg/cm2
(樹脂圧)を加えることによつて部品一体化回路
基板を得た。次いでこれを熱圧着することによ
り、第6図eに示すように絶縁性フイルム69と
同一平面上に回路パターン68の露出面73が形
成された。次いでこれを両面を型で押えながら
180℃に昇温させ網状化反応を行なわせしめた。
こうして得られた回路基板の接続をチエツクした
ところ、断線等はなく回路は正常に動作した。Concrete Example 2 As shown in Figure 6a, 0.5% Qyumen peroxide and 50% by weight average particle size 10 μm
B-stage 1,2 polybutadiene resin containing fused silica (Polybutadiene B manufactured by Nippon Soda Co., Ltd.)
2.4 x 1.2 mm holes 62, 63 are made in a 0.8 mm thick base material 61 obtained by molding a 0.8 mm thick material (-4000) with a press, and then 2.4 x 1.2 x 0.8 mm holes 62, 63 are made in this as shown in Fig. 6b. A chip resistor 64 and a chip capacitor 65 of 3.0 x 1.8 x 0.8 mm were press-fitted, and the surface was made approximately flat. Note that 66a, 66b, 67a, and 67b are terminals. Next, B stage 1,2 polybutadiene resin (manufactured by Nippon Soda Co., Ltd., polybutadiene resin B-
A conductive resin composition was prepared by adding 2% of Qyumen peroxide and 80% of silver grains with an average particle size of 5 μm to (2000) and adding a small amount of tetralin using a three-roll process. was printed and dried under reduced pressure to form a circuit pattern 68 as shown in FIG. 6c. Next, as shown in FIG. 6d, an insulating film 69 with holes 70 formed at specific positions of a prepolymer sheet made of the same resin as the base material 61 is stacked on top of the circuit pattern 68, and further insulated on the back side. A film 71 (0.1 mm thick) is placed in a mold that can be heated and pressurized, and it is heated to 10 kg/cm 2 at room temperature.
By applying (resin pressure), a component-integrated circuit board was obtained. Then, by thermocompression bonding, the exposed surface 73 of the circuit pattern 68 was formed on the same plane as the insulating film 69, as shown in FIG. 6e. Next, press this on both sides with a mold.
The temperature was raised to 180°C to carry out the reticulation reaction.
When the connections of the circuit board thus obtained were checked, there were no disconnections and the circuit operated normally.
具体例 3
第7図aに示すように、樹脂ポリマに重量比で
20%のガラス繊維を添加したプレポリマからなる
基材80,80′の所定個所に1mmφの孔81を
あけ、表裏面から導電性樹脂組成物よりなる回路
パターン82,83を印刷した。このとき孔81
内には導電性樹脂組成物が流れ込み、図示のよう
に表裏の回路パターンは接続された。その後これ
を常温で24時間放置して乾燥を行なつた。ここで
導電性樹脂組成物は、前記具体例2で使用したの
と同じものを用い、印刷はロール転写方式で行な
つた。Specific Example 3 As shown in Figure 7a, the weight ratio of
Holes 81 with a diameter of 1 mm were made at predetermined locations on substrates 80 and 80' made of prepolymer containing 20% glass fiber, and circuit patterns 82 and 83 made of a conductive resin composition were printed from the front and back sides. At this time, hole 81
A conductive resin composition flowed into the inside, and the circuit patterns on the front and back sides were connected as shown. Thereafter, this was left at room temperature for 24 hours to dry. The conductive resin composition used here was the same as that used in Specific Example 2, and printing was performed by a roll transfer method.
次いで、このように調製した異なる導体パター
ンを有する2枚の基材の間に、特定の部分に孔9
0,91を有する基材80と同一材質からなる
100μm厚の絶縁性フイルム85を介在させ、さら
に最外層に特定の部分に孔87〜89を有する
100μm厚の絶縁性フイルム84,86を配置し、
60℃,10Kg/cm2(樹脂圧)で加熱・加圧プレスを
行ない、さらに180℃,60Kg/cm2で30分間加熱・
加圧プレスを行なつて、冷却後、取出した。得ら
れた回路基板の断面は略第7図bに示したような
構造を有しており、上下回路の回路パターンの電
気的接続は良好に保たれていた。 Next, holes 9 are formed in specific parts between the two substrates having different conductor patterns prepared in this way.
Made of the same material as the base material 80 having a diameter of 0.91
An insulating film 85 with a thickness of 100 μm is interposed, and the outermost layer has holes 87 to 89 in specific parts.
Insulating films 84 and 86 with a thickness of 100 μm are arranged,
Heat and press at 60℃ and 10Kg/cm 2 (resin pressure), then heat and press at 180℃ and 60Kg/cm 2 for 30 minutes.
Pressure pressing was performed, and after cooling, it was taken out. The cross section of the obtained circuit board had a structure approximately as shown in FIG. 7b, and the electrical connection between the circuit patterns of the upper and lower circuits was maintained well.
具体例 4
0.5mm厚のBステージポリエチレン樹脂のシー
トを基材とし、一方、Bステージポリエチレン樹
脂10部、テトラリン80部、平均粒径5μmの銅粒80
部およびピロカロール0.2部からなる導電性樹脂
組成物を調製した。この場合、約60℃に加熱した
熱ロールで配合物を混練してペーストを調製し
た。次いで、この導電性樹脂組成物を加温したま
ま、約60℃に加温した前記基材上に所定パターン
にスクリーン印刷し、減圧下40〜5℃で乾燥し、
前記ポリエチレンフイルムを重ね合せ、130℃,
5〜10Kg/cm2(樹脂厚)になるようにして熱ロー
ルでラミネートした。この操作を2回繰り返し
た。Specific example 4 A sheet of B-stage polyethylene resin with a thickness of 0.5 mm is used as a base material, and on the other hand, 10 parts of B-stage polyethylene resin, 80 parts of tetralin, and 80 parts of copper grains with an average particle size of 5 μm are used as a base material.
A conductive resin composition was prepared containing 0.2 parts of pirocarol and 0.2 parts of pirocarol. In this case, the paste was prepared by kneading the formulation with hot rolls heated to about 60°C. Next, while this conductive resin composition was kept warm, it was screen printed in a predetermined pattern on the substrate heated to about 60°C, and dried at 40 to 5°C under reduced pressure.
Layer the polyethylene films together and heat at 130°C.
It was laminated with a hot roll to a thickness of 5 to 10 kg/cm 2 (resin thickness). This operation was repeated twice.
次いで、得られた回路基板シートを第4図bに
示したような雌型をもつ型を用い、シートを160
℃に予熱して真空成型を行つたところ、第4図b
に示したような立体回路基板が得られた。次い
で、これにβ線を主体とする放射線を照射して網
状化反応を行なわせしめた。得られた回路基板は
回路パターンの切断等もなく、回路基板として十
分に使用できることが確認された。 Next, the obtained circuit board sheet was molded using a mold having a female mold as shown in FIG.
After preheating to ℃ and performing vacuum forming, Fig. 4b
A three-dimensional circuit board as shown in is obtained. Next, this was irradiated with radiation mainly consisting of β rays to cause a reticulation reaction. It was confirmed that the obtained circuit board had no cutting of the circuit pattern, and could be fully used as a circuit board.
次に第8図および第9図を参照して、本発明の
変形例を説明する。すなわち第1図で説明した実
施例によれば、回路パターンが回路基板と同一平
面上に露出するごとく形成されている。この回路
パターンは、導電性材料にバインダーとして樹脂
を含んだ組成物で形成されているため、耐摩耗性
或いは他の端子との接続強度の点で弱い問題があ
る。それを補うための保護層の形成について述べ
たものである。 Next, a modification of the present invention will be described with reference to FIGS. 8 and 9. That is, according to the embodiment described in FIG. 1, the circuit pattern is formed so as to be exposed on the same plane as the circuit board. Since this circuit pattern is formed from a composition containing a conductive material and a resin as a binder, it has a problem in terms of wear resistance and connection strength with other terminals. This article describes the formation of a protective layer to compensate for this.
すなわち、第8図a乃至dの工程は、第1図a
乃至dまでの工程と同じである。次に回路パター
ン2の露出面7にCu或いはNiメツキを施した後、
(第8図eを参照)金或いは銀メツキ等の保護層
7aを施した後、再度熱圧着してこの保護層7a
を絶縁フイルム中に圧入した(第8図f)もので
ある。 That is, the steps a to d in FIG. 8 are similar to those in FIG.
The steps from step d to step d are the same. Next, after applying Cu or Ni plating to the exposed surface 7 of the circuit pattern 2,
(See Figure 8e) After applying a protective layer 7a such as gold or silver plating, this protective layer 7a is bonded again by thermocompression.
was press-fitted into an insulating film (Fig. 8f).
第9図は、絶縁性フイルム3の穿孔4に予め金
或いは銀の薄片7bを挿入して(第9図c参照)、
これを熱圧着することにより、第9図dに示すよ
うに金或いは銀の薄片を絶縁フイルムと同一平面
上に露出させ、電気的接続関係を保つて盛り上つ
た回路パターン2の保護層7bを形成した例であ
る。 In FIG. 9, a gold or silver thin piece 7b is inserted in advance into the perforation 4 of the insulating film 3 (see FIG. 9c).
By thermocompression bonding, the gold or silver thin piece is exposed on the same plane as the insulating film, as shown in FIG. This is an example of the formation.
以上説明したように本発明によれば、半田付け
工程或いはスルホール等の接続技術を使用するこ
となく、多層配線が可能になる。そのため近年厚
さ1mm以下の基体に集積回路を埋設し、所望の使
用形態に沿つて使用される外部からの入力を自己
の基本回路によつて処理した上で新たな信号を出
力するような薄型実装における例えば電卓、キヤ
シユカード或いはクレジツトカード等に幅広く適
用出来るという効果がある。 As described above, according to the present invention, multilayer wiring becomes possible without using a soldering process or connection technology such as through-holes. For this reason, in recent years, thin type devices have been developed that embed integrated circuits in substrates with a thickness of 1 mm or less, and process external inputs used in accordance with the desired usage pattern with their own basic circuits before outputting new signals. It has the advantage that it can be widely applied to, for example, calculators, cash cards, credit cards, etc.
本発明においては、要旨を変更しない範囲で
種々の応用、変形が考えられることは勿論いうま
でもない。 It goes without saying that various applications and modifications can be made to the present invention without departing from the gist thereof.
第1図は、本発明に係る回路基板の製造方法の
一実施例を説明するための工程図、第2図は、第
1図の製造工程により得られる本発明回路基板の
回路パターンと絶縁フイルムの境界領域の状態を
拡大して示す断面図、第3図乃至第7図は、本発
明の具体例を説明するための工程図および平面
図、第8図および第9図は、本発明の変形例を説
明するための製造工程図である。
1……回路基板、2,11……回路パターン、
3,10……絶縁フイルム、4……穿孔、7,8
……導電露出面。
FIG. 1 is a process diagram for explaining one embodiment of the method for manufacturing a circuit board according to the present invention, and FIG. 2 shows a circuit pattern and an insulating film of the circuit board of the present invention obtained by the manufacturing process shown in FIG. 3 to 7 are process diagrams and plan views for explaining specific examples of the present invention, and FIGS. 8 and 9 are cross-sectional views showing the state of the boundary area of It is a manufacturing process diagram for explaining a modification. 1...Circuit board, 2,11...Circuit pattern,
3, 10... Insulating film, 4... Perforation, 7, 8
...Conductive exposed surface.
Claims (1)
硬化する樹脂によつて第1の絶縁性部材を形成す
る工程と、Bステージ状態にある網状化反応をお
こして硬化する樹脂をバインダーとした導電性樹
脂組成物からなる回路パターンを前記第1の絶縁
性部材上に形成する工程と、Bステージもしくは
Cステージ状態にある網状化反応をおこして硬化
する樹脂からなり前記回路パターンの所定部に対
応する領域に穿孔部もしくは切欠部を有する第2
の絶縁性部材を少なくとも前記回路パターンを覆
うように形成する工程と、前記第1及び第2の絶
縁性部材と前記回路パターンとを互いに熱圧着し
て前記回路パターンの一部を前記穿孔部もしくは
切欠部を通して前記第2の絶縁性部材と略同一表
面になるまで盛り上げる工程と、前記絶縁性部材
と前記回路パターンとを硬化させる工程とを備え
たことを特徴とする回路基板の製造方法。 2 前記第1、第2の絶縁性部材及び前記回路パ
ターンを形成するために用いる樹脂は熱硬化樹脂
であることを特徴とする特許請求の範囲第1項記
載の回路基板の製造方法。 3 前記熱硬化樹脂は、エポキシ樹脂、不飽和ポ
リエステル樹脂、1,2ポリブタジエン樹脂、熱
硬化型アクリル樹脂、ポリウレタン樹脂、ノボラ
ツク型フエノール樹脂、ポリイミド樹脂、過酸化
物を含むスチレンージビニルベンゼン共重合体、
過酸化物を含むポリエチレン系樹脂から選ばれた
少なくとも1つであることを特徴とする特許請求
の範囲第2項記載の回路基板の製造方法。 4 前記第1、第2の絶縁性部材及び前記回路パ
ターンを形成するために用いる樹脂は放射線硬化
樹脂であることを特徴とする特許請求の範囲第1
項記載の回路基板の製造方法。 5 前記放射線硬化樹脂は、ポリエチレン系樹脂
であることを特徴とする特許請求の範囲第4項記
載の回路基板の製造方法。 6 前記回路パターンを形成する前記導電性樹脂
組成物は金属粉もしくは半導電性粉を含むことを
特徴とする特許請求の範囲第1項記載の回路基板
の製造方法。 7 前記金属粉は、金、銀、銅、ニツケル、タン
グステン、モリブデン、白金、アルミニウム、錫
から選ばれた少なくとも一種もしくはこれらのう
ちの二種以上の合金であることを特徴とする特許
請求の範囲第6項記載の回路基板の製造方法。 8 前記半導電性粉は、カーボン、炭化珪素、五
酸化パナジウムから選ばれた少なくとも一種であ
ることを特徴とする特許請求の範囲第6項記載の
回路基板の製造方法。 9 Bステージ状態にある網状化反応をおこして
硬化する樹脂によつて第1及び第2の絶縁性部材
を形成する工程と、Bステージ状態にある網状化
反応をおこして硬化する樹脂をバインダーとした
導電性樹脂組成物からなる回路パターンを前記第
1及び第2の絶縁性部材上に対向させて形成する
工程と、BステージもしくはCステージ状態にあ
る網状化反応をおこして硬化する樹脂からなり前
記第1及び第2の絶縁性部材上に対向して形成さ
れた前記回路パターンの所定部に対応する領域に
穿孔部を有する第3の絶縁性部材を前記第1の絶
縁性部材と前記第2の絶縁性部材との間に形成す
る工程と、前記第1乃至第3の絶縁性部材を熱圧
着することにより前記第1の絶縁性部材上に形成
された前記回路パターンと前記第2の絶縁性部材
上に形成された前記回路パターンとを前記第3の
絶縁性部材の穿孔部中で接続する工程と、その後
前記絶縁性部材と前記回路パターンとを硬化させ
る工程とを備えたことを特徴とする回路基板の製
造方法。 10 Bステージ状態にある網状化反応をおこし
て硬化する樹脂によつて第1及び第2の絶縁性部
材を形成する工程と、Bステージ状態にある網状
化反応をおこして硬化する樹脂をバインダーとし
た導電性樹脂組成物からなる回路パターンを前記
第1及び第2の絶縁性部材上に対向させて形成す
る工程と、BステージもしくはCステージ状態に
ある網状化反応をおこして硬化する樹脂からなり
前記回路パターンの所定部に対応する領域に穿孔
部を有する第3の絶縁性部材を形成する工程と、
Bステージ状態にある網状化反応をおこして硬化
する樹脂をバインダーとした導電性樹脂組成物か
らなる回路パターンを前記第3の絶縁性部材の少
なくとも一方の面上に形成する工程と、前記回路
パターンが形成された前記第3の絶縁性部材を前
記第1の絶縁性部材と前記第2の絶縁性部材との
間に介在させるとともに前記第3の絶縁性部材と
前記第1及び第2の絶縁性部材のうちの少なくと
も一方の部材との間に電気部品を介在させる工程
と、前記第1乃至第3の絶縁性部材を熱圧着する
ことにより前記第1の絶縁性部材上に形成された
前記回路パターンと前記第2の絶縁性部材上に形
成された前記回路パターンとを前記第3の絶縁性
部材の穿孔部中で接続するとともに前記第1及び
第2の絶縁性部材のうちの少なくとも一方の部材
上に形成された前記回路パターンと前記第3の絶
縁性部材上に形成された前記回路パターンとを前
記電気部品の電極に接続する工程と、その後前記
絶縁性部材と前記回路パターンとを硬化させる工
程とを備えたことを特徴とする回路基板の製造方
法。[Claims] 1. A step of forming a first insulating member using a resin that is in a B-stage state and cured by causing a reticulation reaction, and a resin that is in a B-stage state and cured by causing a reticulation reaction. a step of forming a circuit pattern made of a conductive resin composition using as a binder on the first insulating member; and a step of forming a circuit pattern made of a resin that is cured by causing a reticulation reaction in a B-stage or C-stage state. a second part having a perforation or notch in a region corresponding to a predetermined part of the second part;
forming an insulating member so as to cover at least the circuit pattern; and thermocompression bonding the first and second insulating members and the circuit pattern to each other so that a part of the circuit pattern is formed in the perforation or the circuit pattern. A method for manufacturing a circuit board, comprising the steps of: raising the surface through the notch until the surface is substantially flush with the second insulating member; and curing the insulating member and the circuit pattern. 2. The method of manufacturing a circuit board according to claim 1, wherein the resin used to form the first and second insulating members and the circuit pattern is a thermosetting resin. 3 The thermosetting resin is an epoxy resin, an unsaturated polyester resin, a 1,2 polybutadiene resin, a thermosetting acrylic resin, a polyurethane resin, a novolac type phenolic resin, a polyimide resin, a styrene-divinylbenzene copolymer containing a peroxide. ,
3. The method for manufacturing a circuit board according to claim 2, wherein the material is at least one selected from polyethylene resins containing peroxide. 4. Claim 1, wherein the resin used to form the first and second insulating members and the circuit pattern is a radiation-curable resin.
2. Method for manufacturing a circuit board as described in Section 3. 5. The method of manufacturing a circuit board according to claim 4, wherein the radiation-curable resin is a polyethylene resin. 6. The method of manufacturing a circuit board according to claim 1, wherein the conductive resin composition forming the circuit pattern contains metal powder or semiconductive powder. 7 Claims characterized in that the metal powder is at least one selected from gold, silver, copper, nickel, tungsten, molybdenum, platinum, aluminum, and tin, or an alloy of two or more of these. 7. The method for manufacturing a circuit board according to item 6. 8. The method of manufacturing a circuit board according to claim 6, wherein the semiconductive powder is at least one selected from carbon, silicon carbide, and panadium pentoxide. 9 A step of forming the first and second insulating members using a resin that is cured by causing a reticulation reaction in a B-stage state, and a step of forming the resin that is cured by causing a reticulation reaction in a B-stage state as a binder. a step of forming a circuit pattern made of a conductive resin composition facing each other on the first and second insulating members; A third insulating member having a perforation in a region corresponding to a predetermined portion of the circuit pattern formed oppositely on the first and second insulating members is connected to the first insulating member and the third insulating member. the circuit pattern formed on the first insulating member and the second insulating member by thermocompression bonding the first to third insulating members; The method further comprises the steps of: connecting the circuit pattern formed on the insulating member in a perforated portion of the third insulating member; and thereafter curing the insulating member and the circuit pattern. Characteristic circuit board manufacturing method. 10 A step of forming the first and second insulating members using a resin that is cured by causing a reticulation reaction in a B-stage state, and a step of forming the resin that is cured by causing a reticulation reaction in a B-stage state as a binder. a step of forming a circuit pattern made of a conductive resin composition facing each other on the first and second insulating members; forming a third insulating member having a perforation in a region corresponding to a predetermined portion of the circuit pattern;
forming on at least one surface of the third insulating member a circuit pattern made of a conductive resin composition whose binder is a resin that hardens by causing a reticulation reaction in a B-stage state; and the circuit pattern. is interposed between the first insulating member and the second insulating member, and the third insulating member and the first and second insulating members are interposed between the third insulating member and the first and second insulating members. a step of interposing an electrical component between the electrical component and at least one of the electrical members; Connecting a circuit pattern and the circuit pattern formed on the second insulating member in a perforation of the third insulating member, and at least one of the first and second insulating members. a step of connecting the circuit pattern formed on the member and the circuit pattern formed on the third insulating member to an electrode of the electrical component, and then connecting the insulating member and the circuit pattern. A method for manufacturing a circuit board, comprising the step of curing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59208011A JPS6187388A (en) | 1984-10-05 | 1984-10-05 | Manufacture of circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59208011A JPS6187388A (en) | 1984-10-05 | 1984-10-05 | Manufacture of circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6187388A JPS6187388A (en) | 1986-05-02 |
JPH0224035B2 true JPH0224035B2 (en) | 1990-05-28 |
Family
ID=16549190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59208011A Granted JPS6187388A (en) | 1984-10-05 | 1984-10-05 | Manufacture of circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6187388A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007088004A (en) * | 2005-09-20 | 2007-04-05 | Seiko Epson Corp | Multilayer circuit board, method of manufacturing the same, electro-optical device, and electronic device |
JP2007335653A (en) * | 2006-06-15 | 2007-12-27 | Alps Electric Co Ltd | Circuit board, method of manufacturing the same, and circuit module using the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
-
1984
- 1984-10-05 JP JP59208011A patent/JPS6187388A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159664A (en) * | 1978-06-07 | 1979-12-17 | Shin Kobe Electric Machinery | Method of producing printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS6187388A (en) | 1986-05-02 |
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