JPH0223595A - Method for writing in nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To make page-mode writing possible by applying a specific voltage across required transistors in accordance with the erasure and program modes. CONSTITUTION:When a selected word line 3 corresponding to a page to which the page mode is to be performed is set to a high voltage and 0V is supplied to a non-selected word line 4 and all bit lines 1 and 2 while source lines 5 and 6 are floated, a high voltage is applied across the control gates and drains of memory transistors (TR) Q1 and Q3, the control gates of which are connected with the word line 3, and a high electric field is generated between a floating gate and drain. As a result, electrons are injected from the drain toward the floating gate due to a tunnel effect and the threshold voltages of the TRs Q1 and Q3 rise. Accordingly, logic '1' is written and the selected TRs Q1 and Q3 are erased. Therefore, when a specific voltage which is opposite to the voltage applied at the time of erasure is applied across the control gates and drain areas of the TRs Q1 and Q3 and a low write inhibit voltage is applied across the gates and drain areas of other non-selected TRs Q2 and Q4, page- mode writing can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a writing method for an electrically writable nonvolatile semiconductor memory device.

[Conventional technology]

Figure 3 shows 19g7 IEEE! International Solid State Circuits Conference (Inte
rnationa! 5olid 5tate C1r
cuits Conference) Digest (
Figure 4 is an operation explanatory diagram showing the equivalent circuit of a memory cell in a conventional nonvolatile semiconductor device and the voltage values to be applied to each terminal during erasing and writing, as shown in pages 76 to 77. 2 is a cross-sectional structural diagram of a memory transistor used in the nonvolatile semiconductor device shown in FIG.
Both show memory transistors with floating gates. Each memory transistor Q
, ~Q8 are substantially the same, and as shown in FIG. Interposed control gate 25. A floating gate 26 is formed, a control gate electrode 26 is formed in the control gate 25, a drain electrode 28 is formed in the drain region 21, and a drain electrode 28 is formed in the source region 2.
2 are connected to source electrodes 29, respectively.

The control gate 25 is disposed between the drain region 21 and the source region 22, with one end facing above the drain region 22 and the other end located near the source region 22, and the floating gate 26 is disposed near the drain region 21 between the drain region 21 and the source region 22 with one end facing above the drain region 21, and the control gate 25
By applying a predetermined high voltage between the drain region 21 and the drain region 21, charges (electrons) are injected and accumulated from the drain region 21 to the floating gate 26 by a tunneling phenomenon, or charges (electrons) are transferred to the drain region 21 by a tunneling phenomenon. electrons) can be withdrawn.

Each of the transistors Q, ~Q8 configured in this way is
As shown in the figure (the gate electrodes of the transistors Qs, Q? arranged in a matrix and arranged in the row direction, the gate electrodes of the transistors Q, , Q, are connected to the word IIE?, respectively).
19, and the source electrodes of the transistors Q, , Q, and the source electrodes of the transistors Q6, Q, and l are connected to the source line 17, respectively, and the transistors QS, Q6, and transistors Q7, Q arranged in the column direction are connected to the source line 17, respectively. The drain electrodes marked * are connected to bit lines 15 and 16, respectively.

In the conventional writing method for such a non-volatile semiconductor device, first all memory cells, that is, memory transistor Q
, ~Q, is erased, in other words, electrons are injected into each floating gate and accumulated to create a logic "1" state, and then the selected memory cell is programmed, in other words, electrons are accumulated in the floating gate of the memory transistor. This is done by setting the current charge to a logic "0" state, which causes the charge to be discharged.

Next, a case in which writing is performed to the selected memory transistor Q7 will be specifically explained.

(Erase operation) As shown in FIG. 3, the erase operation is performed by first applying a high voltage V pH to all bit lines 15 and 16 and applying OV to all word lines 18 and 19.

As a result, a high electric field is generated between the floating gate 26 and the drain region 21 shown in FIG. 4, and the charges accumulated in the floating gate 21, that is, electrons, are drawn out to the drain region 21 by tunneling through the thin oxide film 24a. .

The floating gate 26 of each memory transistor Q, ~Q, is
The state becomes an electron depletion state, and the threshold voltages of the memory transistors Q, .about.Q, viewed from the control gate 25 side become lower than before the erase operation, and this state is called an erase state and is set to logic "1".

(Program operation) Which memory transistor Q should be written? A high voltage V pH is applied to the bit line connected to the drain region of the selected bit line 16, and Ov is applied to the unselected bit line 15.
Furthermore, a high voltage ■□2 is applied to the word line connected to the control gate of the memory transistor Q7, that is, the selected word line 18.
In addition, Ov is applied to the unselected word line 19, and the common source line 17 is
Give OV to each.

As a result, a high voltage V□2 is applied to both the control gate and the drain region of the memory transistor Q through the bit line 16 and the word line 18, respectively, and the drain region of the memory transistor Q as shown in FIG. High energy electrons near 21 (Hot Elec I/Ron)
occurs, and this causes the high voltage ■
, 22 and injected into the floating gate 26.

The floating gate 26 is surrounded by an oxide film, and electrons are in an accumulated state. When this state is viewed from the control gate 25 side, the dark value voltage of the memory transistor Q7 becomes higher than before the programming operation. This state is called a program state and is set to logic "0".

Such electrically erasable and programmable nonvolatile semiconductor memory devices (EεFROM) do not require the use of ultraviolet rays or the like for erasing unlike EFROM, and can be electrically erased while mounted on the board. Since the cell can be configured with one transistor, there are advantages such as reduction in chip area.

[Problem to be solved by the invention]

However, in the conventional method as described above, the erasing operation is performed for all memory cells at once.
There was a problem in that page-by-page rewriting was not possible.

The present invention has been made in view of the above circumstances, and its purpose is to provide a writing method for a nonvolatile semiconductor memory device that allows page-by-page rewriting, so-called page mode writing.

[Means to solve the problem]

A writing method for a nonvolatile semiconductor memory device according to the present invention includes:
When erasing, a predetermined voltage is applied between the control gate and drain of only the memory transistor whose control gate is connected to the selected signal line, and when programming, the HS gate is connected to the selected signal line. Is there a restriction on selected memory transistors among memory transistors? A predetermined voltage opposite to that during erasing is applied to the II+ gate and drain region, and a lower write blocking voltage is applied to the control gate and drain region of the other memory transistors.

[Effect]

This enables the present invention to perform page mode writing in which memory transistors connected to each word line are erased and programmed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 1 is an explanatory diagram showing an equivalent circuit of a memory cell in a nonvolatile semiconductor memory device used in the method of the present invention and voltage values for each terminal during erase 1 program operation, and FIG. 2 is a cross-sectional structural diagram of a memory transistor. , Q, -Q4 are memory transistors, 1.degree.2 is a bit line, 3 and 4 are word lines, and 5 and 6 are source lines.

The memory transistors Q and -Q4 are all substantially the same, and as shown in FIG. A control gate 15 and a floating gate 16 are provided through the layer 14, and a control gate electrode 17 is connected to the control gate 15, a drain electrode 18 is connected to the drain region 11, and a source electrode 19 is connected to the source region 12. It is.

IJ control gate 15 has drain region 11 and source region 1
2, with one end facing above the drain region 11 and the other end facing near the source region 12. Furthermore, the floating gate 16 is disposed closer to the drain region 11 side between the drain region 11 and the source region 12, with one end facing above the drain region 11. The floating gate 16 protrudes toward the drain region 11 side in a part of the portion facing the drain region 11.
A protruding portion is provided opposite to the thin oxide film 14a with a thin oxide film 14a interposed therebetween.

These memory transistors Q, ~Q4 are arranged in a matrix as shown in Fig. 1 (Fig. 1 shows the case where two each are provided in the row and column direction),
The memory transistors Q2, Qa, and Qa are arranged in the row direction, and the memory transistors Q, Q, and Q3Q are arranged in the column direction.

The gate electrodes of memory transistors QQ, arranged in the row direction, and the gate electrodes of memory transistors Q2. Q.

The gate electrodes are each word! 113.4, and the drain electrodes of the memory transistors Q+, Qz, memory transistors Qs, and Qa arranged in the column direction are connected to the bit line 1.2, respectively, and the memory transistors Ql l q
z, the source electrodes of memory transistors Q3 and Q4 are connected to source wires 5 and 6, respectively.

Writing to such a non-volatile semiconductor memory device involves an external write cycle in which data for one page is written into an internal latch, and an internal cycle in which data is actually written into memory cells according to the data written to the latch. This internal write cycle is further divided into an erase cycle and a program cycle. In the erase cycle, all memory cells for one page to be programmed are first erased, that is, logic "1" is written, and then in the program cycle, they are programmed according to the data in the latch, that is, logic "1" is written.
Write “O”.

The internal cycle of page mode writing will be specifically explained below.

(Erase operation) High voltage VFP is applied to the selected word line 3 corresponding to the page to be written in page mode, Ov is applied to the unselected word line 4, and OV is applied to all bit lines 1 and 2, and the source This is done by making the lines 5 and 6 floating.

Word by this! A high voltage is applied between the control gate and the drain region of the memory transistors Q, , Q, whose control gates are respectively connected to 113, a high electric field is generated between the floating gate and the drain region, and the electric field is directed from the drain region to the floating gate. Then, electrons are injected by tunneling through the thin oxide film 14 shown in FIG. 2, and the floating gate becomes in a state where electrons are accumulated.

In this state, as seen from the control gate, the memory transistor Q
,, the threshold voltage of Q3 becomes higher than before the erase operation, resulting in an erased state, that is, a state in which logic "1" is written.

Note that the memory transistor Q! whose control gate is connected to the word line 4! , Qa, word line 4, bit line 1
.

(Program operation) In the case of writing logic °O'' only to the transistor Q among the memory transistors Q, Q3 whose control gates are connected to the word vA3, first the selected word line 3 is written.
OV1 non-selected word! 5I4 to Vw+ (=2/3
VPP) is applied to the selected bit line 2, and a high voltage V is applied to the selected bit line 2.
PP, Vllll (=1/3 VP
P) is further performed by making the source line 5.6 floating.

As a result, a high voltage of 0 is applied to the control gate of the memory transistor Q3 and a high voltage of 1 is applied to the drain region, a high electric field is generated between the floating gate and the drain region, and a tunnel is created from the floating gate to the drain region through the thin oxide film 14a. This phenomenon causes electrons to be extracted, leaving the floating gate in an electron-depleted state.

In this state, when viewed from the control gate, the dark value voltage of the memory transistor Q3 becomes lower than before the programming operation, resulting in a programmed state, that is, a state in which logic "0" is written.

Other memory transistor Q! , Qa, the voltage VWI is applied to the gate electrode through the word line 4, and the bit '
Both voltages are applied to the drain region through 41A1.2
, ■7. On the other hand, in the memory transistor Q, OV is applied to the gate electrode through the word line 3, and Vlll is applied to the bit line 1.
In both cases, there is a voltage difference of 1 between the control gate and the drain region.
/3v□ remains applied.

Normally, the tunnel current between the control gate and the drain region in a memory transistor strongly depends on the strength of the electric field, and if the electric field decreases to I MV/mm4, the tunnel current density decreases by about one order of magnitude, so the above-mentioned voltage The difference is 1/3 V
pp memory transistors Q,,Q,.

Almost no tunnel current flows in Q4, and changes in the dark value voltage can be ignored, so that only the memory transistor Q is programmed.

〔Effect of the invention〕

As described above, the method of the present invention has an excellent effect in that page mode writing can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an equivalent circuit of a memory cell in a semiconductor memory device used in the method of the present invention and voltage values for each terminal during erase and program operations, and FIG. 2 is a cross-sectional structural diagram of a memory transistor used in the method of the present invention. , and FIG. 3 shows an equivalent circuit and erasure of a memory cell in a semiconductor memory device used in a conventional method. FIG. 4, which is an explanatory diagram showing voltage values for each terminal during a program operation, is a cross-sectional structural diagram of a memory transistor used in a conventional nonvolatile semiconductor memory device. Q, -Q4...Memory transistor 1.2...Bit line 3.4...Word line 5.6...
... Source line In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a writing method for a non-volatile semiconductor memory device in which a plurality of memory transistors each having a floating gate capable of electrically injecting and discharging charge are arranged in a matrix, the following steps are taken when erasing: A predetermined voltage is applied between the control gate and drain of only the memory transistors whose control gates are connected to the signal line, and when programming, the memory transistors selected from among the memory transistors whose control gates are connected to the selected signal line are A predetermined voltage opposite to that for erasing is applied to the control gate and drain region of the memory transistor, and a write blocking voltage lower than this is applied to the control gate and drain region of other memory transistors. A writing method for a non-volatile semiconductor memory device characterized by: