JPH05182481A - Semiconductor memory writing and erasing electrically - Google Patents

Abstract

PURPOSE:To reduce the distribution range of a threshold voltage and to prevent a malfunction due to an excess erasure memory cell by correcting the threshold value voltage to the memory cell having a prescribed threshold value voltage or below after the application of an erasing voltage. CONSTITUTION:Write is performed to the memory cell whose threshold value voltage is lower than a verifying voltage due to verifying operation after erasing. Then, though a voltage generated at a node 21 is transmitted on a signal line 49a, the voltage is a voltage which VPP/VCC is resistance-divided by a resistance value R11 and the resistance value R12+R13. A voltage Vew is generated to the signal line 49b and 46a by a comparator circuit 49 in accordance with the writing voltage Vew after erasure on the signal line 49a. Thus, the threshold value voltage change quantity of the memory cell is reduced since the low voltage Vew is applied to a selective word line from an X decoder. Thus, the distribution range of the threshold value voltage of the memory cell is narrowed and the memory cell of an excess erasure state is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically programmable erasable non-volatile semiconductor memory device (EEPROM), and more particularly to a flash EEPROM capable of simultaneously erasing a plurality of bytes of memory cells.

[0002]

2. Description of the Related Art EEPROMs are widely used in IC card storage devices and the like because they can electrically erase and rewrite stored information and retain the stored information even when the power is cut off. .. EEPROM
One of them is a flash EEPROM (hereinafter referred to as a flash memory) capable of simultaneously erasing a plurality of bytes of memory cells.

FIG. 21 is a diagram showing a cross-sectional structure of a general flash memory cell. In FIG. 21, a flash memory cell is a P ⁻ type semiconductor substrate 1 having a low impurity concentration.
Of N ⁺ type impurity regions 2 and 3 having a high impurity concentration and formed on the main surface thereof at a prescribed interval. Impurity regions 2 and 3 provide a drain region and a source region, respectively. The flash memory cell further includes an impurity region 2
About 100 A on the channel region 7 between the impurity region 3 and the impurity region 3.
Insulating film 4 with extremely thin film thickness of about (angstrom)
And a control gate 6 formed on the floating gate 5 with an interlayer insulating film 8 interposed therebetween. This flash memory cell has a two-layer gate structure including a floating gate 5 and a control gate 6. Floating gate 5 is electrically isolated from impurity regions 2 and 3 and control gate 6 via insulating films 4 and 8, respectively.

The flash memory cell stores information according to the amount of charge (electrons) accumulated in the floating gate 5.

In the state where many electrons are injected into floating gate 5, an inversion layer is hard to be formed in channel region 7, and therefore the threshold voltage of the memory cell becomes high. On the other hand, when electrons are emitted from the floating gate 5, an inversion layer is easily formed in the channel region 7, and the threshold voltage of this memory cell becomes low. Here, regarding the threshold voltage of the memory cell, a low resistance inversion layer is formed in the channel region 7 between the impurity region 2 and the impurity region 3, and a current flows between the impurity region 2 and the impurity region 3. The voltage applied to the control gate 6 which gives a flowing state is shown.

FIG. 22 is a diagram showing the correspondence between the voltage applied to the control gate 6 and the electron injection / emission state of the floating gate 5. As shown in FIG. 22,
The threshold voltage is high when electrons are injected into the floating gate 5, and the source-drain current Ids flows when the voltage applied to the control gate 6 becomes Vg0 or higher. This state is called a write state and is defined as a state in which data "0" is stored.

Since the threshold voltage is low when electrons are emitted from the floating gate 5, the source-drain current Ids flows (Vg1 <Vg when the voltage Vg applied to the control gate 6 becomes Vg1 or more).
0). This state is called an erased state and is defined as a state in which data "1" is stored. That is, in the flash memory cell, binary information of "1" and "0" is stored by utilizing the fact that the threshold voltage changes according to the amount of electrons accumulated (injection / emission) of the floating gate 5. .. The overerased state will be described later.

General data write and erase operations of the flash memory cell shown in FIG. 21 will now be described. When rewriting normal data, an erasing operation is performed first, and then data writing is performed.

At the time of data writing, a write voltage of about 6V is normally applied to impurity region 2 serving as a drain region, a high voltage of about 12V is usually applied to control gate 6, and impurity region 3 is grounded. It In this state, the high voltage of the control gate 6 is sufficiently higher than the threshold voltage Vg0, so that the inversion layer is formed in the channel region 7 and the source-drain current Ids flows. At this time, an avalanche breakdown phenomenon occurs in the impurity region 2 due to the high electric field, and electrons of the source-drain current are excited to become hot electrons. The hot electrons are accelerated toward the floating gate 5 and injected into the floating gate 5 by the high electric field applied between the control gate 6 and the drain impurity region 2. As a result, the threshold voltage of the flash memory cell rises and the write state is realized.

In the erase operation, a high voltage (about 12 V) is applied to the source impurity region 3, the control gate 6 is grounded, and the drain impurity region 2 is in a floating state. In this state, a high electric field is generated between the floating gate 5 and the source impurity region 3 through the thin gate insulating film 4, and the high electric field causes electrons from the floating gate 5 to become a tunnel current and become a source impurity region 3. To the erased state, the threshold voltage of the flash memory cell drops, and the erased state is realized.

The flash memory includes a memory cell array in which flash memory cells having the structure shown in FIG. 21 are arranged in a matrix. By storing desired data in the memory cells in this memory cell array, it functions as a memory device.

FIG. 23 is a diagram showing the entire structure of a general flash memory. In FIG. 23, the flash memory 100 includes a memory cell array 110 including a plurality of flash memory cells arranged in a matrix of rows and columns. In FIG. 23, in order to simplify the drawing, the memory cell array 110 includes four flash memory cells 16, 17, 18 and 1 arranged in 2 rows and 2 columns.
It is shown to include 9. In the memory cell array 110, word lines W (W0, W1) to which one row of memory cells are connected, and bit lines B (B0, B1) to which one column of flash memory cells are connected are arranged. To be done.

The flash memory 100 further receives an applied address signal (this may be applied from outside the chip or from an arithmetic processing unit formed on the same chip) and an internal address signal. Generating an address buffer 8, an X decoder 12 which decodes an internal row address signal from the address buffer 8 to select a corresponding word line, and an internal column address signal from the address buffer 8 to decode a memory cell array 110.
A Y decoder 9 for generating a column selection signal Y (Y1, Y0) for selecting the corresponding column, and a sense amplifier 15 for detecting and amplifying the stored data of the X decoder 12 and the memory cell selected by the Y decoder 9. , A write circuit 20 for writing information to a selected memory cell, and a data input / output buffer 21 for inputting / outputting data to / from the outside of the device.

Between sense amplifier 15 and write circuit 20 and bit line B of memory cell array 110, a corresponding bit line is connected to sense amplifier 15 or write circuit 20 in accordance with column selection signal Y from Y decoder 9. A column selection gate circuit 120 is provided. Column selection gate circuit 120
Y gate transistor 10 provided for bit line B0 and rendered conductive in response to column selection signal Y0, and Y provided for bit line B1 and rendered conductive in response to column selection signal Y1. It is shown to include a gate transistor 11.

Sense amplifier 15 applies a read voltage to a selected bit line during data reading, detects the presence / absence of a current flowing through this bit line, amplifies the information in the selected memory cell, and then outputs the data contained in data input / output buffer 21. The amplified signal is transmitted to the circuit. The data detected / amplified by the sense amplifier 15 is also applied to the write / erase control circuit 25 for a verify operation described later. Write circuit 20 applies a voltage corresponding to the write data to the selected bit line in accordance with the write data from the input buffer included in data input / output buffer 21.

The flash memory 100 further generates various internal control signals in response to external control signals, that is, the chip enable signal CE, the output enable signal OE and the write enable signal WE, and controls the write and erase operations. Write / erase control circuit 2
5, a high voltage Vpp and an operating power supply voltage Vc externally applied in response to a selection signal of the write / erase control circuit 25.
Vpp / Vcc switching circuit 22 for selecting either c
Under the control of the write / erase control circuit 25, the word line voltage change circuit 23 for changing the voltage applied to the word line according to the operation mode of the flash memory, and the write / erase control circuit 25. A source potential generation circuit 2 for applying a voltage according to an operation mode to each source of a memory cell under control
Including 4.

In the memory cell array 110, one source line Si (S1, S2) is provided for each unit (for example, 1 byte) of memory cells accessed at one time, and the source line Si is a common source. It is connected to the source potential generating circuit 24 via the line S. That is, the access-unit memory cells arranged in the column direction are connected to the same source line Si. By thus providing one source line for each memory cell of the access unit, the wiring area of the source line is reduced and high integration is achieved.

The voltage generated from the word line voltage changing circuit 23 is applied to the X decoder 12. The X decoder 12 transmits the voltage from the word line voltage changing circuit 23 to the selected word line as a word line drive signal.

The high voltage Vpp is usually 12V, and the operating power supply voltage Vcc is usually 5V. Source potential generation circuit 2
4 generates a high voltage Vpp in the erase mode to generate the source line S
i, and source line Si is connected to the ground potential in the write and read operation modes.

The write circuit 20 outputs a write high voltage (about 6V lower than the high voltage Vpp) at the time of writing data "0" (corresponding to the write state), and the data ("" corresponding to the erase state). When writing "1"), a voltage of the ground potential level is generated.

The word line voltage changing circuit 23 generates a high voltage Vpp, an operating power supply voltage Vcc, a write verify voltage Vwr, and an erase verify voltage Ver according to various operation modes.

FIG. 24 shows a specific structure of the word line voltage changing circuit shown in FIG. In FIG. 24, a word line voltage changing circuit 23 is a Vpp / Vcc switching circuit 2
Includes resistors 35 and 36 and an n-channel MOS (insulated gate field effect) transistor 34 connected in series between node ND1 receiving voltage Vpp / Vcc from 2 and ground potential. Here, “Vpp / Vcc” is the voltage V
Either pp or voltage Vcc is shown. Resistance 35
And 36 have resistance values R1 and R2, respectively.
Transistor 34 becomes conductive in response to verify signal VRFY. The voltage Vpp / Vcc or the verify voltage is output from the node ND2 which is the connection point between the resistors 35 and 36.

The verify signal VRFY is used to verify whether or not the memory cell is surely in the erased state in the erase operation mode, and whether the write data is surely written to the selected memory cell in the verify cycle and the data write operation. In the verify cycle for checking whether or not there is an active state of "H" level.

The word line voltage changing circuit 23 further includes an inverter circuit 37 for inverting the verify signal VRFY,
V which is activated in response to the outputs of the inverter circuit 37 and the Vpp switch 38 and transmits the voltage Vpp / Vcc
pp switch 38, voltage on input line 47a and input line 4
Comparing circuit 47 for comparing the voltage on 7b and comparing circuit 4
7 becomes conductive in response to the voltage on the output line 47c of No. 7,
A p-channel MOS transistor 29 transmitting voltage Vpp / Vcc to X decoder 22 (see FIG. 23) via signal line 23a, and an n-channel MOS transistor resetting output line 47c to the ground potential in response to the output of inverter circuit 37.
The transistor 30 is included.

Comparing circuit 47 responds to the output signal of Vpp switch 38 to selectively transmit voltage Vpp / Vcc to node ND3.
And p provided between the nodes ND3 and ND4
Between the channel MOS transistor 27, the p-channel MOS transistor 28 provided between the nodes ND3 and ND5, the n-channel MOS transistor 32 provided between the nodes ND4 and ND6, and between the nodes ND5 and ND6 N channel M provided in
It includes an OS transistor 31 and an n-channel MOS transistor 33 connected between node ND6 and the ground potential.

Node ND4 has transistors 27 and 2
8 gates. This causes the transistor 27
And 28 form a current mirror circuit, and the same amount of current flows through the transistors 27 and 28.
The gate of the transistor 31 is connected to the node ND2 via the input line 47a. The gate of the transistor 32 is connected to the signal line 23a via the input line 47b. The verify signal VRFY is applied to the gate of the transistor 33. The comparison circuit 47 is activated in response to the verify signal VRFY, and the voltage on the signal line 47 a and the signal line 23.
It has the function of setting the voltages on a and 47b to be the same.

FIG. 25 shows a specific structure of Vpp switch 38 shown in FIG. In FIG. 25, V
The pp switch 38 has an inverter circuit 145 that inverts an input signal (Vpp switch activation signal) and its gate coupled to the operating power supply voltage Vcc.
N-channel MOS transistor 14 for transmitting the output of 5
3, a p-channel MOS transistor 141 and an n-channel MOS transistor 144 that form an inverter that inverts the signal transmitted from the transistor 143,
The voltage Vpp in response to the signal potential on the output node ND10
P-channel MOS for transmitting / Vcc to the node ND11
A transistor 142 is included.

Voltage Vpp / Vcc is transmitted to one conduction terminal (source terminal) of transistor 141. When the node ND11 becomes the high voltage Vpp level, the transistor 143 outputs the high voltage Vpp at the inverter circuit 14 level.
5 has a function of preventing application to the output. Before describing the operation of the entire flash memory, the operation of the word line voltage changing circuit 23 will be described with reference to FIGS. 24 and 25.

When the verify operation is not performed, that is, in the erase operation, data write and data read modes, verify signal VRFY is at the ground potential level "L". In this state, transistors 33 and 34 are turned off, while transistor 30 is turned on by a signal of "H" (operating power supply voltage Vcc level) from inverter circuit 37.

When the transistor 33 is turned off, no current flows in the comparison circuit 47, and the comparison circuit 47 becomes inactive. When transistor 34 is turned off, current does not flow through resistors 35 and 36, and voltage Vpp / Vcc applied to node ND1 is output from node ND2.
On the other hand, since the transistor 30 is turned on,
The potential of the signal line 47c becomes "L" of the ground potential level,
Transistor 29 is turned on, and voltage Vpp / Vcc is transmitted to signal line 23a.

In the verify operation mode, verify signal VRFY is at "H" level of operating power supply voltage Vcc.
Becomes As a result, the transistors 33 and 34 are turned on, while the transistor 30 is turned off by the output of the inverter circuit 37. In this state, a current flows through the resistors 35 and 36, so that the node N
The voltage Vpp / Vc applied to the node ND1 from D2
A voltage obtained by resistance-dividing c by resistance values R1 and R2 is given. The voltage of the node ND2 is applied to the gate of the transistor 31 of the comparison circuit 47 via the signal line 47a. Since the transistor 33 is in the ON state, this comparison circuit 4
7 performs the comparison operation.

The Vpp switch 38 is the inverter circuit 3
Since the output of 7 is "L", the output of the inverter circuit 145 becomes "H". Accordingly, the transistor 144 is turned on and the potential of the node ND10 becomes low level. Now, when the voltage Vpp is applied to the transistor 141 and the potential of the node ND11 is at the voltage Vcc level, the transistor 141 is turned on, and a current flows through the transistors 141 and 144. However, when the potential level of the node ND10 becomes low level, the transistor 142 is turned on and the voltage Vpp / Vcc is transmitted to the node ND11.
As a result, the transistor 141 is surely set to the off state, and the node ND10 becomes the ground potential level "L". In response to this, the transistor 26 of the comparison circuit 47 is turned on, and the potential of the node ND3 is Vpp / Vcc.
Becomes

Transistor 31 is turned on in response to the voltage on input line 47a (hereinafter referred to as erase verify voltage Ver), and the potential of node ND5 is the voltage between nodes ND3 and ND6.
The resistance is divided by the ON resistance of. Output line 4 at this time
The voltage on 7c becomes higher than the ground potential level, and accordingly, the transistor 29 approaches the off state, its resistance value increases, and the voltage on the signal line 23a is changed to the voltage Vpp / Vcc.
Lower more. The voltage on the signal line 23a is applied to the gate of the transistor 32. The resistance value of the transistor 32 increases as the voltage on the signal line 23a decreases, thereby increasing the potential of the node ND4.

This rise in the potential of node ND4 is fed back to the gates of transistors 27 and 28. As a result, the resistance values of transistors 27 and 28 increase, and the amount of current flowing through transistors 27 and 28 decreases. This lowers the potential of the node ND5, lowers the resistance value of the transistor 29 via the signal line 47c, and raises the voltage on the signal line 23a.

That is, the comparator circuit 47 operates such that, during its operation, the erase verify voltage Ver applied to the input line 47a and the voltage transmitted on the signal line 23a become equal. Therefore, the voltage determined by resistance values R1 and R2 is transmitted to X decoder through signal line 23a. By properly setting the resistance values R1 and R2, an erase verify voltage having a desired voltage level can be generated.

When the verify signal VRFY is at the low level, the node ND11 of the Vpp switch 38 shown in FIG. 25 is at the ground potential level of the low level, and the voltage of the voltage Vpp / Vcc level is generated at the node ND10. Then, the transistor 142 is turned off. As a result, the transistor 26 of the comparison circuit 47 is set to the OFF state because the source and the gate thereof have the same potential regardless of the voltage Vpp / Vcc, and the signal line 4c is reset even when the signal line 47c is reset.
No current flows from 7c to transistor 30.

Next, returning to FIG. 23, the entire operation of the flash memory will be described. Writing of data to the memory cell is activated by a control signal, that is, a chip enable signal CE and a write enable signal WE. The writing operation of external data to the selected memory cell includes an erase operation mode for erasing the memory cell and a write operation mode for actually writing data to the selected memory cell. In the following description, both the erase operation mode and the write operation mode will be collectively referred to as a program mode. First, the write operation mode of the program modes will be described first.

In the write operation mode, Vpp / V
The cc switching circuit 22 generates a high voltage Vpp under the control of the write / erase control circuit 25. Since the word line voltage changing circuit 23 is not in the verify mode, the verify signal is "L", the high voltage Vpp is generated, and the X decoder 1
Give to 2. The source potential generation circuit 24 connects the common source line S to the ground potential under the control of the write / erase control circuit 25. As a result, each source line Si (S1, S2) is set to the ground potential.

Address buffer 8 has its address strobe timing determined by write / erase control circuit 25, and generates an internal address signal from the applied address signal. Now, assume that the word line W0 and the bit line B0 are selected. In this case, the X decoder 12 transmits the high voltage Vpp transmitted from the word line voltage changing circuit 23 onto the word line W0. The Y decoder 9 uses the column selection signal Y0.
To a high level. The high level of the column selection signal Y0 is a voltage at which the write high voltage is higher than the power supply voltage Vcc, and the operating power supply voltage Vcc is required to pass this voltage.
Higher level than. The structure for generating the write high voltage by Y decoder 9 may be the same as that for word line voltage changing circuit 23 shown in FIG. 24, and a structure for generating voltage Vpp by resistance division may be used.

Under the control of write / erase control circuit 25, data input / output buffer 21 receives write data D from the outside, generates internal data, and supplies it to write circuit 20. Under the control of write / erase control circuit 25, write circuit 20 generates a write high voltage (usually about 6 V) when writing data "0". In the case of data "1", a signal of the ground potential level is generated. The column selection signal Y0 turns on the Y gate transistor 10 included in the column selection gate 120, and applies a write high voltage onto the bit line B0. As a result, a high electric field is applied between the control gate and drain of the memory cell 16, and hot electrons are injected into the floating gate. As a result, the threshold voltage of the memory cell 16 rises and the memory cell 16 enters the write state and stores the data "0". When writing data "1", since a high electric field is not applied to the drain, hot electrons are not generated and charges are not injected / released to / from the floating gate. The reason why the data "1" is not written is that the memory cell is set to the erased state (data "1" stored state) prior to the data writing.

Next, the erase operation mode executed prior to the data write operation for setting this memory cell to the erased state will be described with reference to the flow chart shown in FIG.

The write / erase control circuit 25 first enters the erase operation mode when both the chip enable signal CE and the write enable WE are activated. In the flash memory, all memory cells are simultaneously erased in this erase operation mode. At this time, in order to equalize the threshold voltages of all the memory cells, pre-erase writing for writing data "0" is first performed to all the memory cells (step S501 in FIG. 26).

In this pre-erase write cycle, write circuit 20 generates a write high voltage, X decoder 12 selects all word lines (W0, W1), and Y decoder 9 selects all columns. The signal Y (Y1, Y0) is set to the active state. The word line voltage changing circuit 23 generates a high voltage Vpp and supplies it to the X decoder 12. Source potential generation circuit 2
4 generates a ground potential and transmits it to the common source line S. As a result, the write high voltage is applied to the drains of all the memory cells 16, 17, 18 and 19, the high voltage Vpp is applied to the control gate, and the sources are set to the ground potential. As a result, all the memory cells are set to the written state in which the data "0" has been written. The operation of writing to all the memory cells to raise the threshold voltage thereof is called a pre-erase write operation.

After completion of the write operation before erasure, all memory cells are set to the erased state. At this time, the X decoder 1
2 sets all word lines W0 and W1 in a non-selected state and sets the potential thereof to the ground potential level. Also Y decoder 9
Is also deactivated and column selection signals Y0 and Y1 are set to "L". As a result, the bit lines B0 and B1 are set to the floating state. On the other hand, the source potential generation circuit 24 generates the high voltage Vpp for a predetermined period under the control of the write / erase control circuit 25 to generate the common source line S.
Give to. The high voltage Vpp generated during this predetermined period is a pulsed signal and is called an erase voltage pulse. By applying this erase voltage pulse, in each memory cell,
Electrons are extracted from the floating gate to the source due to the tunnel effect, and the threshold voltage of the memory cell drops (step S502).

Then, a verify operation for confirming whether or not the memory cell is set to the erased state is executed. In this verify cycle, the source potential generation circuit 24 connects the common source line S to the ground potential (step S503).

Next, the X decoder 12 and the Y decoder 9 select the memory cell at address 0 (step S50).
4). The erase verify voltage Ver is transmitted from the word line voltage changing circuit 23 via the X decoder 12 to the word line to which the selected memory cell at address 0 is connected.
That is, in FIG. 24, the verify signal VRFY is "H", and the verify voltage Ver from the signal line 23a.
Is generated.

Now, the memory cell at address 0 is the memory cell 16
Suppose The data in the memory cell 16 at address 0 is detected and amplified by the sense amplifier 15 and then transmitted to the write / erase control circuit 25. The write / erase control circuit 25 determines whether the data supplied from the sense amplifier 15 is the data "1" indicating the erased state (step S5).
06). If the read data is the data "1", it indicates that the threshold voltage of the memory cell is lower than the erase verify voltage Ver, which indicates that the memory cell is in the erased state. In this case, the write / erase control circuit 25 determines whether or not the address of the selected memory cell is the final address (step S507), and if it is not the final address, increments the address by 1 (step S508). , And returns to step S506. If it is determined in step S507 that the memory cell at the last address stores data "1", the erase operation mode ends.

On the other hand, if the write / erase control circuit 25 determines that the read data is not "1" at a certain address in step S506, the memory cell has a threshold voltage equal to or lower than the desired erase verify voltage. Memory cell, it is determined that the memory cell is not in the erased state,
It returns to step S502. That is, a high voltage erase voltage pulse is applied from the source potential generation circuit 24 to the source line, and the erase operation is executed for each memory cell. Thereafter, the memory cell from address 0 is selected again, the stored data is read, and this operation is repeated until it is confirmed that the threshold voltages of all the memory cells are equal to or lower than the erase verify voltage.

Here, the erase verify voltage Ver is set lower than the voltage transmitted to the word line during normal data reading.

[0050]

In the flash memory cell, the erased state is realized by the emission of electrons from the floating gate. This electron emission is performed by generating a tunnel current between the floating gate and the source region. The amount of electrons emitted depends on the height and width of the erase voltage pulse applied between the floating gate and the source region and the number of times the erase voltage pulse is applied.

In the erase operation mode described above, after programming before erasure is performed to align the threshold voltages of the memory cells,
By applying the erase voltage pulse and verifying, the threshold voltage of the memory cell is lowered to a predetermined value (erase verify voltage) or less.

The source line is commonly provided for memory cells of access unit (for example, 1 byte). A wiring is required to connect the source region and this source line, and therefore a source resistance exists. This source resistance causes a state where the source potentials are different in the memory cells in the access unit. Therefore, even in the memory cells in the access unit, the amount of electron emission at the time of erasing is different, and the erase characteristics vary.

In the memory cell array, variations in the gate insulating film, variations in the channel area, and the like may occur as local factors due to variations in the manufacturing process. Even in this case, the erase characteristics of the memory cells also vary.

When variations occur in the erase characteristics of such memory cells, application of an erase voltage pulse causes
A state occurs in which electrons are excessively extracted from the floating gate of the memory cell.

The state in which electrons are excessively extracted from the floating gate is called an over-erased state, and the threshold voltage of the over-erased memory cell indicates a depletion state. Here, the "depletion state" refers to a state in which a source-drain current flows through the memory cell in a state where the ground potential is applied to the control gate.

That is, as shown in FIG. 27, pre-erase writing is performed to adjust the threshold voltages of the memory cells within a predetermined range, and then erasing is performed to verify the threshold voltage of each memory cell. When the voltage is set to be less than or equal to Ver, FIG.
In FIG. 7, there are overerased memory cells as indicated by the broken line. When an unerased cell is found during verification, the erase voltage pulse is applied again. This is also applied to cells in the erased state, which also causes overerasure.

If this over-erased memory cell exists, the problem that accurate data cannot be read occurs.

The problem of this over-erased memory cell is shown in FIG.
This will be described with reference to FIG. In FIG. 28, memory cells FM1, FM2, and FM arranged at intersections of three word lines WL1, WL2, and WL3 and bit line BL.
3 shows a state in which 3 is provided. The memory cell FM1 stores data "1" and is in an erased state. Memory cell F
M2 is in a state of being over-erased, and is shown as a state of storing data "11" in FIG. Memory cell FM
3 is in a writing state and stores data "0".

At the time of data reading, a voltage of about operating power supply voltage Vcc is transmitted on the selected word line according to the applied address, while a read voltage for generating a current is applied on bit line BL. This bit line BL
Data is read by detecting the presence / absence of current in the sense amplifier. Now memory cell FM
2 is in an over-erased state. Therefore, the word line W
Regardless of whether L2 is selected or not, this memory cell FM
2 is always in a conducting state. Now, consider a state in which the memory cell FM3 is selected. Memory cell FM3 has data "0"
The memory cell FM3 is in a non-conductive state even when the word line WL3 is selected. However, in this case, even if the word line WL2 is in the non-selected state, the memory cell FM2 is in the conductive state, the current flows from the bit line BL to the source line SL, and the memory cell FM3 stores the data "1" in the erased state. It is determined that That is, the data "0" is erroneously read as the data "1", and a highly reliable flash memory cannot be obtained.

Further, in order to actually write the data to the memory cell, after the erase operation mode described above is performed, the write operation mode for actually writing the data to the memory cell is executed.

That is, as shown in FIG. 29, the program mode requires a sequence for executing the erase operation mode and a sequence for executing the write operation mode. The erase operation mode is similar to the flow shown in FIG.
In FIG. 29, it is shown in a slightly simplified form. That is, in the erase operation mode, pre-erase writing (step S60
After step 2) is performed, an erase pulse is applied to reduce the threshold voltage of the memory cell (step S603), and then erase verify is performed to determine whether the memory cell is below a predetermined threshold voltage. Executed (step S60
4) When it is confirmed that all the memory cells are in the erased state, the erase operation mode is completed (step S60).
6).

After the erase operation mode is completed, the write operation mode is newly started (step S608). In this write operation mode, write data is first applied to write circuit 20, and a write pulse is applied from write circuit 20 to a memory cell in which data "0" is written (step S610). This write pulse applies a high voltage V to the word line.
With pp applied, a predetermined high voltage for writing is applied in pulses. After applying this write pulse, the content of the written data is read. When reading the content of the write data, a write verify voltage slightly higher than the operating power supply voltage Vcc (voltage level applied to the word line in the normal read mode) is applied to the selected word line.
The written data of the memory cell is read, and when the write data does not match, the application of the write pulse to the selected memory cell is executed again, and the write verify is executed again (step S612). ). Matching / non-matching between the write data and the stored data of the selected memory cell is performed in write / erase control circuit 25 shown in FIG. If the stored data and the written data match in this write verify cycle, the writing of the data to the selected memory cell is completed. This write operation mode is executed for all memory cells to be written. Therefore, the conventional flash memory has a problem that the program mode takes a long time.

Particularly, in the erase operation mode, after all memory cells are set to the erased state, erase verify is required to determine whether or not each memory cell is set to the erased state. Therefore, there is a problem that the time required for the erase operation mode becomes particularly long.

In the write operation mode, data is written in units of data write (usually in units of 1 byte), but data is normally written only in 1-byte memory cells. Instead, the data is sequentially written into the memory cells of a plurality of bytes, and the time required for the write operation mode also becomes long.

Although both the erase operation mode and the write operation mode are executed under the write / erase control circuit, the erase operation mode and the write operation mode have independent operation sequences. However, this causes a problem that the control operation becomes complicated and the program operation becomes complicated.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device which can easily and surely write data to a memory cell in a short time.

Another object of the present invention is to provide a non-volatile semiconductor memory device capable of shortening the time required for the erase operation mode.

Still another object of the present invention is to provide a non-volatile semiconductor memory device capable of performing a stable and reliable erase operation even if the erase characteristics of memory cells vary.

[0069]

According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is arranged in a matrix of rows and columns, each of which is composed of a floating gate type transistor, and a charge accumulated in the floating gate. A memory cell array provided with a plurality of memory cells for storing data representing a written state and an erased state according to an amount, and arranged corresponding to each row of the memory cell array, and the memory cells of the corresponding row are connected to each. A plurality of word lines, a plurality of bit lines arranged corresponding to each column of the memory cell array and connected to memory cells of a corresponding column, and a plurality of corresponding bit lines in response to a given address signal. Memory cell selecting means for selecting a memory cell and erasing to the memory cell selected by the memory cell selecting means in the erase operation mode The erasing means for applying the pressure, the deciding means for deciding whether or not the threshold voltage of the memory cell to which the erasing voltage is applied after the application of the erasing voltage is below a predetermined value, and the deciding means. For the memory cells whose threshold voltage is determined to be less than or equal to the predetermined value, the threshold correction voltage is applied until all the threshold voltages are greater than or equal to the predetermined value and less than the threshold voltage expressing the written state. And a correction means for applying.

A nonvolatile semiconductor memory device according to a second aspect is arranged in a matrix of rows and columns, each having a floating gate type transistor, and a writing state and an erasing state according to the amount of charge accumulated in the floating gate. And a plurality of word lines arranged corresponding to each row of the memory cell array and connected to the memory cells of the corresponding row, and the memory cell array. A plurality of bit lines arranged corresponding to the respective columns, to which the memory cells in the corresponding columns are connected, a memory cell line selecting means for selecting a memory cell to be programmed, and the memory cell selecting means. A discriminator for discriminating whether or not the memory cell selected by has a threshold voltage equal to or higher than a predetermined threshold voltage. Determination data storage means for storing the data indicating the determination result of the determination means with respect to the memory cells connected to the corresponding bit lines, and the data stored by the determination data storage means. In response to the above, the erase voltage is selectively applied to the memory cell selected by the memory cell selection means, and the threshold voltage of the memory cell connected to the selected word line is set to the predetermined threshold voltage. Threshold voltage correcting means for setting the threshold voltage or less is provided.

According to another aspect of the non-volatile semiconductor memory device of the present invention, a memory cell array in which memory cells made of floating gate type transistors are arranged in a matrix of rows and columns, and arranged corresponding to each row of the memory cell array. A plurality of word lines connected to the memory cells of the corresponding rows and a plurality of bit lines arranged corresponding to the columns of the memory cell array and connected to the memory cells of the corresponding columns, respectively. In the program mode, an erase voltage is applied to the memory cells to be programmed to set all the memory cells to be programmed to the erased state, and after the erase of the memory cells by the erase means, according to the program data. Data writing means for writing corresponding data to the memory cell to be programmed is included.

In the nonvolatile semiconductor memory device according to a fourth aspect, in the nonvolatile semiconductor memory device according to the third aspect, the data writing means writes and erases the first logical value representing the written state. A charge injecting means is provided so that the efficiency of injecting charge into the floating gate is different when writing the data of the second logical value indicating the state into the memory cell.

Preferably, the charge injection efficiency when writing the second logic value data representing the erased state is smaller than the charge injection efficiency when writing the first logic value data.

[0074]

In the nonvolatile semiconductor memory device according to the first aspect, after the erase voltage is applied, the threshold voltage is corrected by the correction means only for the memory cells having a predetermined threshold voltage or less. Therefore, the threshold voltage distribution range can be reduced, and the existence probability of the over-erased memory cell can be significantly reduced.

According to another aspect of the non-volatile semiconductor memory device of the present invention, the erasing voltage is applied by the correcting means only to the memory cells having a predetermined threshold voltage or higher, so that the memory cell already in the erased state The erase voltage is not applied to the memory cell, and even if the erase characteristics of the memory cells vary, the threshold voltage distribution range can be made smaller and the existence probability of over-erased memory cells is greatly reduced. To do.

In the nonvolatile semiconductor memory device according to the third aspect, the erase pulse is applied to the memory cell to be programmed and then the data is written in accordance with the program data. Therefore, the erase operation mode is the cycle of applying the erase voltage pulse. However, the time required for the erase operation mode can be significantly reduced, and high-speed data writing can be performed. Further, since the data of "0" and "1" are written at the same time, it is equivalent to that the erase operation mode and the write operation mode are executed at the same time, and the erase operation mode and the write operation mode are separately independent. The control is greatly simplified as compared with the method that is executed.

According to another aspect of the non-volatile semiconductor memory device of the present invention, the efficiency of electron injection into the floating gate at the time of writing data "1" is smaller than the efficiency of electron injection at the time of writing data "0". Since electrons are injected into the floating gate even for memory cells that are over-erased after the erase voltage is applied, the threshold voltage becomes an enhancement state, and there is no over-erased memory cell. Moreover, since the electron injection efficiency of the data “1” is small, the change value of the threshold voltage is small, and the data “0” is not erroneously stored.

[0078]

1 is a diagram showing the configuration of a nonvolatile semiconductor memory device (flash memory) according to an embodiment of the present invention. In FIG. 1, parts corresponding to those of the conventional flash memory shown in FIG. 23 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, the flash memory according to the embodiment of the present invention changes the write pulse width to the write circuit 20 under the control of the write / erase control circuit 25 at the time of data writing. Write pulse width changing circuit 43 for transmitting, negative voltage switch circuit 44 for applying a negative voltage to the selected word line in the erase operation mode, and negative voltage generating circuit for transmitting a negative voltage to this negative voltage switch circuit 44. 45,
BL voltage change circuit 42 for changing the write voltage level transmitted to the bit line in the data write operation mode.
including.

Other configurations are almost the same as those of the conventional flash memory. However, the word line voltage changing circuit 46, during the writing after the erasing, performs the normal writing (in the operation mode in which data is actually written in the memory cell after the erasing operation mode).
Further, it further has a function of generating a voltage lower than the voltage transmitted to the word line and transmitting it to the X decoder 48. The structure of this word line voltage changing circuit 46 will be described in detail later, but in the verify mode, it is higher than the voltage applied to the word line in the data read (normal read mode) and the erase-after-write mode. A lower verify voltage is generated and transmitted to the X decoder. During normal writing and normal reading, a voltage of Vpp / Vcc level is applied.

Therefore, the word line voltage changing circuit 4
6 is at least Vpp, Vcc, erase verify voltage,
It has a function of generating a write voltage after erasing and four kinds of voltages.

The X decoder 48 has a function of setting the selected word line potential to the ground potential level and applying the non-selected word line to the high level in the erase operation mode. In the normal data write and read operation modes, X decoder 48 transmits the voltage of power supply voltage Vcc level onto the selected word line. Next, the operation will be described.

Normal writing and reading are performed in the same manner as the conventional one. Here, "normal writing" refers to the operation of injecting electrons into the floating gate of the selected memory cell and writing data "0". “Read” simply means an operation of reading the data of the selected memory cell via the sense amplifier 15 and the data input / output buffer 21. In the normal write and read operations, the address buffer 8 writes / writes.
The address signal applied under the control of the erase control circuit 25 is taken in and an internal address signal is generated. The internal address signal is X for designating the word line of the memory cell array 110.
It includes an address signal and a Y address signal designating a bit line. Since the X decoder 48 is in the normal write or read operation mode, it raises the potential of the selected word line to "H" of the voltage Vcc level and sets the remaining non-selected word lines to "L" of the ground potential level. To do. The Y decoder 9 decodes the applied Y address signal, and sets the column selection signal Y to "H" to select the corresponding bit line.

Whether data writing or data reading is performed is determined by output enable signal OE and write enable signal WE. At the time of data reading, output enable signal OE is in the active state, and the data on the bit line to which the selected memory cell is connected via the Y gate transistor included in column selection circuit 120 is transmitted to sense amplifier 15. It The sense amplifier 15 determines whether or not a current flows through this bit line, generates internal data according to the determination result, and supplies it to the data input / output buffer 21. Data input / output buffer 21 generates and outputs external read data Q from the applied internal read data.

At the time of data writing, write circuit 20 is activated under the control of write / erase control circuit 25, and when writing data "0", a write high voltage is generated. This write high voltage is transmitted onto the bit line B through the Y gate transistor (10 or 11) in the column selection gate circuit 120. At the time of data writing, the high voltage Vpp is generated from the word line voltage changing circuit 46, and the potential of the selected word line W (W0 or W1) becomes the high voltage pp via the X decoder 48. The source potential generation circuit 24 connects the common source line S to the ground potential under the control of the write / erase control circuit 25. As a result, hot electrons generated by avalanche breakdown are injected into the floating gate of the selected memory cell, the threshold voltage thereof is increased, and data "0" is written.

When writing data "1", the write circuit 20
Does not generate a write high voltage, writing to that memory cell is not executed and the erased state is held.

Next, the erase operation mode will be described with reference to FIG. 2 showing the operation flow.

In the flash memory according to the embodiment of the present invention, the pre-erase writing, which is performed for equalizing the threshold voltages of the memory cells before applying the erase voltage pulse, is not performed.

In the erase operation mode, the negative voltage generating circuit 45 is activated under the control of the write / erase control circuit 25, and a negative voltage of a predetermined voltage (about -10V) is generated to generate the negative voltage switch circuit 44. Transmitted to.

X decoder 48 decodes the X address signal from address buffer 8 and selects the corresponding word line. At this time, the X decoder 48 sets the potential of the selected word line to "L" of the ground potential level and the potential of the non-selected word line to "H" under the control of the write / erase control circuit 25 in the erase operation mode. Set to.

Negative voltage switch circuit 44 includes a negative voltage switch provided corresponding to each word line. The negative voltage switch transmits a predetermined negative voltage when the potential of the corresponding word line is "L". If the corresponding word line has the potential level of "H", it does not function at all and the potential of the word line is held at "H". The operation of the negative voltage switch circuit 44 is controlled by the write / erase control circuit 25 (step S71).

Then, source potential generating circuit 24 transmits a voltage of power supply voltage Vcc (about 5 V) level onto common source line S. On the other hand, the Y decoder 9 is inactivated, and all the Y gate transistors included in the column selection gate circuit 120 are turned off. As a result, all the bit lines B are floating means (high impedance state).
Is set to.

A large negative voltage of about -10 V is applied to the selected word line W by the negative voltage switch circuit 44, while a voltage of the power supply voltage Vcc level is applied from the source potential generating circuit 24 to the source line Si. It As a result, a high voltage of about 15 V is applied between the control gate and the source region of the selected memory cell,
A tunnel current flows between the floating gate and the source region, and electrons in the floating gate are emitted to the source region. This lowers the threshold voltage of the selected memory cell (steps S72 and S73).

After applying the erase voltage pulse by the negative voltage to the selected word line and the positive voltage to the source line, the source potential is set to the ground potential level of 0 V (step S).
74).

With the X address signal as it is, the Y decoder 9 is supplied with the Y address signal indicating the 0th address of the column, that is, the 0th column, and the Y decoder 9 selects the bit line of the 0th column (step S75). ..

Then, under the control of the write / erase control circuit 25, the verify voltage VT is generated from the word line voltage changing circuit 46 and transmitted to the selected word line via the X decoder 48. This verify voltage VT is equal to or higher than ground potential 0V and is a power supply voltage Vcc applied during normal reading.
It is well below the level. This verify voltage V
T may be 0V.

Then, the sense amplifier 15 is activated under the control of the write / erase control circuit 25 to read the data of the memory cell in the 0th column and transmit it to the write / erase control circuit 25.
The write / erase control circuit 25 determines whether or not the data transmitted from the sense amplifier 15 is "0". That is, it is determined whether the threshold voltage of the memory cell in the 0th column is higher than the verify voltage VT (step S).
77). The erase voltage pulse is applied only to the memory cell connected to the selected one word line, and the erase voltage pulse is not applied to the other memory cells. Therefore, since the memory cells connected to the other non-selected word lines existing on the same bit line are not in the over-erased state, they have no influence on the read data for the memory cell in the 0th column. ..

The 0th word connected to this selected word line
When the data in the memory cell in the column is "1", that is, when the threshold voltage of the memory cell is lower than the verify voltage VT level, the write voltage is applied to the memory cell in the 0th column (step S78). That is, the write circuit 20 is activated and a write voltage is applied to the word line and the bit line. In this case, write pulse width changing circuit 43 generates a write pulse having a shorter pulse width than that at the time of normal writing under the control of write / erase control circuit 25, and applies it to write circuit 20. As a result, the write circuit 20 generates a write pulse having a shorter pulse width than that in normal writing.

Further, bit line voltage changing circuit 42 is activated to generate a voltage lower than that in the normal write operation and apply it to Y decoder 9. In this state, the level of the column selection signal Y becomes low and the resistance value of the Y gate transistor becomes high. The Y gate transistor is a MOS transistor, and passes only a voltage obtained by subtracting a threshold voltage from the voltage applied to its gate voltage. As a result, the bit line B
A write voltage having a lower voltage level than that at the time of normal writing is transmitted upward.

A high voltage having a voltage level lower than that at the normal writing is transmitted from the word line voltage changing circuit 46 onto the selected word line. Under this state, hot electrons are injected into the floating gate by avalanche breakdown in the selected memory cell.

At this time, the energy given by the write voltage is smaller than that during normal writing. Therefore, the number of hot electrons generated and the number of electrons injected into the floating gate are smaller than in normal writing, and the amount of change in the threshold voltage of the memory cell is smaller than in normal writing.

The relationship between the write pulse and the amount of change in the threshold voltage of the memory cell will be described with reference to FIG.
In FIG. 3, the horizontal axis represents the write pulse application time (in microsecond units), and the vertical axis represents the threshold voltage of the memory cell.
The curve indicated by a circle shows the change in the threshold voltage of the memory cell under the application conditions of the drain voltage of 5V and the control gate voltage of 12V, and the curve indicated by the ● indicates the drain voltage of 5V and the gate voltage of 10V. Indicates the change in the threshold voltage.

As seen in FIG. 3, drain voltage 5
When writing is performed under the conditions of V and the control gate voltage of 12V, when the pulse width (writing pulse time) is 10 microseconds, the shift of the threshold voltage of about 6V is confirmed. On the other hand, when the write pulse width is set to 1 microsecond under the conditions of the drain voltage of 5V and the control gate voltage of 12V, the threshold voltage changes by about 1V. Here, the threshold voltage uses a memory cell of about 1 V when no write pulse is applied.

Therefore, the write pulse width changing circuit 43 shortens the write pulse width in the post-erase write operation mode as compared with the normal write to reduce the amount of change in the threshold voltage of the memory cell. Therefore, the threshold voltage of the memory cell can be gradually increased.

As shown in FIG. 3, when the control gate voltage is lowered from 12 V to 10 V, the change amount of the threshold voltage is reduced in the region where the write pulse width is 1 μs (microsecond) or more. You can Therefore, by lowering the control gate voltage, the threshold voltage of the memory cell can be gradually increased at the time of writing after erasing.

As described above, the amount of change in the threshold voltage is reduced to carry out the verification, and the post-erase writing to the memory cell is executed until the threshold voltage of the memory cell becomes equal to or higher than the verify voltage VT. To do. When the read data becomes "0" under the condition that the voltage of the word line is the verify voltage VT, it is determined whether or not the Y address is the final address (step S79). Increment the Y address by 1 (step S8
0), and returns to step S76.

This operation is executed for all the memory cells connected to the selected word line, and the memory cells connected to this selected word line have a threshold voltage lower than the verify voltage VT. The above-described write operation after erase is executed on the cell. As a result, the threshold voltages of the memory cells connected to the selected word line are all higher than the verify voltage VT.

As a result, as shown in FIG. 4, in the state where the erase voltage is applied after the word line is selected, the threshold voltage of the memory cells (curve A) which is widely distributed due to the variation of the erase characteristics of each memory cell. The threshold voltage is gradually increased, so that the threshold voltage is distributed in a narrow region as shown by the curve B.

For example, when threshold voltage Vth1 is set to verify voltage VT, post-erase programming is executed for a memory cell having a threshold voltage lower than this threshold Vth1, and curve A indicates that The threshold voltage distribution of the memory cell shown shifts to the threshold voltage distribution shown by the curve B. In this state, the threshold voltage Vth
For the memory cells near 1, the threshold voltage may be slightly smaller than the threshold voltage Vth1. However, in this case, when the word line potential is 0 V during normal data reading, the ON resistance is extremely high, and only a negligible source / drain current is generated, and the data “0” is erroneously read as the data “1”. Therefore, the erroneous reading of data by the overerased memory cell is prevented.

Further, as described above, in the configuration in which the negative voltage is applied to the selected word line in the erase operation mode, it suffices to apply a voltage of about the power supply voltage Vcc level to the source region and the high voltage Vpp to the source region. Since no electrons are applied in this region, hot electrons are not generated in this region, only electrons are emitted from the floating gate due to the tunneling current, and it is possible to prevent damage to the gate insulating film due to hot holes. The life of the memory can be extended.

As will be described later in detail, such a negative voltage is applied only to the selected word line, and the driving load capacitance is small. Therefore, the negative voltage can be easily made negative by the charge pump circuit using the capacitance. A voltage can be generated. Further, in this configuration, the high voltage Vpp can be similarly generated internally by the charge pump operation, and in this case also, since the high voltage Vpp is only applied to the selected word line, the capacity can be easily used. Can be generated by the existing charge pump circuit. 5V by this
It is possible to easily generate both the high voltage Vpp and the negative voltage from the operating power source voltage Vcc of about 5% in a small occupied area.
It is possible to obtain a flash memory with a single power supply.

In the structure shown in FIG. 1, bit line voltage changing circuit 42, word line voltage changing circuit 46 and write pulse width changing circuit 43 may be driven simultaneously, and only one of them may be selected. It may be configured to be driven mechanically. By operating these circuits in combination, it is possible to accurately control the amount of change in the threshold voltage in the post-erase writing.

The series of erase operation cycles shown in the flow chart of FIG. 2 may be implemented in the chip using hardware. Further, write / erase control circuit 25 may be configured by a microprocessor and programmed to execute the flowchart shown in FIG. This erase operation cycle is easily realized by hardware by the configuration of the control circuit that is activated when both the chip enable signal CE and the write enable WE are activated and the desired operation is executed sequentially and sequentially. be able to.

Next, the specific structure and operation of each circuit will be sequentially described in detail. FIG. 5 is a diagram showing a specific configuration of the word line voltage changing circuit shown in FIG. In FIG. 5, word line voltage changing circuit 46 responds to NOR circuit 57 receiving post-erase write instruction signal PAE and verify signal VRFY indicating the verify operation mode, and post-erase write signal PAE and verify signal VRFY. And a voltage generator 460 that selectively generates a desired word line drive voltage. Post-erase write signal PAE and verify signal VRFY are applied from write / erase control circuit 25 shown in FIG. The NOR circuit 57 uses the post-erase write signal PAE.
And a signal of "H" is generated only when both the verify signal VRFY become "L".

The voltage generator 460 generates the voltage Vpp / Vcc.
It includes resistors 50, 51 and 52 and an n channel MOS transistor 63 connected in series between node ND20 receiving the signal and ground potential. The resistors 50, 51 and 52 have resistance values R11, R12 and R13, respectively. The transistor 63 receives the output of the NOR circuit 57 at its gate via the inverter circuit 58.

Voltage generation unit 460 further changes the voltage on node ND21 in response to the output of Vpp switch 55 and Vpp switch 55 that selectively generates voltage Vpp / Vcc in response to post-erase write signal PAE. It includes an n channel MOS transistor 53 transmitting to signal line 49a, and an n channel MOS transistor 54 transmitting a voltage on node ND22 to signal line 49a in response to verify signal VRFY.

The Vpp switch 55 has a function of selectively passing the high voltage Vpp in accordance with the signal of "H" of 5V level. The structure of this Vpp switch 55 is similar to that shown in FIG. That is, Vpp switch 55 generates voltage Vpp / Vcc when post-erasing write signal PAE is in the active state of "H". The voltage Vpp / Vcc generated by the Vpp switch 55 is
It is the same as the voltage Vpp / Vcc applied to D20.

The word line voltage changing circuit 46 is further activated in response to the output of the inverter circuit 58, and the output voltage of the voltage generator 460 applied to the signal line 49a and the word line drive signal on the signal line 49b. In response to the output of the comparator circuit 49 for comparing the voltage with the NOR circuit 57, the voltage V
Vpp switch 56 for generating pp / Vcc and voltage Vp in response to a signal on output signal line 49c of comparison circuit 49.
p channel MO for transmitting p / Vcc onto the signal line 46a
It includes an S transistor 67 and an n channel MOS transistor 59 for resetting the output signal line 49c to the ground potential level in response to the output of the NOR circuit 57.

The Vpp switch 56 is the Vpp switch 55.
With the same configuration as the above, the voltage Vpp / Vcc is generated and the voltage Vpp / Vcc is supplied to the comparison circuit 49 to set the operating state. The voltage on the signal line 46 a is applied to the X decoder 48.

The comparison circuit 49 is the comparison circuit 4 shown in FIG.
7, a p-channel MOS transistor 66 that functions as a voltage supply source and receives the output signal of the Vpp switch 56 at its gate, and a p-channel MOS transistor 66 that is supplied with a voltage from the transistor 66 to form a current mirror circuit. Channel MOS transistors 64 and 65, and an n channel M receiving the signal on signal line 49a at its gate
An OS transistor 62, an n-channel MOS transistor 61 whose gate receives a signal on the signal line 49b,
Included is an n channel MOS transistor 60 which receives the output of inverter circuit 58 at its gate and provides a current path for transistors 61 and 62. This comparison circuit 49
24 is similar to that of the comparison circuit 47 shown in FIG. 24, and has a function of making the signal potential on the signal line 49a equal to the signal potential on the signal line 49b, that is, the signal line 46a when activated. Next, this word line voltage changing circuit 4
The operation of No. 6 will be described.

(I) During Verify Operation After selecting a word line, an erase voltage pulse is applied to the memory cell connected to the selected word line. After this erase voltage pulse is applied, it is determined whether or not the threshold voltage of the memory cell connected to the selected word line is equal to or lower than a predetermined verify voltage VT. During this verify operation, the verify signal VRFY becomes "H", and the post-erase write signal PAE is "L".

In this state, the Vpp switch 55
Output is "L" (see FIG. 25), and the transistor 5
3 is turned off. On the other hand, the transistor 54 is turned on in response to the verify signal VRFY. As a result, the node ND22 is connected to the signal line 49a. NO
The R circuit 57 outputs a signal of "L" because the verify signal VRFY is "H", and accordingly, the inverter circuit 58.
Outputs a signal of "H". As a result, the transistor 59 is turned off and the transistors 60 and 63 are turned on. Further, the Vpp switch 56 includes a NOR circuit 57.
The signal of "L" is output in response to the signal of "L".

As a result, the comparison circuit 49 is activated and compares the signal potential on the signal line 49a with the signal potential on the signal line 49b. The signal potential on node ND22 is transmitted onto signal line 49a. Since the transistor 63 is on, the voltage Vpp / Vcc applied to the node ND20 is applied to the node ND22 by the ratio R13: (R11 + R).
The voltage divided by resistance appears in 12). Therefore, the signal line 49b is changed by the function of the comparison circuit 49 (see FIG. 24).
That is, a voltage obtained by dividing the voltage Vpp / Vcc by the resistance value (R11 + R12) and the resistance value R13 is generated as the verify voltage VT on the signal line 46a and is transmitted to the X decoder.

(Ii) At the time of write operation after erasure The threshold voltage becomes the verify voltage V by the verify operation.
Writing after erasure is performed on the memory cell determined to be lower than T. At this time, the erase write signal PAE becomes "H". The verify signal VRFY is "L". In this state, the output of the Vpp switch 55 is the voltage Vpp /
The voltage becomes Vcc and the transistor 53 is turned on, while the transistor 54 is turned off. Due to the "H" state of the post-erasing write signal PAE, the transistors 60 and 63 are turned on and the transistor 54 is turned off. Further, the transistor 66 is turned on by the Vpp switch 56.

Therefore, in the write operation after erasure,
The voltage generated at node ND21 is transmitted onto signal line 49a. As the voltage appearing at the node ND21, the voltage Vpp / Vcc is the resistance value R11 and the resistance value (R12 +
A resistance-divided voltage is generated in R13). The post-erase write voltage Vew that appears during the post-erase write is higher than the verify voltage VT. According to post-erase write voltage Vew on signal line 49a, comparison circuit 49 generates post-erase write voltage Vew on signal lines 49b and 46a. As a result, the post-erase write voltage Vew lower than the high voltage Vpp is applied from the X decoder to the selected word line.

(Iii) At the time of normal writing and normal reading In the case of writing data "0" to the memory cell after completion of the erase operation mode and when reading the memory cell data, the post-erase write signal PAE and the verify signal. Both VRFY are "L". In this state, the transistor 53
Both and 54 are turned off. Also, NOR circuit 5
7 outputs a signal of "H" because both inputs are "L". As a result, the transistor 59 is turned on, and the transistors 60 and 63 are turned off by the "L" signal from the inverter circuit 58. Transistor 66
Has its gate connected to the voltage Vpp via Vpp switch 56.
Since it receives / Vcc, it is turned off. In this state, the potential of signal line 49c attains to the ground potential level "L", and transistor 67 transmits voltage Vpp / Vcc onto signal line 46. Voltage Vcc is transmitted to the X decoder in the normal read mode, and voltage Vpp is transmitted to the X decoder in the normal write mode.

As described above, according to post-erasing write signal PAE and verify signal VRFY, voltage Vpp / Vc is applied.
c, write voltage Vew after erase, and verify voltage VT
Can be selectively generated. Here, post-erase write voltage Vew is lower than the voltage during normal writing, and verify voltage VT is lower than voltage Vcc during normal reading and post-erase write voltage Vew.

After data writing, a write verify cycle is executed to determine whether this write data is correct. If the write verify voltage level applied to the word line at this time is different from the above-mentioned verify voltage VT, the voltage generating circuit 460 may generate another write verify voltage. .. This configuration can be easily realized by increasing the number of resistors by 1 in the resistance division circuit. Alternatively, at the time of write verify, a configuration may be used in which operating power supply voltage Vcc applied at the time of normal read is boosted and generated using a capacitor.

The verify voltage VT is higher than the ground potential and the threshold voltage of the memory cell after programming after erasure is lower than the threshold voltage indicating the programmed state. Any value will do.

With the structure described above, the voltage level transmitted to the word line in the write operation after erasing can be lowered, the threshold voltage change amount of the memory cell can be reduced, and the memory cell drain can be reduced. The distribution range of the threshold voltage can be narrowed.

FIG. 6 is a diagram showing an example of a specific configuration of the bit line voltage changing circuit and the Y decoder shown in FIG.
In FIG. 6, a bit line voltage changing circuit (BL voltage changing circuit) 42 has a node ND3 receiving the voltage Vpp / Vcc.
It includes resistors 70 and 71 and an n-channel MOS transistor 72 connected in series between 0 and the ground potential. The resistors 70 and 71 have resistance values R21 and R22, respectively.
Have. Transistor 72 receives erased write signal PAE at its gate. A node ND31 which is a connection node of the resistors 70 and 71 is connected to the signal line 68a. When the write signal PAE after erasure becomes "H", the node ND
31, the voltage Vpp / Vcc is set to the resistance values R21 and R21.
The voltage divided by 22 appears.

Bit line voltage changing circuit 42 is further activated in response to the output of inverter circuit 80 and inverter circuit 80 receiving post-erase write signal PAE, and voltage Vpp /
A comparison is made between a Vpp switch 81 that generates Vcc and a comparison circuit 68 that is activated in response to the post-erasing write signal PAE and the output of the Vpp switch 81 and that compares the signal potentials on the signal line 68a and the signal line 68b. In response to the signal on the signal line 68c transmitting the output signal of the circuit 68, the voltage Vpp / Vc
In response to the output of the p-channel MOS transistor 69 for selectively passing c and the inverter circuit 80, the signal line 6
It includes an n channel MOS transistor 76 for resetting 8c to the ground potential. The output voltage of the transistor 69 is transmitted to the Y decoder 9 via the signal line 42a.

The comparison circuit 68 is the comparison circuit 4 shown in FIG.
7 and a configuration similar to that of the comparison circuit 49 shown in FIG. That is, the comparison circuit 68 receives a p-channel MOS transistor 77 whose gate receives the output of the Vpp switch 81, and a p-channel MOS transistor 78 forming a current mirror type circuit which operates using a voltage supplied through the transistor 77 as a power supply voltage. 79, n channel MOS transistors 73 and 74 forming a differential amplifying means for comparing signals on the signal line 68a and the signal line 68b, and turned on in response to the post-erase write signal PAE, so that the transistor 73 is turned on. And n channel MOS transistor 75 providing a current path of 74.

The comparison circuit 68 becomes active when the post-erasing write signal PAE is "H", and differentially amplifies the signal potential on the signal line 68a and the signal potential on the signal line 68b to obtain a differential signal. The amplification result is transmitted to the signal line 68c. The resistance value of the transistor 69 varies according to the signal potential on the signal line 68c. The output voltage of the transistor 69 is the signal line 68.
is transmitted to b. Therefore, the comparator circuit 68, in operation, has a signal potential on the signal line 68a and the signal line 68a.
It has the function of setting the same potential as the signal potential on b.

When write signal PAE after erasure is "L", comparison circuit 68 is in an inactive state (transistors 77 and 7).
5 are both turned off), and the signal line 68c is set to the ground potential level by the transistor 76. Accordingly, transistor 69 transmits the applied voltage Vpp / Vcc onto signal line 42a.

Y decoder 9 includes a unit decoder provided corresponding to each Y gate transistor. This unit decoder includes a NAND type decode circuit 86 which receives a predetermined combination of address signals and a power supply voltage Vc.
n between the signal line 42a and the ground potential so as to receive the voltage transmitted through the transistor 84 and an n-channel MOS transistor 84 that functions as a protection resistor and receives the output of the decode circuit 86 at its gate. P-channel MOS transistor 82 and n-channel MOS transistor 85, which are complementarily connected to each other, and node ND36.
Included is a p-channel MOS transistor 83 that selectively transmits the signal potential on signal line 42a to node ND35 in response to the signal potential above. This transistor 83 is a node N
It is provided to stabilize the potential of D36. In the transistor 84, the signal potential of the node ND35 is high voltage Vpp.
In this case, the output transistor of the NAND type decode circuit 86 is prevented from being destroyed.

The NAND type decoding circuit 86 outputs a signal of "L" when all the address signals of the given combination are "H". In response to "L" of the node ND35, the transistor 85 is turned off and the transistor 8
2 is turned on. As a result, the signal potential on the signal line 42a is transmitted to the node ND36. Node ND36
The transistor 83 is turned off in response to the signal potential to the node ND35, and the potential of the node ND35 is held at "L" by the NAND type decoding circuit 86.

When the decode circuit 86 is in the non-selected state (when at least one bit of the applied address signal is "L"), the output of the decode circuit 86 is "H", the transistor 85 is in the ON state, and the transistor 82 is in the ON state. It is turned off. As a result, the potential level of the node ND36 becomes "L". The potential level of node ND36 is transmitted to the gate of transistor 83. The transistor 83 is turned on, and the potential level of the node ND35 changes to the signal line 4
The potential level on 2a is reached, and the transistor 82 is surely set to the off state. A column selection signal Y is generated from node ND36 and transmitted to the gate of the corresponding Y gate transistor. Next, the operation of changing the bit line voltage by the bit line voltage changing circuit 42 and the Y decoder 9 will be described.

(I) At the time of write operation after erasure At the time of write operation after erase, write signal PAE after erase becomes "H". In this state, comparison circuit 68 is activated and voltage Vpp / Vc applied to signal line 68a is applied.
A voltage obtained by resistance-dividing c by resistance values R21 and R22 is transmitted to the signal line 42a.

The selective decoding circuit 86 outputs an "L" signal. As a result, the voltage Vpp / Vcc is applied to the node ND36 via the transistor 82 as the resistance value R.
The voltage divided by the resistors 21 and R22 is transmitted. The voltage at this time is a voltage level lower than voltage Vpp / Vcc appearing at node ND36 during normal writing (Vpp normally appears because a write high voltage is transmitted during normal writing). As a result, the gate voltage of the Y gate transistor becomes lower than that during normal writing, and the write circuit 20
Even if a write high voltage is generated from, the signal potential transmitted to the corresponding bit line via the Y gate transistor becomes low. At this time, the voltage level transmitted to the bit line is determined by the voltage level applied to its gate and the threshold voltage of the Y gate transistor. Therefore, the resistance 7
The bit line voltage level can be adjusted to an appropriate level by the resistance values R21 and R22 of 0 and 71.

(Ii) In normal read mode, normal write and verify mode In this state, post-erasure write signal PAE is at "L". Therefore, voltage Vpp / Vcc is transmitted to signal line 42a according to its operation mode. This signal line 42a
The upper signal potential is the output node ND36 of the selective decoding circuit.
Transmitted to. Therefore, the voltage level of the column selection signal Y becomes the voltage Vpp / Vcc level.

It should be noted that the voltage Vpp / Vcc is
High voltage Vpp may be generated during normal writing and after erasing, and voltage Vcc may be generated during erase verify operation and normal reading. At this time, if a voltage higher than Vcc is applied to the word line at the time of write verify (a cycle for determining whether or not the write data is normal after the data write), the high voltage Vpp in the write verify mode. May be used.

FIG. 7 shows a specific structure of write pulse width changing circuit 43 shown in FIG. In FIG. 7, a write pulse width changing circuit 43 includes an oscillating circuit 87 that outputs an oscillating signal of a predetermined cycle, and a frequency dividing circuit that divides the oscillating signal from the oscillating circuit 87 by a frequency dividing ratio # 1 and outputs the divided signal. 88 and a frequency dividing circuit 89 for frequency-dividing the output signal of the frequency dividing circuit 88 by a frequency dividing ratio # 2.
A frequency dividing circuit 90 which divides the output signal of the frequency dividing circuit 89 by the frequency dividing ratio # 3; a frequency dividing circuit 91 which divides the output of the frequency dividing circuit 90 by the frequency dividing ratio # 4; It includes a selection circuit 900 which selectively passes one of the output signal of frequency dividing circuit 88 and the output signal of frequency dividing circuit 91 in response to an input signal PAE. A write pulse signal PGM is generated from selection circuit 900 and applied to write circuit 20. When writing data "0" in response to write pulse signal PGM, write circuit 20 generates a write high voltage within the time defined by write pulse signal PGM.

Select circuit 900 includes n-channel MOS transistor 92 and p-channel MOS transistor 94 which form one CMOS transmission gate.
And an n-channel MOS transistor 93 and a p-channel MOS transistor 95 forming the other CMOS transmission gate. After erasing, write signal PAE is applied to the gates of transistors 92 and 95. Post-erasing write signal PAE is applied to the gates of transistors 94 and 93 through inverter circuit 96.

Reset signal RS is applied to oscillation circuit 87 and frequency dividing circuits 88 to 91. Frequency divider circuits 88-91
, A pulse signal whose cycle becomes longer is generated.
That is, the cycle of the pulse signal output from the frequency dividing circuit 88 is shorter than the cycle of the output pulse signal of the frequency dividing circuit 91, and therefore the width of the output pulse of the frequency dividing circuit 88 is smaller than the width of the output pulse of the frequency dividing circuit 91. It gets shorter. Next, the operation will be described.

When the reset signal RS is active,
The oscillator circuit 87 does not oscillate, and the frequency divider circuit 88
Up to 91 also maintain the reset state, and no pulse signal is output in this state.

At the time of writing, the reset signal RS becomes inactive, and the oscillation circuit 87 and the frequency dividing circuits 88 to 91.
Operates and outputs a signal having a predetermined pulse width.

In a normal write operation, post-erase write signal PAE is at "L" and transistors 93 and 95 are provided.
Is turned on and the transistors 92 and 94 are turned off. Therefore, selection circuit 900 selects the output pulse signal from frequency dividing circuit 91 and applies it to write circuit 20 as write pulse signal PGM.

In the write operation after erasure, write signal PAE after erasure attains "H" and transistors 92 and 9 are provided.
4 is on, and transistors 93 and 95 are off. In this state, the selection circuit 900 has the frequency dividing circuit 88.
The output pulse signal of is selected and applied to the write circuit 20 as the write pulse signal PGM. The width of the output pulse signal of the frequency dividing circuit 88 is shorter than the pulse width of the output signal of the frequency dividing circuit 91. As a result, at the time of writing after erasing, writing is performed only for a short time, and the amount of change in the threshold voltage of the memory cell can be made smaller than that at the time of normal writing.

The write pulse width changing circuit 43 divides the output of the oscillating circuit 47 using a frequency dividing circuit and outputs it. A configuration in which the write pulse width is changed can be obtained by using a fall delay circuit that delays only the fall of the pulse signal from the oscillation circuit 87 instead of this frequency divider circuit.

When the erase voltage pulse is applied, the potential of the selected word line is set to a negative voltage, and a voltage of about 5 V is applied to the source line. This reduces the electric field applied to the source region and prevents damage to the gate insulating film (due to hot holes). The configuration for applying a negative voltage to the selected word line when the erase voltage pulse is applied will be described below.

FIG. 8 shows a specific structure of negative voltage generating circuit 45 shown in FIG. In FIG. 8, a negative voltage generating circuit 45 includes an oscillator 450 for generating two-phase pulse-shaped clock signals φ and / φ having a predetermined cycle, and an oscillator 450.
In response to a two-phase clock signal φ, / φ from which the charge pump operation is performed to generate a negative voltage, and the write / erase control circuit 25 receives a negative voltage generation instruction signal ENV. And a control circuit 452 for activating the oscillator 450. The control circuit 452 also monitors the negative voltage output from the charge pump circuit 454,
When the output negative voltage becomes equal to or lower than a predetermined level, the operation of the oscillator 450 is stopped and a predetermined level (about -1
It has a negative voltage monitor function for outputting a stable negative voltage of 0V). The structure of a level detection circuit for detecting whether or not such a negative voltage has reached a predetermined potential level is well known in the art.

Charge pump circuit 454 is connected in series between the ground potential and output node OG, and each is a diode-connected p channel MOS transistor T0.
It includes Tn and capacitors C1 to Cn for lowering the potentials of the connection nodes G1 to Gn by a charge pump operation. The transistors T0 to Tn are equivalent to diodes connected in the forward direction between the output node OG and the ground potential. The clock signal φ from the oscillator 450 is applied to the capacitors C1, C3 ... C (2i + 1). Capacity C2, ... C (2i) ...
A complementary clock signal / φ is applied to Cn from an oscillator 450. Next, the operation will be described.

When negative voltage generation instruction signal ENV is generated in the erase operation mode, control circuit 452 is activated and oscillator 450 generates two-phase clock signals φ and / φ.

When the clock signal φ becomes "H", the potentials of the nodes G1, G3, ... Gn-1 change to the capacitances C1, C3 ,.
It rises due to capacitive coupling of n-1. As a result, the transistors T0, T2, ... Tn-2 are turned on, and the potentials of the nodes G2 to Gn-1 also reach the levels corresponding to the potentials of the nodes at the preceding stages.

When the clock signal φ falls to "L", the potential levels of the nodes G1, G3, ... Gn-1 drop, the transistor T0 is turned off, and the transistors T2, T are turned on.
4 and Tn-2 are also turned off.

Then, when the clock signal / φ rises to "H", the potentials of the nodes G2, G4, ... Gn rise, the transistors T1, T3, ... Tn-1 are turned on, and the potential of the node at the previous stage changes. It is transmitted to each node. Then, when the clock signal / φ falls to "L", the transistors T1, T3, ... Tn-1 are turned off, the transistor Tn is turned on, and the output node OG has a potential level corresponding to the node Gn.

By repeating this operation, the potentials of the nodes G1 to Gn are sequentially lowered, and the potentials of the nodes G1 to Gn are reduced.
The charges of n are respectively transmitted to the nodes G0 to Gn−1 in the previous stage, and the charges are extracted from the output node OG at every cycle of the clock signals φ and / φ, that is, electrons are injected into the output node OG and the output node OG is output. Potential decreases. From the charge pump circuit 454, the potential difference between the nodes G0 to Gn is finally determined by the threshold voltage Vt of the transistor.
A negative voltage of h is generated and applied to output node OG. Therefore, a negative voltage determined by the product of the number of stages of transistors T0 to Tn and the threshold voltage appears at output node OG. Typically this negative voltage is at a level of about -10V.

Control circuit 452 detects the negative voltage level of output node OG, and when it reaches a predetermined level, oscillating circuit 450 stops the oscillating operation and does not perform the charge pump operation. Generate voltage.

FIG. 9 shows the negative voltage switch circuit 44 shown in FIG.
3 is a diagram showing a specific configuration of a negative voltage switch 440 included in FIG. The negative voltage switch 440 is provided corresponding to each word line. In FIG. 9, the negative voltage switch 440 is
A p-channel MOS transistor 441 transmitting a negative voltage from negative voltage generating circuit 45 to node 44a in response to a signal potential of output node 44b, and a p-channel MO diode-connected between node 44a and output node 44b.
S transistor 442, node 44a and node 44c
And a p-channel MOS transistor 44 selectively transmitting clock signal φn to node 44c in response to a signal potential on output node 44b.
Including 4.

Transistor 442 is diode-connected in the forward direction from node 44b to node 44a, and clock signal φn is generated from write / erase control circuit 25 only in the erase operation mode. It is electrically set to the floating state (high impedance state) or the ground potential except in the erase operation mode.

Between the corresponding word line and output node 44b, p channel MOS transistor 449 is turned on in response to negative voltage propagation signal NTR generated from write / erase control circuit 25 in the erase operation mode. Is provided. This negative voltage propagation signal NTR is a signal having substantially the same voltage level as the negative voltage generated from negative voltage generating circuit 45. Next, the operation will be described.

In the erase operation, the negative voltage propagation signal N
TR is generated, the transistor 449 is turned on, and the potential on the corresponding word line changes to the negative voltage output node 44b.
Transmitted to.

Now, it is assumed that the potential of the corresponding word line is at the ground potential level of 0V. At this time, the voltage of the ground potential level is applied to the gates of transistors 441 and 444 via node 44b. As a result, the transistor 444 is turned on and the clock signal φn is transferred to the node 4
4c.

When the clock signal φn rises from "L" of 0V level to "H" of 5V of power supply voltage Vcc level,
Due to the capacitive coupling of the capacitor 443, the potential of the node 44a rises. At this time, the transistor 441 receives the signal of the ground potential level at its gate and the negative voltage (about -10 V) from the negative voltage generating circuit 45 at the other conduction terminal thereof, so that the positive voltage injected into this node 44a is increased. The charges are discharged to the negative voltage generation circuit 45 via the transistor 441. Therefore, the potential of the node 44a is
And the threshold voltage Vthp of the transistor 441, that is, 0V + Vthp <1V.

Then, when the clock signal φn falls from "H" to "L", charges are extracted from the node 44a by the capacitive coupling of the capacitor 443, and the potential of the node 44a drops. Transistor 442 is turned on in response to the decrease in the potential of node 44a, and the potential of node 44a is transmitted to node 44b. Negative voltage output node 4 at this time
The potential of 4b and the potential of the node 44a are the parasitic capacitance and the capacitance 44 whose main constituent elements are the parasitic capacitance of the corresponding word line.
It becomes a value determined by the capacity of 3. At this time, the nodes 44b and 44a have at least a negative potential.

Then, when clock signal φn rises to "H", the potential of node 44a rises again due to capacitive coupling of capacitance 443. However, at this time, the potential of the node 44b is a negative potential, the transistor 441 is in an ON state, and the potential of the node 44a is a negative voltage output node 44b.
Voltage and the threshold voltage of the transistor 441. Transistor 442 is off because the potential of node 44a is higher than the potential of node 44b, and the potential of negative voltage output node 44b does not change.

Then, when clock signal φn falls to "L", the potential of node 44a falls again, and this falling potential is transmitted to negative voltage output node 44b.

By repeating the above operation, the potentials of node 44a and negative voltage output node 44b are sequentially reduced, and finally the potential of negative voltage output node 44b and the transistor 44 are supplied with the negative voltage applied from negative voltage generating circuit 45.
It lowers to a voltage level given by the sum of the threshold voltage Vthp of unity. Negative voltage propagation signal NTR is a signal of a level approximately the same as the negative voltage generated from the negative voltage generating circuit, the negative voltage on node 44b is transmitted to the corresponding word line, and the negative voltage of the corresponding word line is transmitted. The potential becomes a negative voltage.

When the potential of the corresponding word line is "H" at the power supply voltage Vcc level, transistors 441 and 444 are provided.
Since a signal of power supply voltage Vcc level is applied to the gate of, the transistors 441 and 444 are turned off. In this state, since the potential of node 44a does not change, the potential of negative voltage output node 44b holds the potential transmitted from the corresponding word line potential.

As described above, when the potential of the corresponding word line is at the ground potential level, that word line level can be set to a negative voltage. Therefore, when the erase word pulse is applied, if the potential of the selected word line is set to "L" at the ground potential level and the potential of the non-selected word line is set to "H" at the power supply voltage Vcc level by the X decoder, the selected word line potential is moved to Only the negative voltage can be applied, and the erase voltage pulse can be applied only to the memory cell connected to the selected word line. Next, a configuration for changing the potential of the selected word line according to this operation mode will be described.

FIG. 10 is a diagram showing a specific structure of the X decoder 48 shown in FIG. In FIG. 10, only the portion related to the word line W0 of the memory cell array 110 is shown.
The X decoder 48 receives a NAND type decode circuit 196 which receives a predetermined set of address signals (X address signals) and an erase signal ERASE generated at the time of an erase operation at its gate via an inverter circuit 195, and the decode circuit 1
N channel MOS transistor 191 for selectively transmitting the output of 96 to node ND50, and decode circuit 196
Inverter circuit 194 for inverting the output of the
An n-channel MOS transistor 192 that selectively transmits the output of the inverter circuit 194 to the node ND50 in response to RASE, and a word line drive from the word line voltage changing circuit 46 in response to the signal potential on the node ND50. A p-channel MOS transistor 198 for transmitting a signal to word line W0 and an n-channel MO transistor for setting word line W0 to the ground potential in response to the signal potential on node ND50.
The S-transistor 193, the p-channel MOS transistor 199 for cutting off the transistor 193 and the word line W0 when a negative voltage is applied to the word line W0, and the potential of the node ND50 in response to the signal potential on the word line W0. A p-channel MOS transistor 1 for stabilization that is set to the word line drive signal level from the line voltage changing circuit
Including 97. About -1 to the gate to transistor 199
A negative voltage of about V is applied. The negative voltage of -1 V may be given by the negative voltage from the negative voltage generating circuit 45 or may be given by another circuit. Next, the operation will be described.

During the erase operation, that is, when the erase voltage pulse is applied, the erase signal ERASE becomes "H". In this state, the transistor 191 is off and the transistor 192 is on. It is now assumed that the set of address signals applied to decode circuit 196 is all "H" and word line W0 is selected. In this state, the output of the NAND type decoding circuit 196 is "L", and the potential of the node ND50 becomes "H" via the inverter circuit 192. As a result, the transistor 198 is turned off and the transistor 193 is turned on. The transistor 199 is in the on state because a negative voltage of about -1 V is applied to its gate, and the potential of the word line W0 becomes the ground potential level "L".

The ground potential level on word line W0 is applied to the gate of transistor 197, and transistor 1
97 is turned on, and the voltage Vpp / Vcc from the word line voltage changing circuit (in this case, the voltage Vpp
cc) is applied, and the potential level of word line W0 is maintained at the ground potential level.

During the erase operation, the negative voltage propagation signal NT
R is generated, the transistor 449 is turned on,
Word line W0 is connected to negative potential switch 440. As described with reference to FIG. 9, when the word line potential is at the ground potential level, the negative potential switch 440 is driven, and the potential of the word line W0 becomes a negative potential via this negative potential switch 440 (here, The negative voltage propagation signal NTR is a signal of substantially the same level as the negative voltage generated from the negative voltage generation circuit 45).

When the potential of the word line W0 becomes negative, the gate potential of the transistor 199 becomes higher than the source potential and the transistor 199 is turned off. As a result, the transistor 1
93 and the word line W0 are separated, and the word line W0 is fixed to a negative potential.

On the other hand, when the word line W0 is in the non-selected state, the output of the decoding circuit 196 is "H" and the potential of the node ND50 is "L". In this state, the transistor 198 is turned on and the transistor 193 is turned off, and the potential of the word line W0 becomes the voltage level applied from the word line voltage changing circuit (Vcc level). Therefore, in this case, the negative voltage switch 440 does not operate even if the negative voltage propagation signal NTR is generated, and the potential of the word line W0 becomes "H".

The erase signal ERASE is set except in the erase operation, that is, in the operation mode in which the erase voltage pulse is applied.
Is "L". In this state, the transistor 191 is on and the transistor 192 is off. Therefore, when the word line W0 is selected, the decoding circuit 1
The output of 96 becomes "L", and the potential level of the node ND50 becomes "L" via the transistor 191. Therefore, the potential of the selected word line W0 becomes the voltage level applied from the word line voltage changing circuit via the transistor 198. Negative voltage propagation signal NTR other than erase operation
Is not generated and the word line W0 and the negative voltage switch 440 are separated.

By using the X decoder having the above-described structure, the selected word line is set to the negative voltage and the non-selected word line is set to the "H" level only when the erase voltage pulse is applied, and in the other operations. Can set the selected word line to the output voltage level from the word line voltage changing circuit and set the potential level of the non-selected word line to the ground potential level.

When the X decoder having such a configuration is used, V is applied to the source line S when the erase voltage pulse is applied.
Only the cc (5V) level voltage is applied, and it is not necessary to apply the high voltage Vpp to the source region of the flash memory, so that the gate insulating film can be prevented from being damaged by the application of the high voltage Vpp. The life of can be extended.

Further, the negative voltage is only transmitted to the selected word line, the driving load thereof is small, and the negative voltage generating circuit having an extremely small driving capability can sufficiently apply the negative voltage to the word line, thus occupying a small area. A negative voltage can be easily generated in the area. As a result, the high voltage Vpp is only transmitted to the word line at the time of writing, and can be generated from the power supply voltage Vcc by using a charge pump circuit having a small occupied area. Obtainable.

In the above-described embodiment, after the erase voltage pulse is applied, the memory cell having a predetermined threshold voltage VT or lower is subjected to post-erase writing to gradually raise the threshold voltage. As a method of narrowing the distribution range of the threshold voltage, a method of gradually decreasing the threshold voltage of the memory cell having a predetermined threshold voltage or more is also possible.
Hereinafter, this method will be described.

FIG. 11 is a diagram showing the overall structure of a flash memory according to another embodiment of the present invention. 11, parts corresponding to those of the flash memory of the embodiment shown in FIG. 1 are designated by the same reference numerals. In FIG. 11, a flash memory is provided corresponding to each bit line B0 and B1, and verify data indicating whether or not the threshold voltage of a memory cell connected to the corresponding bit line is equal to or lower than a predetermined voltage value. Data latch 3 for latching
21 and 322, and a transfer circuit 310 for transmitting the latch data of verify data latches 321 and 322 to corresponding bit lines B0 and B1 in response to control signal CLT.

Transfer circuit 310 is provided between verify data latch 321 and bit line B0, and has an n channel MOS transistor 311 receiving the control signal CLT at its gate, bit line B1 and verify data latch 3.
22 and an n channel MOS transistor 312 receiving a control signal CLT at its gate.

Verify data latches 321 and 32
2 is activated in the erase operation mode (including both the erase voltage applying operation and the erase verify operation) under the control of the write / erase control circuit 25, and its latch data is also controlled by the write / erase control circuit 25. Will be reset.
The other structure is similar to that of the memory shown in FIG. Next, the operation will be described.

The write operation and read operation are similar to those of the flash memory shown in FIG. 1, and description thereof will not be repeated.

Next, the erase operation mode will be described with reference to the operation flow of FIG.

First, in response to the X address signal from address buffer 8, X decoder 48 selects the corresponding word line. Now, the selected word line (specific word line) is set to the word line W0 (step S101).

Then, the source potential generating circuit (not shown in FIG. 11 but provided similarly to the memory of FIG. 1) is operated to set the potentials of source lines S1 and S2 to the ground potential level of 0V ( Step S102).

Then, under the control of the write / erase control circuit 25, the Y decoder 9 generates a column selection signal (column selection signal Y0) indicating the address 0 of the column (step S10).
3).

The word line voltage changing circuit 46 generates and applies a predetermined verify voltage to the X decoder 48. As a result, the verify voltage VT2 is applied to the potential of the selected word line W0 (step S104).

Then, the sense amplifier 15 is activated and the data of the memory cell at address 0 for this column is read.
Write / erase control circuit 25 gives a write pulse to write circuit 20 when the read data is data "0" indicating the written state. After deactivating sense amplifier 15, write pulse circuit 20 generates a signal of "H" in response to the write pulse. The address 0 for the current column is selected, and the "H" signal from the write circuit 20 is transmitted to the Y gate transistor 10 and the bit line B0. In this state, the control signal CLT is set to "H". As a result, the verify data latch 321 is activated under the write / erase control circuit 25 and latches the "H" data supplied from the write circuit 20 (step S10).
5).

On the other hand, write / erase control circuit 25 does not give a write pulse to write circuit 20 when the data in the read memory cell is "1" indicating the erased state. Therefore, in this case, the "L" data in the reset state is latched in the verify data latch.

Thereafter, this operation is performed for each memory cell connected to the selected word line W0 (steps S106 and S107), and then the verify data latches 321 and 322 latch "H" data. Whether or not it is determined (step S10).
8). That is, it is determined whether or not the storage data of the memory cell connected to the selected word line W0 is "1".

When there is at least one memory cell showing data "0" in step S108, source potential generating circuit 24 sets source lines S1 and S2 in a high impedance state (step S109).

Next, with the control signal CLT held at "H", the negative voltage generating circuit 45 and the negative voltage switch 44 are provided.
The selected word line W0 is set to a negative potential via. The setting of the negative voltage of the selected word line W0 is realized by generating the erase signal ERASE in step S110 using the circuit configuration described above.

Threshold voltage is a predetermined threshold voltage VT2
For higher memory cells, the verify data latches 321 and 322 latch the "H" signal.
Therefore, a positive voltage of "H" is applied to the corresponding bit line. A negative voltage is applied on the selected word line. The source line S is in a high impedance state. This allows
A high electric field is generated between the floating gate and the drain, and a tunnel current draws electrons from the floating gate onto the drain region and the bit line.

After the erase voltage pulse is applied once, the process returns to step S102 again, the memory cells on the selected word line W0 are sequentially read, and the corresponding memory cells are erased according to the read data result. It is determined whether the threshold voltage is equal to or lower than a predetermined threshold voltage VT2), and the data indicating the determination result is written into the corresponding verify data latch.

During this operation, the corresponding verify data latch is reset for the memory cell whose data has changed from data “0” to data “1”, and the stored data becomes “L”. This is because write circuit 20 outputs an "L" signal, so that "L" data can be easily stored in the corresponding verify data latch.

The ground potential level is only applied onto the bit line connected to the reset verify data latch. Therefore, even if a negative voltage is applied on the selected word line W0, a sufficiently high electric field for causing a tunnel phenomenon is not generated between the floating gate and the drain region, and the extraction of electrons from the floating gate occurs. Absent. Therefore, in this case, the erase operation is always performed only on the memory cell whose threshold voltage is higher than verify voltage VT2.

Erase operation is performed while performing the verify operation until all the memory cells connected to the selected word line W0 have a threshold voltage equal to or lower than the threshold voltage set by the verify voltage VT2. In this operating method, the erase voltage pulse is not applied to the memory cell whose threshold voltage becomes the verify voltage VT2 or less. Therefore, an extremely narrow threshold voltage distribution can be realized with the maximum value of the threshold voltage of this memory cell being the verify voltage VT2.

FIG. 13 is a diagram showing the distribution of threshold voltages after the erase operation in the flash memory shown in FIG. In FIG. 13, when a specific word line, that is, a word line including a memory cell to be programmed is selected, the threshold voltage distribution of the memory cells connected thereto is given by curves D1 and D2. Curve D
Reference numeral 1 indicates a cell in the written state whose threshold voltage is sufficiently higher than the verify voltage VT2. A curve D2 shows the distribution of memory cells which are already in the erased state and whose threshold voltage is smaller than the verify voltage VT2. In this erase operation mode, the erase operation is performed on the memory cell represented by the curve D1. As a result, a threshold voltage distribution is obtained in which the maximum threshold voltage is the verify voltage VT2 and the threshold voltage is distributed within an extremely narrow range (curve D3). The erase operation flow shown in FIG. 12 can be realized by configuring the write / erase control circuit 25 with a simple microprocessor. Further, the write / erase control circuit 25 may be configured such that, when used in a microcomputer having a built-in flash memory or the like, an external microprocessor thereof executes its function.

In both of the above two embodiments,
Before the data write operation of actually writing the data to the memory cell, the erase operation is performed to narrow the threshold voltage distribution range. However, by using the above configuration, the time required for this erase operation mode can be greatly shortened. The configuration will be described below.

FIG. 14 is a flow chart showing in principle the program operation of the flash memory which is still another embodiment of the present invention. First, the program operation mode in this flash memory will be described with reference to FIG.

First, the program operation mode is activated when both the chip enable signal CE and the write enable signal WE are activated (step S3).
00). In response to this, first according to the address signal,
After selecting the word line to which the memory cell to be programmed is connected, an erase voltage pulse of sufficient magnitude is applied to the memory cell connected to this selected word line (step S302). The erase voltage pulse has a magnitude such that all the selected memory cells are sufficiently erased. Here, the unit to which the erase voltage pulse is applied as a region to which the memory cell to be programmed is connected may be a byte unit, a plurality of byte units, a word line unit, or all. The erase voltage may be simultaneously applied to the memory cells. In the following description, the case where the erase unit is one word line will be described.

When this erase voltage pulse is applied, a negative voltage is applied to the selected word line, a voltage Vcc (about 5 V) is applied to the source line, and the bit line is in the floating state, as in the case of the previous embodiment. To be done.

Then, after the erase voltage pulse is applied, erase verify is performed (step S306). Here, it is explained that the erase voltage pulse has a magnitude such that any memory cell can be sufficiently erased. However, the erase verify operation is performed for confirmation. If the erase voltage pulse has a sufficient magnitude, it need not be performed. In this erase verify operation, after setting the source line to the ground potential, the potential of each selected word line is set to a predetermined verify voltage (a little higher than 0 V), the data of each memory cell is read, and the data "1" is read. It is determined whether or not "" is read. If there is an unerased memory cell, the process returns to step S304 and the erase voltage pulse is applied. After the erase verify operation is completed, data "0" and "1" are simultaneously written according to the data (step S308). Both data "0" writing and data "1" writing are performed by injecting electrons into the floating gate. After writing the data, a write verify operation is performed to determine whether or not the program data is accurately written in each memory cell (step S310). When the same data as the program data has been written in all the memory cells, the writing ends (step S312).

In the operation flow shown in FIG. 14, an erase voltage pulse is applied. Therefore, there is a possibility that overerased memory cells exist. However, the overerased memory cell stores the data "1". Data "0" is written to the over-erased memory cell,
When the write state is set, the write verify operation surely raises the threshold voltage to a value indicating the write state.

On the other hand, when data "1" is written in the over-erased memory cell, the data "1" is written in this embodiment by injecting electrons into the floating gate. Therefore, in this case, the threshold voltage rises, so that the threshold voltage of the overerased memory cell changes from the depletion state to the enhancement state. That is, the electron injection efficiency in writing data “1” is as large as the threshold voltage of the over-erased memory cell is in the enhancement state, but the electron injection efficiency in writing data “0” is large. Is set to a value sufficiently lower than Next, a configuration for adjusting the electron injection efficiency at the time of writing the data "1" and the data "0" will be described.

FIG. 15 is a diagram showing changes in the threshold voltage of the memory cell in the first program operation mode in still another embodiment of the present invention. In this first programming method, an erase voltage pulse is first applied. By applying the erase voltage pulse, the threshold voltage of the selected memory cell differs depending on the respective initial data "0" and "1". However, by applying a sufficient erase voltage pulse, all the threshold voltages of this memory cell are brought into the state representing the erased state. The verify voltage in the erase verify mode is set to a value slightly higher than 0V.

When the erase voltage pulse is applied a plurality of times or a sufficiently large pulse is applied, there is a possibility that an overerased memory cell exists. However, by applying this erase voltage pulse, electrons are extracted from the floating gate to the source region by a tunneling current. When the floating gate becomes in the over-erased state and the positive charge increases, the electric field for causing the tunnel phenomenon becomes small and the tunnel phenomenon becomes difficult to occur, so that the minimum reaching potential of the threshold voltage of the over-erased memory cell is reached. Also has a limit and converges to a certain value. Here, in FIG. 15, the horizontal axis represents time and the vertical axis represents the threshold voltage of the memory cell.

By applying the erase voltage voltage pulse, each threshold voltage of the selected memory is brought into the depletion state, and then data "0" and "1" are written. Data “0”
In writing data, the charge injection efficiency into the floating gate is sufficiently high, and in writing data "1", the charge injection efficiency into the floating gate is reduced. The write pulse is applied until the threshold voltage of the memory cell in the erased state slightly shifts from the depletion state to the enhancement state.

FIG. 16 is a diagram showing voltage application conditions for realizing the threshold voltage change of the memory cell shown in FIG. In FIG. 16, one erase unit is represented as a sector, and one sector is composed of two memory cells as an example. As shown in FIG. 16A, source lines SL1 and SL2 are word lines W, respectively.
0 and W1 are arranged in parallel. In the flash memory shown in FIGS. 1 and 11, the source lines S1 and S1
2 is arranged in parallel with the bit lines B0 and B1.
However, in the structure shown in FIG. 16, source lines SL1 and SL2 are arranged in parallel with word lines W0 and W1 in order to realize rewriting (programming) of data in sector units, and source lines SL1 and SL2 are arranged. Can set its potential in sector units. Next, in the structure shown in FIG. 16, voltage application conditions for writing data "0" into memory cell 16 and writing data "1" into memory cell 18 will be described.

When the erase voltage pulse is applied, the memory cell to be programmed is included in sector SE1.
That is, sector SE1 is the selected sector and sector SE2
Is a non-selected sector.

In the erase operation, bit lines B0 and B1 are set to a floating state (FL), a negative voltage of -9V is applied to word line W0, and word line W1 is set to the ground potential. A voltage of 5V is applied to the source line SL1 and a ground potential level of 0V is applied to the source line SL2.
Is transmitted. The application of the negative voltage to the selected word line W0 is realized by using the configurations of the negative voltage generating circuit, the negative voltage switch circuit, and the X decoder 48 shown in FIGS. In this state, sector SE1
In the memory cells 16 and 18 included in, a high electric field is applied to the control gate and the source region, and electrons in the floating gate are generated by the tunnel phenomenon due to the tunneling phenomenon.
It is pulled upward, and its threshold voltage decreases.

In sector SE2, the potentials of word line W1 and source line SL2 are both at the ground potential level of 0.
V, no change occurs.

At the time of data writing, a write voltage of about 4 V is applied to bit line B0 connected to memory cell 16 in which data "0" is written. At the time of this data writing, the potential of the selected word line W0 is set to a high voltage of 10V. Memory cell 18 in which data "1" is written
A relatively low write voltage of about 2 V is applied to the bit line B1 connected to. In unselected sector SE2, both word line W1 and source line SL2 are at the ground potential level of 0V, and the potential of source line SL1 is also set to 0V.

In this state, as described above with reference to FIG. 3, since the potential of bit line B0 is high, a large amount of hot electrons due to avalanche breakdown are injected into the floating gate, and this memory cell 16 is affected. The threshold voltage rises significantly, while its drain voltage is 2V
In the low memory cell 18, the injection amount of hot electrons due to avalanche breakdown is small, and the threshold voltage thereof is not highly increased. With this configuration, the memory cell 16 stores the data "0" in the written state, and the memory cell 18 stores the data "1" in the erased state. At this time, electrons are being injected into the floating gate and the threshold voltage thereof is rising, so that the memory cell 18 is not in the over-erased state.

In the write verify operation, the data "0" is written again as in the conventional case when the data "0" is written.
Is written. When the data "0" is erroneously written to the data "1", all the memory cells in the selected sector SE1 are erased. Data “1”
Since the injection efficiency of electrons into the electron is small, the increase amount of the threshold voltage is small, and it is considered that the possibility that this state will occur is negligible. When data "0" is written by mistake instead of data "1", data "1" is written after the erase voltage pulse is applied again.

Writing of this data is performed in access units (1 byte unit, 1 word unit). In this case, it may be considered that one memory cell in the illustrated configuration represents one access unit.

FIG. 17 is a diagram showing another programming method. In FIG. 17, the horizontal axis represents time and the vertical axis represents the threshold voltage of the memory cell. In the method shown in FIG. 12, the data write cycle after erasing includes two data write cycles, "write 1" and "write 2". In the first write cycle "write 1", data "1" is first written to the memory cell to be programmed, and the threshold voltages of all memory cells are low. To be in a state.

In the second write cycle "write 2", data "0" is written only to the memory cell in which data "0" is written.

FIG. 18 is a diagram showing conditions of voltage application to the memory cell in the programming method shown in FIG.
FIG. 18 shows a case where data "0" is written in memory cell 16 and data "1" is written in memory cell 18.

First, in the erase cycle, the bit line B
0 and B1 are set to a floating state (FL), word line W0 is set to a negative voltage of -9V, and 5V is applied to source line SL1. The word line W1 and the source line SL2 are at the ground potential level of 0V. In this state, the erase voltage pulse is applied to the memory cells 16 and 18, electrons are extracted from the floating gate by the tunnel current, the threshold voltage thereof is lowered, and the depletion state is set.

Then, data writing is performed. First, in the "write 1" cycle, a voltage of 4V is applied to bit lines B0 and B1, and 5V is applied to word line W0. Word line W1 and source lines SL1 and SL2
Is set to the ground potential of 0V. In this state, the voltage value applied to the control gates of memory cells 16 and 18 is low. Therefore, as shown in FIG. 3, the number of electrons injected into the floating gate is small, the amount of change in the threshold voltage is small, and the threshold voltages of the memory cells 16 and 18 are low. Becomes

Then, a "write 2" cycle for writing data "0" is executed. In this cycle, a voltage of 4V is applied to the bit line B0 and 1 is applied to the selected word line W0.
0V is applied. The voltage of the bit line B is set to 0V. In this state, since a high voltage of 10 V is applied to the control gate of the memory cell 16 and a voltage of 4 V is applied to the drain region, hot electrons generated by avalanche breakdown are injected into the floating gate, and this threshold voltage is applied. The value voltage fluctuates greatly and becomes a threshold voltage indicating a written state, whereby data "0" is written. In the memory cell 18, since the drain region has a potential of 0 V and hot electrons are not generated, the amount of electrons injected into the floating gate does not change. By thus performing the writing of the data “1” and the writing of the data “0” in two stages, it is possible to rewrite the memory cell data at a high speed without the overerased memory cells. it can.

The structure for changing the voltage applied to the selected word line W0 in the "write 1" cycle and the "write 2" cycle can be realized by using the above word line voltage changing circuit. In this case, the word line drive signal having a desired voltage level can be obtained by changing the control signal in the write operation after erase in accordance with the write cycle in the previous embodiment. In the case of the structure shown in FIG. 18, the write voltage may be realized by reducing the write high voltage generated by write circuit 20 by bit line voltage changing circuit 42 (see FIG. 1), or simply by writing. The built-in high voltage may be set to the level of 4V.

FIG. 19 is a diagram showing another programming method. In FIG. 19, the horizontal axis represents time and the vertical axis represents the threshold voltage of the memory cell. In the programming method shown in FIG. 19, after performing the erase operation, the time of the "write 1" cycle for writing the data "1" is shortened, and the "write 2" cycle for writing the subsequent data "0" is shortened. Make the time longer. This is realized by changing the write pulse width according to each data "0" and "1" or the write cycle. In this case, as shown in FIG. 3, the amount of change in the threshold voltage of the memory cell decreases as the write pulse application time decreases.

FIG. 20 is a diagram showing an example of voltage application conditions to the memory cell for realizing the programming method shown in FIG. FIG. 20 also shows voltage application conditions when programming is performed in sector S1 including memory cells 16 and 18 in a memory cell array including memory cells 16 to 19 arranged in 2 rows and 2 columns. Data "0" is written to the memory cell 16, and data "1" is written to the memory cell 18. In this case, the erasing conditions are the same as in the previous embodiment, and a voltage of -9V is applied to the selected word line W0 and 5V is applied to the source line SL1.
This brings the threshold values of the memory cells 16 and 18 into the depletion state.

Then, a "write 1" cycle for writing data "1" is executed. In this state, the bit line B
A voltage of 4V is applied to 0 and B1, and a high voltage of 10V is applied to the word line W0. The source line SL1 is set to the ground potential of 0V. In the non-selected sector SE2, each signal line is set to 0V. In this case, the application time of the write pulse in the "write 1" cycle is extremely short as shown in FIG. Therefore, memory cell 1
In 6 and 18, the amount of electrons injected into the floating gate is small, and each memory cell 16 and 18 is in an enhancement state in which the threshold voltage is low.

Then, data "0" is written.
This is done only for memory cell 16. Therefore, in this case, 4V is applied to the bit line B0 and a high voltage of 10V is applied to the word line W0. The bit line B1 is at ground potential 0V. In this state, electrons are injected into the floating gate as in the case of data "1". The "write 2" cycle has a write pulse application time longer than that in the "write 1" cycle. Therefore, the threshold voltage of memory cell 16 greatly rises, and the threshold voltage is in the enhancement state of a high value indicating the written state.

The structure in which the write pulse is changed to two stages and the write pulse width is changed is realized by using write pulse width changing circuit 43 shown in FIG.

The word line voltage, the bit line voltage and the write pulse width for writing both data "0" and data "1" are changed by writing pulse width changing circuit 43 and bit line shown in FIG. The voltage changing circuit 42 and the word line voltage changing circuit 46 can be used. In this case, as described above, the post-erase write signal PA when performing the post-erase write is used.
Instead of E, a control signal is generated according to each write cycle.

In the operation flow chart shown in FIG. 14, after the erase voltage pulse is applied, the erase verify (step S306) is executed. However, if the condition that the erase voltage pulse brings about a sufficient threshold voltage change is guaranteed, it is not necessary to perform the operation. That is, if the erase voltage pulse is applied and it is guaranteed that the threshold voltage of each memory cell is in the depletion state, the erase verify operation need not be performed.

If there is a large threshold voltage distribution such that an over-erased memory cell exists, instead of such a large erase voltage pulse, the erase verify cycle is performed so that all are in the depletion state. Even if it does not, the maximum value of the threshold voltage is guaranteed by the erase verify operation. Therefore, when the data "1" is written, even if the threshold voltage of the cell at the verify voltage (erase verify voltage) level rises, the threshold voltage fluctuation is sufficiently lower than the threshold voltage indicating the written state. Configured not to bring. That is, in these embodiments, writing is performed after erasing to make the threshold voltage range uniform and, after that, data "0" is written.
This post-erasing write operation is omitted by executing the data "1" write instead of performing the write. Although one word line is shown as the sector indicating the unit to be programmed in the above embodiment, this may be a byte unit or a plurality of byte units.

The flash memory may have a structure in which the memory cell array is divided into a plurality of blocks and each block is accessed.

[0237]

According to the first aspect of the invention, after the erase voltage pulse is applied, the threshold voltage is gradually corrected by performing the write after erase on the memory cell having a predetermined threshold voltage or less. Therefore, variation in threshold voltage is reduced, and erroneous data reading and programming by the overerased memory cell can be prevented.

According to the second aspect of the present invention, since the erase voltage pulse is applied only to the non-erased memory cell having the threshold voltage equal to or higher than the predetermined threshold voltage, the erase memory cell is erased again. The voltage pulse is not applied, the variation in the threshold voltage of the memory cell after erasing is reduced, and the malfunction due to the over-erased memory cell can be prevented.

According to the first and second aspects of the present invention, there is no need to perform pre-erase writing for equalizing the threshold voltages of the memory cells before applying the erase voltage pulse, which is necessary for the erase operation mode. The time can be shortened.

According to the invention described in claim 3, since the data "0" and the data "1" are written after the memory cell is set to the erased state, the erase operation mode and the write operation mode have different sequences. , The sequence control for data programming is simplified, and the time required for programming can be shortened.

According to the invention described in claim 4, since the efficiency of injecting electrons into the floating gate is different between the data "0" write and the data "1" write, erroneous data write is prevented. At the same time, writing is also performed on the over-erased memory cell, so that the threshold voltage of the over-erased memory cell rises and malfunction due to the over-erased memory cell can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a nonvolatile semiconductor memory device which is an embodiment of the present invention.

FIG. 2 is an operation flowchart showing an erase operation mode in the nonvolatile semiconductor memory device which is an embodiment of the present invention.

FIG. 3 is a diagram showing write characteristics in a flash memory cell.

FIG. 4 is a diagram showing distribution of threshold voltages of memory cells after execution of an erase operation in the nonvolatile semiconductor memory device shown in FIG.

5 is a diagram showing a specific configuration of the word line voltage changing circuit shown in FIG.

FIG. 6 is a diagram showing a specific configuration of a bit line voltage changing circuit and a Y decoder shown in FIG.

FIG. 7 is a diagram showing a specific configuration of the write pulse width changing circuit shown in FIG.

8 is a diagram showing a specific configuration of the negative voltage generating circuit shown in FIG.

9 is a diagram showing a specific configuration of a negative voltage switch included in the negative voltage switch circuit shown in FIG.

10 is a diagram showing a specific configuration of the X decoder shown in FIG.

FIG. 11 is a diagram showing an overall configuration of a nonvolatile semiconductor memory device which is another embodiment of the present invention.

12 is a flowchart showing an erase operation mode in the nonvolatile semiconductor memory device shown in FIG.

13 is a diagram showing a distribution of threshold voltages of memory cells after completion of an erase operation in the nonvolatile semiconductor memory device shown in FIG.

FIG. 14 is a flowchart showing an operation of a nonvolatile semiconductor memory device which is still another embodiment of the present invention.

FIG. 15 is a diagram showing a first programming method in the operation flowchart shown in FIG. 14;

16 is a diagram showing a voltage application condition to a memory cell for realizing the first programming method shown in FIG.

FIG. 17 is a diagram showing a second programming method in the flowchart shown in FIG. 14.

18 is a diagram showing voltage application conditions to each memory cell in the programming method shown in FIG.

FIG. 19 is a diagram showing a third programming method in the operation flow shown in FIG. 14.

20 is a diagram showing voltage application conditions to each memory cell in the programming method shown in FIG.

FIG. 21 is a diagram showing a cross-sectional structure of a general flash memory cell.

22 is a diagram showing changes in threshold voltage of the flash memory cell shown in FIG. 21 in a written state and an erased state.

FIG. 23 is a diagram showing an overall configuration of a conventional nonvolatile semiconductor memory device.

FIG. 24 is a diagram showing a specific configuration of the word line voltage changing circuit shown in FIG. 23.

FIG. 25 is a diagram showing a specific configuration of the Vpp switch shown in FIG. 24.

FIG. 26 is a flowchart showing an erase operation mode in a conventional nonvolatile semiconductor memory device.

FIG. 27 is a diagram showing distribution of threshold voltages of memory cells in a conventional nonvolatile semiconductor memory device.

FIG. 28 is a diagram for explaining a problem of an overerased memory cell.

FIG. 29 is a flowchart showing a program mode of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 8 address buffer 9 Y decoder 15 sense amplifier 20 writing circuit 21 data input / output buffer 22 Vpp / Vcc switching circuit 23 word line voltage changing circuit 24 source potential generating circuit 25 writing / erasing control circuit 45 negative voltage generating circuit 46 word line Voltage change circuit 48 X decoder 44 Negative voltage switch circuit 321 Verify data latch 322 Verify data latch 440 Negative voltage switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshikazu Miyawaki 4-chome, Mizuhara, Itami City, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Laboratory (72) Inventor Tomoshi Futani 4-chome, Mizuhara, Itami City, Hyogo Prefecture No. 1 Mitsubishi Electric Corporation LSI Research Center

Claims (4)

[Claims] 1. A memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns, each memory cell storing information in a nonvolatile manner, each of the memory cells having a floating gate type transistor, And according to the accumulated charge amount of the floating gate,
Of the memory cells of the memory cell array are connected to the memory cells of the corresponding rows. A plurality of word lines, a plurality of bit lines arranged corresponding to each column of the memory cell array and connected to memory cells of a corresponding column, the memory cell array in response to a given address signal Memory cell selecting means for selecting a corresponding memory cell, and in the erase operation mode, an erase voltage for setting each of the selected memory cells to the erased state, to the memory cell selected by the memory cell selecting means. Erasing means for applying, deciding means for deciding whether or not the threshold voltage of each memory cell to which the erasing voltage is applied after applying the erasing voltage is below a predetermined value, and For the memory cell whose threshold voltage is determined to be equal to or lower than the predetermined value by another means, the threshold correction voltage is applied until the threshold voltage becomes equal to or higher than the predetermined value and lower than the first threshold voltage. An electrically writable and erasable semiconductor memory device comprising a correction means for applying a voltage. 2. A memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, each having a floating gate type transistor and storing information in a nonvolatile manner according to an amount of charge accumulated in the floating gate. A plurality of word lines which are arranged corresponding to the respective rows of the memory cell array and to which the memory cells of the corresponding rows are respectively connected; and a plurality of word lines which are arranged corresponding to the respective columns of the memory cell array and which correspond to the respective columns. A plurality of bit lines to which the memory cells are connected, a memory cell selecting means for selecting a corresponding memory cell according to a given address signal, and the memory cell selected by the memory cell selecting means has a predetermined threshold voltage. Discriminating means for discriminating whether or not it has the above threshold voltage, provided corresponding to each bit line, and Selected by the memory cell selection means in response to the discrimination data storage means for storing the data indicating the discrimination result of the discrimination means for the memory cell connected to the test line, and the data stored in the discrimination data storage means. A threshold value correcting means for applying an erase voltage to the memory cells in parallel and selectively, thereby setting all the threshold voltages of the selected memory cells to the predetermined threshold voltage or less.
A semiconductor memory device that can be electrically written and erased. 3. A plurality of memory cells arranged in a matrix of rows and columns, each of which is composed of a floating gate type transistor, and which expresses a written state and an erased state according to the amount of charge accumulated in the floating gate. A memory cell array provided, a plurality of word lines arranged corresponding to each row of the memory cell array, to which the memory cells of the corresponding row are connected, arranged corresponding to each column of the memory cell array, respectively A plurality of bit lines to which memory cells of corresponding columns are connected, a memory cell to be programmed is selected in a program operation mode, an erase voltage is applied to the selected memory cell, and thereby, the memory cell to be programmed is to be programmed. Erase means for setting the memory cell to the erase state, and after applying the erase voltage by the erase means, An electrically writable and erasable semiconductor memory device comprising data writing means for simultaneously writing corresponding data to the memory cell to be programmed in accordance with gram data. 4. The data write means is characterized in that a charge injection efficiency to the floating gate required to write data of a first logical value expressing the erased state gives the written state. 4. An electrically writable and erasable semiconductor as claimed in claim 3, including charge injection means having a charge injection efficiency lower than the charge injection efficiency to the floating gate required to write data representing a logic value of 2. Storage device.