JPH0222844A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a large-scale and highly integrated semiconductor integrated circuit by a method wherein a corner at the upper part of an electrode wiring part is removed to about a half of a film thickness and a taper is formed in order to enhance a covering property of an interlayer insulating film formed on it and an upper-layer wiring part. CONSTITUTION:When a two-layer wiring part is formed on 1 field oxide film 12 on a silicon substrate 11, a cross-sectional structure of a first-layer Al electrode wiring part 13 is shaped to be a shape that corners at the upper part of a rectangle have been removed. When a thickness of the first-layer Al electrode wiring part is about 0.6mum, it is good that a thickness (d) of the corners (tapered parts) at the upper part is set at about 0.3mum. An interlayer insulating film 14 is deposited on it, e.g., in about 1.2mum. Various materials such as a silicon nitride film, a silicon oxide film, an SiO2 film, a coating film, a composite film or the like can be utilized as the interlayer insulating film. A second-layer Al electrode wiring film 15 is formed on it. When a two-layer wiring structure is formed in this manner, ups and downs of the interlayer insulating film become comparatively gentle and a thickness of the second-layer aluminum film can be kept uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to the shape of electrode wiring.

[Conventional technology]

In recent years, MO3 type semiconductor integrated circuits have become larger and more integrated, and increasingly high-density wiring is required. As a result, high-density wiring using multilayer wiring is becoming necessary.

As a conventional technique, a wiring structure as shown in FIG. 4 has been used. Although the figure shows an example of two-layer wiring, a first layer of KE electrode wiring 43. A glabellar insulating film 44 is formed thereon, and then a second layer of Af electrode wiring 45 is formed. The Ae electrode wiring is formed twice by forming a photoresist pattern using photolithography on an aluminum film deposited over the entire surface of the substrate by sputtering or the like, and etching the aluminum film using the pattern as a mask. At this time, anisotropic etching is used for etching in order to minimize pattern conversion errors from the designed wiring width. therefore,
The finished aluminum pattern has an etched surface almost perpendicular to the substrate.

[Problem to be solved by the invention]

When a glabellar insulating film is deposited on an electrode wiring pattern etched perpendicularly to a substrate as described above, the steps are generally steep. Therefore, as shown in FIG. 4, when the spacing between the kl electrode wirings in the - layer is narrow, a groove with a steep slope is formed in the glabella insulating film, and when the ke electrode wiring in the second layer crosses the groove, In this case, the film thickness becomes considerably thinner as shown in A in the same figure, and in some cases, the wiring may be cut. -For example, first layer A! ! The thickness of the electrode wiring is 0.
6 μm, the interlayer insulating film is a 1-2 μm nitride film grown by plasma CVD, and the thickness of the second layer kl electrode wiring is 1.1 μm, the −th layer Aff electrode wiring spacing is 2
If it is less than μm, the second layer of the electrode wiring in the groove becomes thin and the yield begins to decrease.

That is, the conventional electrode wiring shape has the drawback that the interlayer film has a steep step difference, making it impossible to increase the density of the wiring pattern.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a mesa-shaped electrode wiring formed by obliquely removing an upper corner of a conductive film having a predetermined width.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention. The figure shows a case where a two-layer wiring is formed on a field oxide film 12 on a silicon substrate 11.
The cross-sectional structure of the electrode wiring 13 is a rectangular shape with the upper corner cut off. A on the first layer! If the thickness of the electrode wiring is about 0.6 μm, the upper corner (part of the taper)
The thickness d is preferably about 0.3 μm, and a glabellar insulating film of about 1.2 μm is deposited thereon. The glabellar insulating film includes a silicon nitride film grown by plasma CVD, a silicon oxynitride film (oxynitride film), an Si02 film grown by sputtering, and a coating film.

Alternatively, various materials such as composite membranes can be used. On top of that is a second layer of AI! Electrode wiring 15 is formed. 2 like this
With the layer wiring structure, the undulations of the glabellar insulating film become relatively gentle, and the uniformity of the second layer aluminum film thickness can be maintained.

FIG. 3 shows an example of a manufacturing method for obtaining the tapered structure of the first layer Ae electrode wiring shown in FIG.

First, as shown in FIG. 3(a), the field oxide film 3
After depositing an aluminum film 33 on the entire surface of the aluminum film 2, photoresist masks 3 and 4 with a predetermined pattern are made using photolithography technology.

Subsequently, as shown in FIG. 3(b), the first layer aluminum film 33 is removed to half its thickness by wet etching using a photoresist mask. Since wet etching is isotropic, a portion of the aluminum under the photoresist mask 34 is also etched. The remaining aluminum is then removed using reactive ion etching using a 7-photoresist mask 34. Since this is an anisotropic etch, the aluminum is etched to the width of the photoresist mask, resulting in a pattern as shown in FIG. 3(c). Thereafter, as shown in FIG. 3(d), the photoresist mask is removed and a glabellar insulating film is grown.

FIG. 2 is a sectional view of a semiconductor chip showing an example of application of the present invention.

The figure shows an example used for the gate electrode of a MOS transistor, with a drain 24 and a source 2 on a silicon substrate 21.
4', a MOS transistor with a gate 23 is formed, and by making the upper corner of the gate electrode drop to about half the film thickness, the step after depositing the glabellar insulating film 25 is extremely gentle. Therefore, the coverage of the wiring layer in the subsequent wiring process is not deteriorated.

〔Effect of the invention〕

As explained above, in the present invention, by tapering the upper corner of the electrode wiring to about half the film thickness, the coverage of the glabella insulating film and the upper layer wiring formed thereon is improved. This has the effect that even if wiring is arranged at a higher density, the yield does not decrease, and a large-scale, highly integrated semiconductor integrated circuit can be realized.

In the above description, the present invention is applied to the first layer electrode wiring of a two-layer wiring system, but it can also be applied to the second layer electrode wiring. It goes without saying that the present invention can be applied to all wiring in a multilayer wiring system.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip showing an application example of the present invention, and FIGS. 3(a) to (d) are one example of the present invention. FIG. 4 is a cross-sectional view of a semiconductor chip arranged in the order of steps for explaining the manufacturing method of the embodiment, and FIG. 4 is a cross-sectional view of a semiconductor chip showing a conventional example. 11.21, 31.41... silicon substrate, 12.3
2.42...Field oxide film, 22...Gate oxide film, 13,15.33,43.45...AI! Electrode wiring, 14, 25, 35. 44... Interlayer insulating film, 23
...Gate, 24.24'...Drain. Source, 34...Photoresist mask.

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a mesa-shaped electrode wiring formed by obliquely removing an upper corner of a conductive film having a predetermined width.