JPH02189926A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02189926A JPH02189926A JP1009216A JP921689A JPH02189926A JP H02189926 A JPH02189926 A JP H02189926A JP 1009216 A JP1009216 A JP 1009216A JP 921689 A JP921689 A JP 921689A JP H02189926 A JPH02189926 A JP H02189926A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- integrated circuit
- semiconductor chip
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000007769 metal material Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 210000001331 nose Anatomy 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にリードの引き
出し構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a lead extraction structure.
従来、半導体集積回路装置を構成する半導体チップに設
けられた電極パッドを外部に電気接続するリード引き出
し構造として、第4図又は第5図に示す構造がとられて
いる。2. Description of the Related Art Conventionally, a structure shown in FIG. 4 or 5 has been used as a lead extraction structure for electrically connecting electrode pads provided on a semiconductor chip constituting a semiconductor integrated circuit device to the outside.
第4図のものは、導電性リードフレーム11に半導体チ
ップ1を搭載し、金属細線12を利用して電極パッド2
を外部リード13に電気接続する構造である。14は封
止用の樹脂である。In the one shown in FIG. 4, a semiconductor chip 1 is mounted on a conductive lead frame 11, and electrode pads 2 are mounted using thin metal wires 12.
It has a structure in which the external lead 13 is electrically connected to the external lead 13. 14 is a sealing resin.
また、第5図のものは、半導体チップ1を回路基板21
上に搭載し、その電極パッド2をインナーリード22を
用いて基板21に設けた回路パターン23に電気接続し
ている。このインナーリード22はテープ状に設けた金
属薄膜で形成している。In addition, in the case of FIG. 5, the semiconductor chip 1 is connected to the circuit board 21.
The electrode pad 2 is electrically connected to a circuit pattern 23 provided on a substrate 21 using an inner lead 22. This inner lead 22 is formed of a tape-shaped metal thin film.
(発明が解決しようとする課題〕
上述した従来のリード引き出し構造のうち、第4図に示
した構造ではリードフレーム11が必要とされるため、
組立に際しては半導体チップ寸法に見合ったリードフレ
ームを個々に準備する必要があり、製造や管理が煩雑な
ものになる。また、リードフレームを固定するためには
樹脂14を用いて封止する必要があり、半導体集積回路
装置全体が大型化するという問題もある。(Problems to be Solved by the Invention) Among the conventional lead extraction structures described above, the structure shown in FIG. 4 requires a lead frame 11;
During assembly, it is necessary to prepare individual lead frames that match the dimensions of the semiconductor chip, making manufacturing and management complicated. Furthermore, in order to fix the lead frame, it is necessary to seal it using the resin 14, which poses a problem of increasing the size of the entire semiconductor integrated circuit device.
また、第5図に示した構造では、テープ状に設けたイン
ナーリードの接続、切断等の作業が極めて困難であり、
かつその取り扱いを慎重に行う必要がある等、作業性が
悪いとい、う問題がある。また、この構造では第4図に
示した構造よりも小型化には有利であるが、インナーリ
ードを横方向に接続するために、半導体集積回路装置の
小型化には限度がある。Furthermore, in the structure shown in FIG. 5, it is extremely difficult to connect and cut the inner leads provided in the form of a tape.
There is also the problem of poor workability, such as the need to handle it carefully. Further, although this structure is more advantageous in terms of size reduction than the structure shown in FIG. 4, there is a limit to the size reduction of the semiconductor integrated circuit device because the inner leads are connected laterally.
本発明は取り扱いを容易にし、かつ小型化を可能にした
半導体集積回路装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that is easy to handle and can be miniaturized.
〔課題を解決するだめの手段]
本発明の半導体チップ11Fsr装置は、半導体チップ
に設けた電極パッドに導電性材からなるリードを立設し
、このリードの先端を露出するように半導体チップを樹
脂で被覆している。[Means for Solving the Problems] In the semiconductor chip 11Fsr device of the present invention, leads made of a conductive material are erected on electrode pads provided on the semiconductor chip, and the semiconductor chip is covered with resin so that the tips of the leads are exposed. It is covered with.
」−述した構成では、リードを利用して外部との電気接
続を行うことができ、リードフレームやインナーリート
を不要にして取り扱いを容易にし、かつ小型化を実現す
る。In the above-described configuration, electrical connections to the outside can be made using leads, and a lead frame or inner lead is not required, making handling easier and downsizing.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
図において、半導体千ノブ1はこれまでと同様に表面に
複数個の電極パッド2を設けているが、これらの電極パ
ッド2上には導電性のり一部3を立設している。このリ
ード3ば、第2図に拡大図示するように、先端を幾分細
(した金属材料をノブ状に形成し、その大径の基部を電
極バンド2に圧着等により接続している。そして、この
リート3の先端のみを露出させるように、半導体チップ
1の全体を樹脂4で被覆している。In the figure, the semiconductor Senknob 1 has a plurality of electrode pads 2 on its surface as before, but a portion 3 of conductive glue is erected on top of these electrode pads 2. As shown in an enlarged view in FIG. 2, this lead 3 is made of a knob-shaped metal material with a somewhat thin tip, and its large diameter base is connected to the electrode band 2 by crimping or the like. , the entire semiconductor chip 1 is covered with a resin 4 so that only the tip of the lead 3 is exposed.
このように構成した半導体集積回路装置を実装する際に
は、第3図に一部を拡大して示すように、実装基板5上
に半導体集積回路装置を伏せて載置し、内部配線6で電
気接続された基板側パッド7にリード3の先端を接触さ
せ、単口1等を用いたりフロー法により接続する。When mounting the semiconductor integrated circuit device configured in this manner, as shown in a partially enlarged view in FIG. The tip of the lead 3 is brought into contact with the electrically connected pad 7 on the board side, and the connection is made using a single port 1 or the like or by a flow method.
したがって、この半導体集積回路装置では、電極パッド
2上に立設したり−ド3を用いて外部との電気接続を行
うため、リードフレームやインナリードは不要となり、
取り扱いを極めて簡単なものにできる。また、樹脂4は
半導体チップ1を最小限の大きさでJ・I止しているた
め、半導体集積回路装置全体の大きさを半導体チップ1
と略同程度に極めて小さいものにできる。Therefore, in this semiconductor integrated circuit device, since the electrical connection with the outside is made by standing on the electrode pad 2 or using the lead 3, a lead frame and an inner lead are not required.
It can be extremely easy to handle. In addition, since the resin 4 holds the semiconductor chip 1 to a minimum size, the size of the entire semiconductor integrated circuit device is reduced by the size of the semiconductor chip 1.
It can be made extremely small to the same extent as .
(発明の効果〕
以上説明したように本発明は、半導体チップの電極パッ
ドにリードを立設するとともに半導体チップを樹脂で被
覆しているので、リードを利用して外部との電気接続を
行うことができ、リードフレー1・やインナーリードを
不要にして半導体集積回路装置の取り扱いを容易にし、
かつその小型化が達成できる効果がある。(Effects of the Invention) As explained above, in the present invention, the leads are erected on the electrode pads of the semiconductor chip and the semiconductor chip is coated with resin, so that electrical connection with the outside can be made using the leads. This eliminates the need for lead frames and inner leads, making it easier to handle semiconductor integrated circuit devices.
Moreover, there is an effect that the miniaturization can be achieved.
第1図は本発明の一実施例の縦断面図、第2図は樹脂封
止前の一部の拡大斜視図、第3図は実装状態の一部拡大
断面図、第4図は従来の半導体集積回路装置の一例の縦
断面図、第5図は従来の半導体集積回路装置の他の例の
一部縦断面図である。
1・・・半導体チップ、2・・・電極パッド、3・・・
リード、4・・・樹脂、5・・・実装基板、6・・・内
部配線、7・・・基+ffl (i1jlパッド、1]
・・・リードフレーム、12金属細線、13・・・外部
リード、I4・・・樹脂、21・・・回路基板、22・
・・インナーリード、23・・・回路パターン。
第2
図
第5
図Fig. 1 is a longitudinal sectional view of one embodiment of the present invention, Fig. 2 is an enlarged perspective view of a part before resin sealing, Fig. 3 is an enlarged sectional view of a part of the mounted state, and Fig. 4 is a conventional A vertical cross-sectional view of an example of a semiconductor integrated circuit device, and FIG. 5 is a partial vertical cross-sectional view of another example of a conventional semiconductor integrated circuit device. 1... Semiconductor chip, 2... Electrode pad, 3...
Lead, 4... Resin, 5... Mounting board, 6... Internal wiring, 7... Group+ffl (i1jl pad, 1)
...Lead frame, 12. Fine metal wire, 13.. External lead, I4.. Resin, 21.. Circuit board, 22.
...Inner lead, 23...Circuit pattern. Figure 2 Figure 5
Claims (1)
るリードを立設し、このリードの先端を露出するように
前記半導体チップを樹脂で被覆したことを特徴とする半
導体集積回路装置。1. A semiconductor integrated circuit device characterized in that a lead made of a conductive material is provided upright on an electrode pad provided on a semiconductor chip, and the semiconductor chip is coated with a resin so that the tip of the lead is exposed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1009216A JPH02189926A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1009216A JPH02189926A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02189926A true JPH02189926A (en) | 1990-07-25 |
Family
ID=11714255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1009216A Pending JPH02189926A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02189926A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994024694A1 (en) * | 1993-04-14 | 1994-10-27 | Amkor Electronics, Inc. | Interconnection of integrated circuit chip and substrate |
US5461197A (en) * | 1991-02-15 | 1995-10-24 | Kabushiki Kaisha Toshiba | Electronic device having a chip with an external bump terminal equal or smaller than a via hole on a board |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US5925934A (en) * | 1995-10-28 | 1999-07-20 | Institute Of Microelectronics | Low cost and highly reliable chip-sized package |
US6204089B1 (en) * | 1999-05-14 | 2001-03-20 | Industrial Technology Research Institute | Method for forming flip chip package utilizing cone shaped bumps |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5787144A (en) * | 1980-11-19 | 1982-05-31 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS5848947A (en) * | 1981-09-18 | 1983-03-23 | Sharp Corp | Manufacture of semiconductor device |
JPS62147735A (en) * | 1985-12-23 | 1987-07-01 | Matsushita Electric Works Ltd | Manufacture of flip chip |
JPS631341U (en) * | 1986-06-20 | 1988-01-07 | ||
JPS644051A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Formation of bump of hand drum shape |
-
1989
- 1989-01-18 JP JP1009216A patent/JPH02189926A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5787144A (en) * | 1980-11-19 | 1982-05-31 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS5848947A (en) * | 1981-09-18 | 1983-03-23 | Sharp Corp | Manufacture of semiconductor device |
JPS62147735A (en) * | 1985-12-23 | 1987-07-01 | Matsushita Electric Works Ltd | Manufacture of flip chip |
JPS631341U (en) * | 1986-06-20 | 1988-01-07 | ||
JPS644051A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Formation of bump of hand drum shape |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5461197A (en) * | 1991-02-15 | 1995-10-24 | Kabushiki Kaisha Toshiba | Electronic device having a chip with an external bump terminal equal or smaller than a via hole on a board |
WO1994024694A1 (en) * | 1993-04-14 | 1994-10-27 | Amkor Electronics, Inc. | Interconnection of integrated circuit chip and substrate |
US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
US5925934A (en) * | 1995-10-28 | 1999-07-20 | Institute Of Microelectronics | Low cost and highly reliable chip-sized package |
US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
US6204089B1 (en) * | 1999-05-14 | 2001-03-20 | Industrial Technology Research Institute | Method for forming flip chip package utilizing cone shaped bumps |
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