JPH02187063A - Mos integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit operating with a higher voltage by a method wherein the thickness of the gate oxide film of a MOS-FET in the circuit operating with a higher voltage is larger than the thickness of the gate oxide film of a MOS-FET in a circuit operating with a lower voltage. CONSTITUTION:MOS-FET circuits operating with different voltages are provided in a same semiconductor chip to form an IC device. The thickness of the gate oxide film 8 of the MOS-FFT in the circuit 30 operating with a higher voltage is larger than the thickness of the gate oxide film 7 of the MOS-FET in the circuit 20 operating with a lower voltage. With this constitution, the FET can have a high gate breakdown strength with which the FET can withstand an electric source voltage. As the threshold of the gate is elevated when the gate oxide film thickness is increased, if a low threshold is required, it is obtained by selecting a channel length and a channel width or by adjusting the impurity concentration of a substrate region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS integrated circuit device in which MOS transistor circuits that operate under different power supply voltages are built into the same semiconductor chip.

[Conventional technology]

Traditionally, MO9 integrated circuits have been most widely used for applications that handle digital signals, but most of the circuits built into them, including 0M03 circuits, operate under a single low-voltage power supply of about 5V. It is configured,
Both the input signal and the output signal are all low voltage signals, and if the output signal needs to drive a load that operates under high voltage, the drive circuit for that purpose is a transistor or the like that operates in response to the low voltage signal. It is often composed of individual high-voltage elements.

However, depending on the application, the number of loads that must be driven by the output signal of the MOS integrated circuit device is very large, and if the drive circuit for each load was constructed from individual elements, the drive system would become too large. There are cases. An example of this is a drive circuit for a relay panel with a large number of input points or a display panel with a large number of pixels.In order to reduce the size of the drive circuit, a drive circuit for a load that operates on a high voltage power supply is connected to the MO3 direction 7. It has come to be possible to integrate this into the same semiconductor chip along with an MO3 circuit for digital signals that operates on a low voltage power supply.

In the high-voltage circuit section of a MOS integrated circuit device that operates with such multiple power supply voltages, it is inevitable that the MOS transistors used therefor will be considerably larger than those for the low-voltage circuit section. Since the gate withstand voltage value is not very high, the circuit configuration requires some ingenuity.

This example will be explained below with reference to FIG.

On the left side of FIG. 3 is shown a flip-flop that operates in response to a low power supply voltage Vd as a representative of the low voltage circuit 20, and its Q output and its complementary signal are used as the output signals of the low voltage circuit 20 on the right side. It is assumed that the signal is input to a high voltage circuit 40 that operates in response to a high power supply voltage V. High voltage circuit 40
The output stage of consists of a pair of p-channel MO3 transistor 41 and n-channel MO3 transistor 42 connected in series between a pair of power supply potential points V and E, and an output terminal To for driving a load is connected from the interconnection point of both. is derived. A series circuit of two Zener diodes 43, 45 and a resistor 44 on the left side is for gate protection of the output MO3 transistor. This is to prevent a gate voltage higher than that from being applied.

MOS transistors 46 and 47 connected in parallel to Zener diodes 43 and 45 respectively turn on and off the output transistors 41 and 4.
2, the n-channel type transistor 47 is connected to the low voltage circuit 2.
0 output signal directly, but the p-channel type transistor 46 is connected to another n-channel MO3 transistor 48.
A complementary signal of the output signal of the low voltage circuit 20 is received through a level shift circuit consisting of a series circuit of three resistors 49, 50 and 51.

When the output signal of the low voltage circuit 20 is -, the transistor 47 receiving it is off, and therefore the output transistor 42
is turned on, the transistor 48 receiving the complementary signal h of the output signal is turned on, and in response, the transistor 46 is also turned on, and the output transistor 41 is therefore turned off, so the output terminal is placed at the reference potential E. . When the output signal of the low voltage circuit 20 is b, the on/off state of each transistor is reversed to the above 2, and the output terminal To is placed at the power supply potential V.

[Problem to be solved by the invention]

In the above example, MOS transistors 41 and 42 are protected by Zener diodes 43 and 45, respectively, MOS transistor 46 is protected by a resistor 49 from applying a large voltage to their gates, and MOS transistors 47 and 48 are originally protected from low voltage. Since only voltage signals are received, the gates of all MOS transistors in the high voltage circuit 40 are safely protected.
As can be clearly seen from the figure, there is a problem in that the configuration of the high voltage circuit becomes quite complicated simply because the gate of the MOS transistor is protected. Furthermore, even with the circuit configuration shown in FIG. 3, the gate protection is not necessarily perfect, and there is a particular weakness in the gate of the output MOS transistor, and in reality, the allowable power supply voltage for the high voltage circuit 20 is limited to below a certain limit. It will be done.

An object of the present invention is to obtain an MO5 integrated circuit device that does not require complicating the configuration of a high voltage circuit section and operates with multiple power supply voltages without any particular restrictions on the power supply voltages used.

[Means to solve the problem]

This purpose, according to the present invention, is to provide an MO5 integrated circuit device that operates under a high power supply voltage, in which MOS transistor circuits that operate under different power supply voltages are built into the same semiconductor chip as described at the beginning. This is achieved by making the thickness of the gate oxide film of the MO'3 transistor in the circuit that operates under a low power supply voltage larger than the thickness of the gate oxide film of the MOS transistor in the circuit that operates under a low power supply voltage.

MO in a circuit that operates under high power supply voltage in the above configuration
Regardless of whether the S transistor is connected to the power supply potential point side or the reference potential point side in the circuit, it is advantageous to increase the gate oxide film thickness in order to simplify the circuit configuration. It is. In order to make the gate oxide film thickness different between the high-voltage circuit section and the low-voltage circuit section in this way, the easiest way is to apply oxide films of different thicknesses separately, or by using the so-called double oxidation method. It is also possible to deposit a thin oxide film and then add more oxide to areas where a thicker film is required.

Note that as the thickness of the gate oxide film increases, the gate threshold value increases, so a MOS transistor that requires a low threshold value is provided with a desired threshold value by selecting its channel length and channel width. However, the area of the channel portion may become extremely large due to the selection of the channel shape, and in this case, it is advantageous to select or adjust the impurity concentration of the substrate such as the well of the MOS transistor. be.

That is, a MOS transistor with a large gate oxide film thickness can have a desired low gate threshold value by lowering the impurity concentration of its substrate. To adjust the impurity concentration of such a substrate,
Means such as a so-called channel doping method can be used as appropriate.

In addition, in setting such a gate threshold value, it is necessary to set the gate threshold value of at least the MOS transistor connected to the reference potential point side in a circuit that operates under a high power supply voltage to be equal to or lower than the value of the low power supply voltage. It is.

(Function) As can be seen from the previous example in Figure 3, it takes a considerable amount of effort to protect the gate of a MOS transistor using a circuit, and in practice, it is difficult to protect the gate of a MOS transistor from a transient circuit phenomenon or an unexpected path. Since this method has a limit as it may cause the circuit to wrap around the circuit groove, the present invention improves the withstand voltage value of the gate of the MOS transistor itself by selecting the thickness of the gate oxide film as described in the above structure, and the circuit trench Measures are taken to simplify the base and relax constraints on circuit voltage.

The withstand voltage value of the silicon oxide used in the gate oxide film is of course a function of its thickness, and ideally it should be proportional to the thickness, but the actual withstand voltage value is different from its essential withstand voltage value. is nearly an order of magnitude lower, and is not necessarily proportional to the film thickness.This is thought to be due to factors such as defects in the gate oxide film, impurity content, and internal charge distribution.
In the thickness range of about 1000 or less, which is commonly used in low voltage MOS transistors, the withstand voltage value is significantly improved as the film thickness increases.

The present invention focuses on this point and solves the problem by increasing the gate oxide film thickness within a practical range, thereby improving the gate withstand voltage value by one order of magnitude or more. If a clean gate oxide film is used, in a MOS transistor for a low voltage circuit of about 5V, the gate oxide film will have a
It is sufficient to have a film thickness of 00 to 500 people, and this is 2
000 to about 3000, it is possible to manufacture an MO3 transistor for high voltage circuits with a withstand voltage value improved by about one order of magnitude. In addition, if the film thickness is around this level, the shape and dimensions of the channel should be selected within a practical range.
If the film thickness is to be increased beyond this value, the impurity concentration of the substrate can be further controlled as described above to give this high-voltage MOS transistor a practically low gate threshold. be able to.

According to this configuration of the present invention, a circuit that operates under a power supply voltage of up to several tens of volts can be easily and economically constructed, and the limit of the usable power supply voltage can be extended to 100 to 200 volts or more. .

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a partially enlarged cross-sectional view illustrating an MO3 integrated circuit device according to the present invention, and the left side of the figure shows MOS transistors for the low voltage circuit 20, and the right side shows the MOS transistors for the high voltage circuit 30. In this example, both are of n-channel type.

In FIG. 1, a semiconductor substrate 1 as well as a low voltage circuit 2 are shown.
Common to both the 0 and high voltage circuits 30, p-type is used as usual, and a strong n-type buried layer 2 is first diffused from the surface separately for both circuits. , an n-type high-strength epitaxial layer 3 is grown to a predetermined thickness depending on the power supply voltage used in the high-voltage circuit 30. Next, a junction separation layer 4 is grown from the surface of this epitaxial layer 3 to the substrate 1. The epitaxial layer 3 is junction-separated into separate semiconductor N regions for low voltage circuit 20 and high voltage circuit 30 by deep diffusion. Note that the steps up to this point are of course common to the low voltage circuit 20 and the high voltage circuit 30.

In the illustrated example, the MOS transistors are all n-channel type, so first, p-type wells 5 and 6 are diffused from the surface of the epitaxial layer 3 as substrate regions for the MOS transistors of the low voltage circuit 20 and the high voltage circuit 3o, respectively. do. The well 6 for the MOS transistor of the high voltage circuit j120 may have the same impurity concentration as the well 5 for the low voltage circuit 3° when the power supply voltage used is about several tens of V, but the diffusion may be slightly deeper if necessary. be considered a wife.

If the power supply voltage of the high voltage circuit 20 is higher than this, in order to facilitate control of the gate threshold, the impurity concentration may be increased in advance during diffusion of the well 5, or ion implantation may be used after the diffusion. It is desirable to dope the channel very shallowly with p-type impurities on the surface of the MOS transistor.In the case of a p-channel MOS transistor,
In order to increase the impurity concentration of the n-type epitaxial layer 3 serving as the substrate region, n-type impurities are shallowly added to the surface of the epitaxial layer 3 by channel doping.

Next, gate oxide films 7 and 8 are attached for the 20 low voltage circuits and the high voltage circuit 30, respectively.For example, gate oxide for low voltage! The thickness of 117 is about 500 or less.When the power supply voltage is several tens of V, the thickness of gate oxidation WA8 for high voltage is 3.
More than 000 people attended each event. As mentioned above, these gate oxide 15N? It is easiest to attach 8 and 8 separately, and a double oxidation method can be used as necessary.

Gate 9 is then formed over gate oxides 117 and 8, such as polycrystalline silicon, as is customary.

The pattern of this gate 9 is formed by, for example, 3 photo processes.
1! In the case of the a rule, the channel length is 34 for low voltage circuits.
+ For high voltage circuits with a power supply voltage of several tens of microns, the channel length should be 4 to 54 mm so that the channel width is 4 to 6 -. Set the channel width to be a little over 50. In this case, the gate threshold of the MOS transistor is 0.0 on the low voltage side.
6~IV, l~ on the high voltage side! , 5v is obtained. Note that the channel width for the above high voltage circuit can be appropriately reduced by lowering the impurity concentration of the well 6.

The source/drain layer 10 on the low voltage circuit 20 side and the source/drain N11 on the high voltage circuit 30 side are both made of n-type in this example by a self-aligned ion implantation method using the gate 9 as a mask as usual. It will be spread. However, for the source/drain layer 11 on the high voltage circuit 30 side, it is desirable to adopt a so-called offset gate structure or a double diffusion structure depending on the power supply voltage value. A connecting film 13 is provided in each open window, and the source terminals S,
A gate terminal G and a drain terminal are provided.

FIG. 2 shows an example in which a circuit having the same function as that in FIG. 3 is configured using the MOS transistors configured as described above. Although they are composed of MOS transistors with thin oxide films, thick gate oxide films are used for all of the MOS transistors 31 to 33 in the high voltage circuit 30 shown surrounded by a dashed line in the figure, and the power supply voltage V Corresponding gate withstand voltage values are given.

A pair of 2-channel MOs that are the output stage in the high voltage circuit 30
3 transistor 31 and n-channel MO3 transistor 3
2, of course, has the same circuit configuration as that in FIG.
A complementary signal of the output signal from the low voltage circuit 20 is directly given to the gate of the p-channel MO3 on the power supply potential point V side.
The output signal of the low voltage circuit 20 is connected to the gate of the transistor by an n-channel MO3 transistor 33 and a resistor 34.35.
It is applied via a level shift circuit consisting of. As can be easily seen, the MOS transistors 31 and 33 perform the same on/off operation, and the resistor 35 can be omitted by setting the on-resistance of the MOS transistor 33 to be high.

As can be seen from the comparison of FIG. 2 with FIG. 3, in the high voltage circuit 30, each MO3 transistor 31 to 33 has a high gate withstand voltage value, and there is no need to consider gate protection.
According to the present invention, the configuration can be much simpler than the conventional one.

2, in the MO3 integrated circuit device implementing the present invention, the chip area required for building the high voltage circuit side can be significantly reduced. As can be seen from the example in Figure 2,
As for the p-channel MO3 transistor connected to the power supply potential side, its gate is usually controlled via a level shift circuit, so if the gate control voltage generated there is set in advance to a large value, the gate There is no need to make the threshold too small,
Utilizing this, it is possible to further save the chip area required for manufacturing a p-channel MO3 transistor.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various embodiments. The example circuit of the MO3 integrated circuit device is of course merely an example, and the optimum configuration should be adopted depending on the purpose and use. The same applies to the thickness of the gate oxide film and the size of the channel part, and in reality M
It is selected or set as appropriate depending on the conditions and accuracy of the process used to manufacture the O3 integrated circuit device.

〔Effect of the invention〕

As described above, in the present invention, for an MO3 integrated circuit device in which MOS transistor circuits that operate under different power supply voltages are built in the same semiconductor chip, the gate of the MOS transistor in the circuit that operates under a high power supply voltage is MOS in circuits that operate under low power supply voltage
Since the thickness of the gate oxide film of the transistor is larger than that of the transistor, the MOS transistor for high-voltage circuits has a gate withstand voltage value high enough to withstand the power supply voltage, and the configuration of high-voltage circuits can be made smaller than before. can also be greatly simplified.

When implementing the present invention, the shape and dimensions of the gate are appropriately selected depending on the thickness of the gate oxide film, and M
A practical gate threshold can be given to the O3 transistor, and when the power supply voltage is high, by further controlling the impurity concentration in the substrate region,
100% reduction in conventional restrictions on power supply voltage for high-voltage circuits
It can be relaxed to ~200 V or more.

The present invention is particularly suitable for applications such as the above-mentioned display panel drive circuit where a large number of loads (and high voltage circuits) must be directly driven from an MO3 integrated circuit device. The configuration of the voltage circuit can be simplified to improve its economic efficiency, and the power supply voltage can be raised to a high voltage, thereby achieving a remarkable effect of expanding the applicable range of the MO3 integrated circuit device.

[Brief explanation of the drawing]

1 and 2 relate to the present invention; FIG. 1 is a partially enlarged sectional view illustrating an MO3 integrated circuit device according to the present invention, and FIG. 2 is a circuit diagram of an example of its application. FIG. 3 is a circuit diagram of an application example of a conventional MO3 integrated circuit device.

Claims (1)

[Claims] MO operating under different power supply voltages within the same semiconductor chip
In a device that incorporates an S transistor circuit, the thickness of the gate oxide film of a MOS transistor in a circuit that operates under a high power supply voltage is made greater than the thickness of the gate oxide film of a MOS transistor in a circuit that operates under a low power supply voltage. A MOS integrated circuit device characterized by being enlarged.