JPH02159057A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve retaining characteristics of information by forming a charge accumulation region at the inside wall within groove along the outer periphery of a cell region and by forming a MOS transistor surrounding a bit wire and a contact hole in ring shape. CONSTITUTION:A groove 9 is formed at the periphery on a substrate 1 so that a transistor region 2 may be in island shape and then a P<+> high concentration diffusion layer 14 is formed on the side surface part and bottom surface part and an N<+> high concentration diffusion layer 12 is formed only at the side surface part of the groove 9. The N<+> diffusion layer 12 becomes a change accumulation region and the P<+> diffusion layer 14 plays a role of separating elements among memory cells. Then, a dielectric film 11 is formed on the side surface part and bottom surface part of the groove 9 and then an N-type polysilicon 10 which becomes the capacitor electrode is filled into the groove 9. Then, after forming a gate oxide film 4 at a transistor region 2, a polysilicon electrode 3 which becomes the gate electrode is formed. After accumulating an insulation film 8, a hole 13 for contact of a bit wire 7 is formed and a drain region 5 is formed by implanting N-type impurities.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a dynamic random access memory (DRAM).

Conventional technology As a memory cell for highly integrated semiconductor memory devices, the so-called "one-transistor type" memory cell, which is composed of one transistor and one capacitor, is widely used because it has few components and the cell area can be easily miniaturized. It is used.

In recent years, higher integration and larger capacity have been pursued in semiconductor memory devices, and there is a demand for miniaturization of elements. In a one-transistor type memory cell, reduction in memory cell capacity must be avoided as much as possible in order to maintain ease of information determination. For this reason, various efforts have been made to increase the capacity of memory cells without increasing their occupied area.

For example, at the International Solid State Circuits Conference a (I) held in 1988,
SSCC) (7) 7 SCC (Surrounding Hi-
A memory cell with a capacity cell structure has been proposed. FIG. 3 shows a memory cell having an SCC structure, in which FIG. 3(a) is a plan view and FIG. 3(b) is a sectional view taken along line cc'. In the SCC, the n+ diffusion layer 12 on the side wall of the groove 9 formed on the surface of the p-type Si substrate 1 so as to surround each cell region 2 is used as a charge storage region. Inside the groove 9 is a plate electrode 10 via a dielectric film 11.
is filled to form a capacitor. The switching transistor is formed in the upper part of the cell region 2, and the source region 6 and the charge storage region are connected to form a one-transistor type memory cell. 3 is a word line, and 7 is a bit line.

Also, the International Conference on Electronic Devices (I) was held in 1984.
I V E C (Isolation-merge) shown in abstract p240-243 of
d Vertical Capacitor cell
) memory cell structure has been proposed. Figure 4 shows IV
FIG. 4(a) is a plan view of the EC cell, and FIG. 4(b) is a sectional view taken along line D-D. IVEC
Here, a charge storage region 12 is formed on the side wall of a groove 9 formed on the surface of a p-type Si substrate 1 so as to surround each cell region 2, with an insulating film 15 interposed therebetween. The groove 9 is filled with a plate electrode 10 via a dielectric film 11 to form a capacitive portion. A switching transistor is formed above the cell region 2 to constitute a memory cell. 3 is a word line, and 7 is a bit line.

Problems to be Solved by the Invention However, in the memory cell of the above-mentioned SCC structure, there is a leakage current between the charge storage region of the memory cell and the drain region of the switching transistor, and a leakage current between the source and drain of the switching transistor. ,
There is a problem in that this tends to occur along the separation region and deteriorates the retention characteristics of information stored in the capacitor.

In addition, in the memory cell of the above IVEC structure, when the charge storage region is at a high potential, the semiconductor interface on the side surface of the groove tends to be inverted, causing a leakage current between the source and drain of the switching transistor due to a so-called parasitic MO8) transistor. , there was a problem of deteriorating information retention characteristics.

Means for Solving the Problems The semiconductor storage device of the present invention includes a memory capacitor and a MOS
A trench is formed around the memory cell including the transistor so that it remains in an island shape, a charge storage region is formed on the inner wall of the trench along the outer periphery of the cell region, and a contact hole with the bit line is formed for the MOS transistor. It is formed in a ring shape so as to surround it.

Operation With this configuration, no leakage current occurs because there is no separation region by an insulating film between the drain region of the switching transistor connected to the bit line and the charge storage region or source region.

Example Hereinafter, the present invention will be explained in detail using the drawings.

A first embodiment of the invention is shown in FIG. FIG. 1(a) is a plan view, and FIG. 1(b) is a sectional view taken along the line 1-A'. A groove 9 is formed on the p-type Si substrate 1 by anisotropic etching around the transistor region 2 so as to form an island shape. A p+ high concentration diffusion layer 1 is formed on the side and bottom portions of this groove 9.
4, and an n+ high concentration diffusion layer 12 is formed only on the side surfaces of the groove 9. The n+ diffusion layer 12 serves as a charge storage region. In addition, the p+ diffusion layer 14 is formed deeper than the n+ diffusion layer 12, and plays the role of increasing capacitor capacity and suppressing leakage current, and especially at the bottom part, plays the role of element isolation between memory cells. Next, dielectric film 11 is formed on the side and bottom parts of trench 9, and n-type polysilicon 10, which will become a capacitor electrode, is filled in trench 9. In this way, n-type polysilicon 10 is formed into a cell. A capacitor is formed in the trench 9 as a plate electrode, and the bottom of the trench 9 serves as an element isolation region.Next, after forming a gate oxide film 4 in the transistor region 2, the gate electrode A polysilicon electrode 3 is formed as follows.After depositing an insulating film 8,
A hole 13 for a bit line contact is formed. After forming the drain region 5 of the transistor of the memory cell by implanting n-type impurities, an S + 02 film is formed on the side wall of the hole 13, and aluminum wiring is performed to form the bit line 7. In the manner described above, a memory cell having the structure shown in FIG. 1 is obtained.

As described above, according to this embodiment, between the drain region 5 of the transistor and the charge storage region 12, the SCC of the conventional example is
Since there is no isolation region formed by an insulating film like in a memory cell structure, no leakage current occurs.

Next, a second embodiment of the present invention will be described.

FIG. 2 shows a second embodiment, where FIG. 2(a) is a plan view and FIG. 2(b) is a sectional view taken along line BB'. A trench 9 is formed on the p-type Si substrate 1 by anisotropic etching around the transistor region 2 so as to form an island shape, and an insulating film 15 is formed on the side and bottom portions of the trench 9. Next, n+ polysilicon 12, which will become a charge storage region, is formed in trench 9 so as to connect to transistor region 2. Next, a dielectric film 11 is formed on the side surface of the charge storage region 12, and the groove 9 is filled with n+ polysilicon 10 which will become a plate electrode. Thereafter, a memory cell having the structure shown in FIG. 2 is obtained in the same manner as in the first embodiment.

In this embodiment as well, since there is no separation region formed by an insulating film between the drain region 5 and the charge storage region 12 of the transistor, parasitic MO as in the conventional IVEC cell
8) No transistor is formed and no leakage current occurs.

As described in detail, according to the semiconductor memory device of the present invention, there is no separation region by an insulating film between the drain region of a switching transistor connected to a bit line and the charge storage region or source region. Therefore, a memory cell with extremely good retention characteristics can be obtained without causing leakage current.

[Brief explanation of the drawing]

1(a) and 1(b) are respectively a plan view and a sectional structural view of a semiconductor memory device according to a first embodiment of the present invention, and FIG.
a) and (b) are a plan view and a cross-sectional structure diagram of the second embodiment, respectively; FIGS. 3A and 3B are a plan view and a cross-sectional structure diagram of a conventional semiconductor memory device, respectively; Diagram (a)
, (b) are a plan view and a sectional structural view of other conventional devices, respectively. p-type Si substrate, 2...transistor region, 3.
...Word line, 4...Gate oxide film, 5
...Drain region, 6...Source region, 7...Bit line, 8...Insulating film, 9...
...Groove, 10...Plate electrode, 11.
...Dielectric film, 12...Charge storage region,
13...Bit line contact window, 14...
...p+ diffusion layer, 15...insulating film. Name of agent: Patent attorney Shigetaka Awano

Claims (2)

[Claims] (1) Includes a memory capacitor and a MOS transistor,
A trench is formed in the substrate around the memory cell so that the memory cell remains in the form of an island, and the memory capacitor is connected to the MO
It is composed of a diffusion layer electrode formed on the side surface of the groove so as to be electrically connected to the source region of the S transistor, a dielectric film formed on the side surface of the groove, and a conductive electrode filled in the groove. . A semiconductor memory device, wherein the MOS transistor is formed in a ring shape so as to surround a contact hole with a bit line. (2) includes a memory capacitor and a MOS transistor;
A groove is formed in the substrate around the memory cell so that the memory cell remains in the form of an island, and the memory capacitor has one electrode as a conductive electrode formed on the side surface of the groove, and the other electrode as a conductive electrode formed in the groove. It is configured to be a conductive electrode filled with
A semiconductor memory device characterized in that the MOS transistor is formed in a ring shape so as to surround a contact hole with a bit line.