JPS62193168A - One-transistor type dram device - Google Patents

Abstract

PURPOSE:To contrive the exceeding reduction of soft error probability and leakage current by composing the device out of a fourth electrode layer which is formed on an insulating film for dielectric of an upper capacitor and has an electrical connection part with a second electrode layer and inserting the fourth electrode layer among third electrode layers of adjacent memory cells in a trench. CONSTITUTION:A lower plate electrode 6 using a polysilicon for forming a lower cell plate and an upper plate electrode 11 using a polysilicon for forming an upper cell plate are electrically connected in the outside of a memory cell. A capacitor is formed between a cell plate of the lower plate electrode 6 and a conductive electrode 9 for forming a source of the memory cell. Accordingly, this semiconductor memory device can not only have an exceeding large storage capacity, but reduce soft error probability and leakage current drastically. Also, the formation of an insulating thin film becomes easy in the process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a one-transistor type DRAM device, and particularly to a high-density and highly reliable one-transistor type DRAM device.

2. Description of the Related Art In recent years, semiconductor memory devices have become more densely packed, especially DRA.
The increase in the integration and capacity of M is remarkable. RAM like this
The development of the chip is largely due to the development of high-density technology for memory cells, which occupy more than half the area of the chip. Currently, DRAMs with various three-dimensional structures are being developed for the purpose of further increasing density.
Cells have been proposed. Conventionally, this type of 3D structure D
RAM Technical Papers) 1!244
-247) 0 In Figure 2, 1 is the drain forming the bit line, 2 is the gate oxide film of the MOS transistor forming the transfer gate for signal readout, and 3
4 is a source diffusion part of a memory cell; 5 is an insulating thin film that is a capacitor of a memory cell; 6 is a cell plate made of polysilicon, for example; 1 is a plate electrode, a thick film for cell isolation, 8 a substrate, and 10 an interlayer insulating film. This is an example of a memory cell structure called a trench structure, and is an FCC cell (Folded Co
It is called pacitor Ce1l).

Since the trench is formed in the depth direction of the substrate 8, by controlling the depth of the trench, the storage capacitance can be sufficiently secured to a value required for a memory cell (generally said to be 50 fF or more). Further, in the FCC structure, the trench is used not only as a signal storage capacitor but also for element isolation, and by making the intercell isolation thick film 7 thick, the intercell leakage current can be kept sufficiently low.

Another example of a three-dimensional structure cell is a stacked structure, which has a structure as shown in Figure 3 (for example, 1986.6.30 Nikkei Electronics p.209-
231). In FIG. 3, 1 is a drain that forms a bit line, 2 is a gate oxide film of a MOS transistor that is a transfer gate for signal readout, 3 is a gate electrode made of polysilicon, for example, that forms a word line, 4 6 is an insulating film forming a capacitor of the memory cell; 6 is a plate electrode made of polysilicon, for example, forming a cell plate; 7 is a thick film for isolation between cells; 8 is a substrate; 9 1 is a conductive electrode constituting the source portion of the memory cell, and 10 is an interlayer insulating film. A capacitor is formed between the cell plate 6 and the conductive electrode forming the source part of the memory cell 9, and the cell capacitance can be increased by using the part on the word line and the side surface of the electrode 9 as a capacitor. . α-ray soft errors are caused by α particles passing through a depletion layer formed in the pn junction region below the source of the memory cell. The area is much smaller than that of the conventional planar type or the trench structure memory cell described above, making it extremely resistant to α-ray soft errors.

Problems to be Solved by the Invention In such conventional configurations, there are the following problems with each of the trench structure and stacked structure including FCC.

First, in trench-structured memory cells, the required storage capacity can be obtained by selecting the trench to a predetermined depth, but since the trench is buried deep in the substrate, depletion occurs in the substrate under the plate electrode. The layers become larger, and the α-ray torrent error rate is more than an order of magnitude worse than that of a planar cell with the same capacity. Therefore, in order to lower the a-line soft error rate, it is necessary to increase the area of the capacitor cell on the plane, which is disadvantageous for high integration.

On the other hand, by implanting ions into the sides or bottom of the trench, a so-called Hi-C cell structure can be formed and the growth of the depletion layer can be suppressed, but as a result of high-concentration implantation, leakage current increases and the process This poses a practical problem as it complicates the process.

It is also necessary to form a thin insulating film along the trench surface, but depending on the orientation of the trench surface with respect to the crystal axis,
The oxidation rate of the insulating film (for example, S 102 ) is different, making it difficult to grow an insulating film with a uniform thickness, which causes variations and decreases in dielectric strength voltage, which poses a practical problem.

Furthermore, in order to achieve both an increase in the dielectric constant and an increase in dielectric strength of the insulating film constituting the capacitor of the memory cell, it is necessary to use a multilayer structure of Si3N4 and S102 for the insulating film. of single crystal silicon,
The influence of stress on Si3N4 occurs, defects etc. are formed in the substrate silicon, and leakage current increases, which poses a practical problem.

It is clear that these problems will become even more serious obstacles when further promoting higher integration and larger capacity.

On the other hand, in the stacked structure, the p
The area of the n-junction is small, so it has the advantage of being resistant to soft errors. In addition, the element isolation area can be larger than that of a planar cell, making it easier to suppress leakage between elements.However, due to its structure, there is a limit to the increase in memory cell capacity, and as elements become smaller and more integrated, It is inevitable that the memory cell capacity will be insufficient.

The present invention solves these problems by realizing an increase in storage capacity, allowing for higher integration and larger capacity, greatly reducing the damping error rate and leakage current, and reducing the insulation constituting the capacitor. It is an object of the present invention to provide a semiconductor memory device having a memory cell structure in which a film can be easily formed. a trench formed in a predetermined region of a semiconductor substrate of a type, an insulating thick film for element isolation formed on the semiconductor substrate on an inner wall of the trench and a peripheral part of the trench, and an insulating thickness for element isolation in the peripheral part. a source region of a signal readout MOS transistor of a conductivity type opposite to that of the semiconductor substrate adjacent to the film; a gate insulating film of the MoS transistor formed on the semiconductor substrate adjacent to the source region; a drain region for a bit line of a conductivity type opposite to that of the semiconductor substrate formed near the surface of the semiconductor substrate on the side opposite to the source region adjacent to the film; and a drain region for a bit line of the opposite conductivity type to the semiconductor substrate, and a region around the trench of the thick insulating film for element isolation and the gate. a word line first electrode provided on the insulating film; a glabellar insulating film formed on the first electrode; a word line first electrode provided on the element isolation insulating film; an insulating film between the eyebrows formed on one electrode, a second electrode layer for a lower cell plate formed on the thick insulating film for element isolation and on the interlayer insulating film, and a second electrode layer between the second electrode layer and the source region. an interlayer insulating film provided between, an insulating film for the dielectric of the lower capacitor of the memory cell formed on the second electrode layer, and an insulating film for the dielectric of the lower capacitor formed on the lower capacitor dielectric, and an insulating film for the dielectric of the lower capacitor formed on the second electrode layer; a third electrode layer in contact with the third electrode layer, a dielectric insulating film of the upper capacitor of the memory cell formed on the third electrode layer, and the second electrode layer formed on the dielectric insulating film of the upper capacitor. and a fourth electrode layer for an upper cell plate having an electrical connection portion, and a fourth electrode layer for an upper cell plate having an electrical connection portion, and a fourth
A one-transistor type DRAM device characterized in that an electrode layer is inserted is provided.

For production This configuration has the following effects.

The storage capacitor consists of a part buried in the trench and a part on the other plane, and further includes an upper part of the third electrode,
The capacitance is extremely increased because the lower and side portions all serve as cell capacitors.Even when compared with an FCC structure with the same cell area and the same trench depth, the cell capacitance is on a can plate. Based on our calculations, the cell area is 8) Ivy? (equivalent to 4M bit DRAM), trench depth 3) 1m
By setting the trench depth to 3.11 m, the cell capacitance can be approximately 120 fF, and when the cell area is 5)t (equivalent to 16 M pit DRAM), approximately eofF can be obtained by setting the trench depth to 3.11 m. In addition, by making the area of the source part as small as possible in design or process technology, the memory cell's source Since the pn junction region between the diffusion portion and the substrate can be made small, the leakage current of the memory cell can be kept extremely small.

Furthermore, since the pn junction region is small, the depletion layer associated therewith also becomes very small, thereby making it possible to drastically reduce the α-ray phasing error. In addition, when forming a thin insulating film to serve as a capacitor, the oxidation rate of polysilicon does not depend on orientation, allowing the insulating film to grow with a uniform thickness, thereby suppressing variations and reductions in dielectric strength.

Furthermore, even if a multilayer structure of St N and SiO2 is used as the insulating film constituting the memory cell capacitor, if the second and third electrodes constituting the memory cell capacitor are formed of polysilicon, the stress caused by Si3N4 can be reduced. Since the influence can be absorbed without affecting the substrate, it is extremely advantageous for stable formation of a multilayer insulating film.

Embodiment FIG. 1 is a one-transistor type D according to an embodiment of the present invention.
FIG. 2 is a sectional side view of a main part of a memory cell portion of a RAM device. 1st
In figure a, 1 is a drain forming a bit line;
2 is an MO constituting a transfer gate for signal readout.
S) Gate oxide film of the transistor, 3 is a gate electrode made of poly7 silicon which constitutes a word line, 4 is a source diffusion part of a memory cell, 5 is an S102 insulating film which constitutes a capacitor of a memory cell, 6 is a A lower gray electrode made of polysilicon forming a lower cell plate, 7 a thick film for cell isolation, 8 a substrate, 9 a conductive electrode made of polysilicon forming a source part of a memory cell, 1o an interlayer An insulating film 11 is an upper gray electrode made of polysilicon forming an upper cell plate. The lower plate electrode 6 and the upper plate electrode 11 are electrically connected outside the memory cell. A capacitor is formed between the cell plate at 6 and the conductive electrode forming the source portion of the memory cell at 9.

FIG. 1 is a sectional view of a main part of a memory cell portion of a one-transistor type DRAM device according to another embodiment of the present invention;
The difference from the embodiment shown in FIG. This point is placed on the fourth electrode layer 11 constituting the plate electrode.

Effects of the Invention As described above, according to the present invention, a semiconductor memory device not only can have an extremely large storage capacity, but also can drastically reduce the soft error rate and leakage current, and can easily form an insulating thin film during the process. . Therefore, the present invention allows for higher integration of semiconductor memory devices.

The effect of realizing large capacity extremely easily can be obtained.

[Brief explanation of drawings]

1a and 1) are side sectional views of main parts showing a semiconductor memory cell section according to an embodiment of the present invention, FIG. 2 is a side sectional view of main parts showing an FCC structure memory cell which is an example of a conventional trench structure, FIG. 3 is a side sectional view of a main part of a conventional stacked structure memory cell. 1... Drain forming the bit line, 2...
...Gate insulating film, 3...Gate electrode forming word line, 4...Source diffusion part of memory cell, 5...Constituting capacitor of memory cell Insulating film, 6... lower plate electrode, 7...
... Thick film for separation, 8 ... Substrate, 9 ...
...Conductive electrode constituting the source part of the memory cell, 10
. . . Interlayer insulating film, 11 . . . Upper plate electrode. Name of agent: Patent attorney Toshio Nakao and one other person
--Bishinino and ηAT uY・shi4゜to・γ−to clue & Smo

Claims (1)

[Scope of Claims] 1: a trench formed in a predetermined region of a semiconductor substrate of one conductivity type; an insulating thick film for element isolation formed on the semiconductor substrate on the inner wall of the trench and the peripheral portion of the trench; A source region of a signal readout MOS transistor of a conductivity type opposite to that of the semiconductor substrate formed near the surface of the semiconductor substrate adjacent to the thick insulating film for element isolation in the peripheral portion, and on the semiconductor substrate adjacent to the source region. a gate insulating film of the MOS transistor formed in the gate insulating film; and a bit line drain region of a conductivity type opposite to that of the semiconductor substrate formed near the surface of the semiconductor substrate on the opposite side to the source region adjacent to the gate insulating film. , a word line first electrode provided on the trench peripheral portion of the element isolation thick insulating film and on the gate insulating film; an interlayer insulating film formed on the first electrode; and the element isolation insulating film. a second electrode layer for a lower cell plate formed on the thick film and the interlayer insulating film; an interlayer insulating film provided between the second electrode layer and the source region; a dielectric insulating film of the lower capacitor of the formed memory cell; a third electrode layer formed on the dielectric insulating film of the lower capacitor and in electrical contact with the source region; and a third electrode layer on the third electrode layer. a fourth electrode layer for an upper cell plate formed on the dielectric insulating film of the upper capacitor and having an electrical connection with the second electrode layer; A one-transistor type DRAM device comprising: a fourth electrode layer inserted between third electrode layers of adjacent memory cells in the trench. 2. The one-transistor DRAM device according to claim 1, having a first electrode formed on the gate insulating film and on the fourth electrode layer via an interlayer insulating film.