JPH02140853A - Bus width converting circuit - Google Patents

Abstract

PURPOSE:To effectively utilize a CPU bus, to shorten its occupation time, and to speed up transfer of data on an I/O bus by providing an output data dividing means and an input data merging means. CONSTITUTION:Out of the output data at 16 bits outputted through a CPU bus 2, the higher-order eight bits are held by a D latch 10, the lower-order eight bits are held by a D latch 12, and successively sent through buffers 11 and 13 to an I/O bus 3. On the other hand, the input data at 16 bits successively inputted through the I/O bus 3 in units of eight bits are successively held by D latches 14 and 16, and sent through buffers 15 and 17 to the CPU bus 2. Thus, the whole bus width of the CPU bus is effectively utilized, the bus occupation time at the time of input/output the data with respect to I/O equipment is shortened, and the transfer of the data on the I/O bus can be speeded up while the data transfer speed on the CPU bus is being suppressed to a low value according to a DMA (Direct Memory Access) controller, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" This invention is applicable to, for example,
■10 (input/output) connected to the U bus and external peripheral devices
The present invention relates to a bus width conversion circuit that matches bus widths when the bus widths are different.

"Conventional technology" As is well known, C plays a central role in computer systems.
In order to improve its processing performance, I'U has increased the number of processing bits from the conventional 8 bits to 16 bits or 32 bits.
It is moving to bits. Under such circumstances,
Various input/output devices such as hard disk drives, which are positioned as peripheral devices outside the computer system, still mainly exchange data in 8-bit units.
Many types of input/output devices with 8-bit specifications are available on the market in a wide variety of types and at low prices.

``Problem to be solved by the invention'' By the way, the CPU with 16-bit or 32-bit specifications
When data is exchanged in 8-bit units between a computer and an 8-bit specification input/output device, the following problems occur.

■For example, when connecting a 16-bit specification CPU to an 8-bit specification input/output device, an 8-bit I10 bus will be connected to the 16-bit CPU bus, but in this case, the total bus width of the CPU bus Only half of the CPU bus is used, making it impossible to effectively utilize the CPU bus to exchange data.

As a result, the exclusive time of the CPU bus becomes longer than necessary, and the processing capacity of the CPU cannot be fully utilized.

■In order to achieve higher performance in computer systems, faster data transfer speeds between the CPU and input/output devices are required, but the bus width remains at 8 bits.
When data transfer speeds are increased, DMA (direct memory access) controllers on the market generally no longer work properly, and in order to cope with this, new hardware with dedicated data transfer functions is needed. must be designed and developed. Here, the case where 8-bit data is transferred at a transfer rate of 500+ms and the case where 16-bit data is transferred at 100 (1+s) are substantially equivalent, so if the bus width is widened, the operating speed will be increased. It is also possible to use a relatively slow commercially available DMA controller, and the system can be configured at low cost.

■In order to solve the problems of ■ and ■ mentioned above, the CPU
16-bit or 32-bit input/output according to the specifications! It is possible to use a 16-bit or 32-bit LSI for data transmission systems, but this is not preferable because the price of the entire computer system will be high. It is desirable to purchase an LSI with 8-bit specifications.

This invention was made in view of the above-mentioned circumstances, and the CP
In addition to effectively utilizing the U bus and shortening its dedicated time, the data transfer speed on the CPLJ bus is kept low to match the DMA controller, etc., and the data transfer speed on the 10 bus is increased. It is an object of the present invention to provide a bus width conversion circuit that allows the entire system to be configured at low cost.

"Means for Solving the Problem" This invention provides a CPU bus having a bus width of M bits,
In a bus width conversion circuit that performs bus width matching with an I10 bus having a bus width of N (≦M/2n (n is a positive integer)) bits, a signal is output in units of N bits via the CPU bus. output data dividing means for dividing the output data into N bit units and sequentially sending them to the I10 bus, and merging input data sequentially input in N bit units via the I10 bus in N bit units. and input data merging means for sending to the CPU bus.

"Operation" According to the above configuration, the C inside the computer system
The M-bit output data output via the PU bus is
After the output data is divided into N bits by the output data division means: 1.
While being sequentially sent out to the I10 bus connected to external peripherals,! Input data sequentially input in N bit units via the 10 bus is merged in N bit units by the input data merging means and then sent to the CPU bus.
When the bus widths of the bus and the I10 bus are different, these bus widths are matched, and as a result, the entire bus width of the CPU bus is effectively used, and the bus exclusive time when the 110 device is at high output is In addition to being shortened, the CPU
It is possible to increase the data transfer speed on the I10 bus while keeping the data transfer speed on the bus low in accordance with the DMA controller and the like.

Embodiment j Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a bus width conversion circuit according to an embodiment of the present invention. In this figure,! is a bus width conversion circuit, and ! It is provided between a CPU bus 2 having a bus width of 6 bits and an I10 bus 3 having a bus width of 8 bits. A CPU 4, a DMA controller 5, and a data memory (RAM) 6 are connected to the CPU bus 2, and a peripheral f10 controller (
For example, various input/output devices 8 are connected via a hard disk controller, a communication controller, etc.) 7.

In the bus width conversion circuit 1, IO! 6 bit CPU
This is an 8-bit D latch that holds data for the upper 8 bits (f-1) of bus 2, and the output of this D latch 10 is 8 bits.
8-bit I1 via 3-bit state buffer 11
Output to 0 bus 3. Similarly, 12 is a 16-bit C
This is an 8-bit D latch that holds data for the lower 8 bits (L) of the PU bus 2, and the output of this D latch 12 is 8 bits.
Via the bit 3 state buffer y13! 10 bus 3.

14 is an 8-bit D latch that holds the 8-bit data of the I10 bus 3, and the output of this D latch 14 is sent to the upper 8 bits (g) of the CPU bus 2 via the 8-bit 3-state buffer I5. Output to. Similarly, 16 is I
The output of this D latch I6 is output to the lower 8 bits (L) of the CPU bus 2 via an 8-bit 3-state buffer I7. Ru.

20 is the DMA controller 5 and peripheral 110 control [
Based on various control signals supplied from l-rough, D latch 10 and ! A write control circuit 30 instructs the data acquisition timing of 2 and the data output timing of the buffers 11 and 13, and 30 is a write control circuit that instructs the D latch 14 and the data output timing of the buffers 11 and 13 based on various control signals supplied from the DMA controller 5 and the peripheral I10 controller 7. This is a read control circuit that instructs data acquisition timing of buffers 15 and 17 and data output timing of buffers 15 and 17.

As shown in FIG.
It is composed of an MA timing generator 2I, a write strobe generator 22, and a 2-bit down counter 23, and as shown in FIG. 3, the count value of the down counter 23 changes depending on the current operating state. The read control circuit 30 also includes a DMA timing generator 31, a read strobe generator 32, as shown in FIG.
It consists of a 2-bit up counter 33, and changes depending on the current operating state as shown in FIG.

In the above configuration, of the 16-bit output data output via CPU bus 2, the upper 8 bits are held in the D latch IO and the lower 8 bits are held in the D latch I2, and the data is divided into 8 bit units. The data is in the buffer l! and! 3 to the I10 bus 3. On the other hand, 16-bit input data sequentially input in 8-bit units via the [10 bus 3] is input to the D latches 14 and 16.
is held sequentially by this! The data merged into 6-bit units is sent to C through buffers 15 and 17.
It is sent to PU bus 2.

Next, the operation of each part mentioned above will be explained in more detail.

First, when performing a DMA transfer, the CPU 4 selects "from which address in the data memory 6 and how many words should be transferred".
Write to controller 5. Then, the DMA controller 5 outputs a BUSRQ signal to the CPU 4, requesting that the bus be transferred. In response to this request, the CPU 4 becomes the DMA controller 5! 3 outputs the US A K signal and passes the bus to the DMA controller 5. As a result, the data memory 6 and the bus width conversion circuit 1 come under the control of the DMA controller 5, and the peripheral I10 controller 7 is controlled by the write control circuit 20 and the continuation control circuit 30 of the bus width conversion circuit 1. Then, this peripheral I10 controller 7 is in a state of directly exchanging data with the data memory 6 via the bus width conversion circuit l.

The subsequent operations will be explained separately into operations for writing data from the CPU 4 side to the external input/output device 8 and operations for reading data output from the input/output device 8.

It is assumed that in the initial state, both the down counter 23 and the up counter 33 are set to a count value of "00".

[Operation when data is input]

(2) The CPU 4 issues a command corresponding to data writing to the peripheral I10 controller 7.

(2) The peripheral I10 controller 7 enables DrtQ and requests data transfer (CPU→peripheral I10). At this time, in the initial state, the write control circuit 20
The down counter 23 is in the state of “00”, and the DMA
The timing generator 21 converts the PDRQ request into CDrtQ
It is transmitted to the CPU 4 as a signal.

■The DMA controller 5 that received this CDRQ signal,
The 16-bit write data read from the data memory 6 is sent to the bus width conversion circuit via the CPU bus 2! At the same time, a CDAK signal indicating a response to the transfer request is supplied to the DMA timing generator 21 and write strobe generator 22 of the write control circuit 20.

(2) The write strobe generator 22 supplies a WR multiplied signal to the clock terminals CK of the D latches 10 and 12, which instructs data capture. As a result, the upper 8 bits of the 16-bit write data supplied via the CPU bus 2 are taken into the D latchero, and the lower 8 bits are taken into the D latch 1.
Incorporated into 2. At the same time, the write strobe generator 22 outputs W I? The double signal is supplied to the load terminal LOAD of the down counter 23, and the count value is preset to "IO".

■The light strobe generator 22 is a down counter 23
At the point when the count value = "!0", the W r (H signal that instructs the output of the upper side data is supplied to the gate input terminal G of the buffer 11, and at the same time, the PDAK signal is sent to the DMA timing generator 2K. As a result, the upper 8 bits of write data captured in the D latch 10 are sent out onto the I10 bus 3 via the buffer l!, and captured into the peripheral 110 controller 7.

Thereafter, the write strobe generator 22 sets the count value of the down counter 23 to "OI".

■DMA retiming generator 2, when the PDRQ signal requesting the next data is supplied from the peripheral E10 controller 7, the count value is "Ol" at this point, so the DMA controller 5 In addition to outputting the CDRQ signal, the write strobe generator 22 buffers the WRL signal that instructs the output of lower-order data! At the same time, it instructs the DMA timing generator 21 to output the PDAK signal, so that the lower 8 bits of write data captured in the D latch 12 are transferred to the buffer I3. The signal is sent out onto the ■10 bus 3 via the I10 bus 3 and taken into the peripheral I10 controller 7. Thereafter, the write strobe generator 22 sets the count value of the down counter 23 to "00°."

By repeating the operations ① to ① described above a number of times according to the number of words to be transferred, the transfer of the necessary write data is completed.

[Operation when reading data]

(2) The CPU 4 issues a command corresponding to data reading to the peripheral I10 controller 7.

(2) The peripheral I10 controller 7 enables DRQ and requests data transfer (CPU←peripheral I10).

At this time, in the initial state, the read control circuit 30
The up counter 33 is in the state of "00".

■The DMA timing generator 31 that receives the PDRQ signal transmits the PDAK signal indicating a response to the transfer request to the peripheral I1.
On the other hand, the I, 10 controller 7, which received this PDAK signal, sends the upper 8-bit successive data supplied from the input/output device 8 to the bus width conversion circuit via the I10 bus 3. Send to.

(2) The read strobe generator 32 supplies an RDH signal to the clock terminal OK of the D latch 14, which instructs the fetching of upper-order data. As a result, the upper 8 bits of read data supplied via the I10 bus 3 are taken into the D latch 14. Immediately after that, the read strobe generator 32 sets the count value of the up counter 33 to "0!°."

■The following successive data (
When the PDrlQ signal indicating a transfer request for the lower 8 bits is supplied, repeat the same operations as above (■ to ■),
The lower 8 bits of read data supplied via the I10 bus 3 are taken into the D latch 16. In this case, the read strobe generator 32 sends the RDL signal instructing to take in the lower data to the clock terminal CK of the D latch 16.
supply to Thereafter, the read strobe generator 32 sets the count value of the up counter 33 to "lO".

(2) When the count value of the up counter 33 reaches "lO", the DMA timing generator 3I supplies the DMA controller 5 with a CDRQ signal indicating a request to transfer successive data. After that, at the same time as the CDAK signal is enabled, the RD double signal buffer 1 instructs to output data.
5 and 17 to the gate input terminals G. As a result, D
The successive data of the upper 8 bits taken in the latch 14 and the successive data of the lower 8 bits taken in the D latch 16 are sent to the CPU via the output j1 buffers I5 and 17.
simultaneously on bus 2, resulting in 16 bits of successive data being written into data memory 6 by DMA controller 5. Thereafter, the CDAK signal supplied from the DMA controller 5 is disabled, so that the up counter 33 is cleared and its count value becomes 2"00".

By repeating the operations ① to ① described above a number of times according to the number of words to be transferred, the necessary successive data transfer is completed.

As described above, the 16-bit output data outputted via the CPU bus 2 is divided into 8-bit units by the bus width conversion circuit l and sequentially sent to the Summer 10 bus 3, while [
Input data that is input sequentially in 8-bit units via the 10 bus 3 is processed by the bus width conversion circuit I! The data are merged into 6-bit units and sent to the CPU bus 2.

"Effects of the Invention" As explained above, according to the present invention, output data output via a CPU bus having a bus width of M bits is processed by the data dividing means to N (≦M/2n (n is positive). integer)
) After being divided into bit units, the input data is sequentially sent to the I10 bus, while the input data sequentially input in N bit units via the I10 path is merged into M bit units by the input data merging means, and then sent to the CPU. Since data is sent to the bus, the entire bus width of the CPU bus is effectively used to exchange data, and as a result, the bus exclusive time during input/output with 110 devices on the CPU bus is reduced. planned, C
This has the effect of making full use of the processing power of the PU, and also reduces the data transfer speed on the CPU bus.
It is possible to increase the data transfer speed on the I10 bus while keeping it low enough to match the MA controller, etc., so it is fully compatible with slow operating speed DMA controllers etc. that are generally on the market. Since the computer system can be constructed using LSIs with a wide variety of inexpensive 8-bit specifications, it is also possible to construct the entire computer system at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a write control circuit of the same embodiment, and FIG. 3 is a block diagram showing the operation of the write control circuit. FIG. 4 is a block diagram showing the configuration of the read control circuit of the same embodiment, and FIG. 5 is a diagram for explaining the operation of the read control circuit. l...Bus width conversion circuit, 2...CPU bus, 3...I10 bus, +0.12, 14.16...8 bit D Radzi, 11.13,15. I7...8 bit buffer, 20...Write control circuit, 2I...DMA timing generator, 22...
... Write strobe generator, 23 ... Down counter, 30 ... Read control circuit, 31 ... DMA timing generator, 32 ...
...Read strobe generator, 33...Up counter. Applicant Yamaha Co., Ltd. Figure 2 Figure 4 Figure 3 Figure 5

Claims (1)

[Claims] A CPU bus having a bus width of M bits, and a bus width of N (≦M/2
In a bus width conversion circuit that performs bus width matching with an input/output bus having a bus width of ^n (n is a positive integer) bits, output data is output in M bit units via the CPU bus. output data dividing means that divides the data into N bit units and sequentially sends the divided data to the input/output bus, and merges the input data sequentially input in N bit units via the input/output bus into M bit units , and input data merging means for sending to the CPU bus.