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JPH02121329A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02121329A
JPH02121329A JP27506588A JP27506588A JPH02121329A JP H02121329 A JPH02121329 A JP H02121329A JP 27506588 A JP27506588 A JP 27506588A JP 27506588 A JP27506588 A JP 27506588A JP H02121329 A JPH02121329 A JP H02121329A
Authority
JP
Japan
Prior art keywords
film
substrate
phase
concentration
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27506588A
Other languages
Japanese (ja)
Inventor
Osamu Haida
拝田 治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP27506588A priority Critical patent/JPH02121329A/en
Publication of JPH02121329A publication Critical patent/JPH02121329A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent any Al spike from occurring without augmenting the contact resistance between an Si substrate and an Al wiring by a method wherein, during the formation process of Al films, an Ag film containing Si is higher concentration than the Si slid solubility at heat treatment temperature is formed in the first phase while another Al film containing Si in lower concentration than the Si concentration in the first phase is formed in the second phase. CONSTITUTION:The first layer insulating film 1 is deposited on an Si substrate 2. First, the photographic etching process is used together with the dry-etching process to remove oxide film 1 on the contact region for making a contact hole 3. Secondly, the Si substrate 2 is held on an anode of a sputtering device while the contact hole 3 is coated with the first phase Al film 4 as a wiring film on a cathode comprising Al-Si alloy (1wt.% of Si). Thirdly, the Al film 4 is coated with the second phase A film 5. In case of forming the second phase Al film 5, Al-Si alloy containing 0.4wt.% of Si is used for the cathode of the sputtering device while the second Al film 5 becomes another Al layer containing 0.4wt.% of Si.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特に、高集積
LSIの製造において、配線材料として使用するSi含
有Al膜とSi基板とのコンタクト部分の接続状態を改
良した、半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device, and in particular, in manufacturing a highly integrated LSI, contact between a Si-containing Al film used as a wiring material and a Si substrate. The present invention relates to a method of manufacturing a semiconductor device in which the connection state of parts is improved.

〔従来の技術〕[Conventional technology]

従来から、Si半導体基板上の絶縁膜に開孔処理(コン
タクトホールエツチング)を行い、次いで配線材料であ
るAIを蒸着等して、Al配線膜を半導体基板上に形成
することにより、半導体装置の製造が行われてきた。
Conventionally, semiconductor devices have been fabricated by performing a hole-opening process (contact hole etching) on an insulating film on a Si semiconductor substrate, and then depositing AI, which is a wiring material, to form an Al wiring film on the semiconductor substrate. Manufacturing has been going on.

従来配線材料であるAIには、Siが1〜2%含まれて
いた(例えば、LSIハンドブック、280頁、オーム
社、1984年)。Siを含有する理由は、熱処理時、
Si基板からAl膜への31の拡散の逆現象として生ず
る、Si基板へのAIの拡散成長(AIスパイク)を防
止するためである。即ち、AlにSiを含有することに
よりSi基板からAI中へのSiの拡散を防止し、もっ
てAIのSi基板への拡散を防止することによりAIス
パイクの発生を避けようとするものである。
AI, which is a conventional wiring material, contains 1 to 2% Si (for example, LSI Handbook, p. 280, Ohmsha, 1984). The reason for containing Si is that during heat treatment,
This is to prevent the diffusion growth of AI (AI spike) into the Si substrate, which occurs as a reverse phenomenon of the diffusion of 31 from the Si substrate to the Al film. That is, by containing Si in Al, the diffusion of Si from the Si substrate into the AI is prevented, thereby preventing the diffusion of AI into the Si substrate, thereby avoiding the occurrence of AI spikes.

このAIスパイクが生ずるとSi基板のソース。When this AI spike occurs, the source of the Si substrate.

ドレインを貫通してAIが成長するので、基板とAI配
線膜とが短絡してしまう。そこで、従来はSiをAl膜
中に含有させることにより、このような短絡を防止して
いる。
Since AI grows through the drain, the substrate and the AI wiring film are short-circuited. Conventionally, such short circuits have been prevented by incorporating Si into the Al film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記1〜2重量%のSi含有量は、AI
配線膜とSi基板との電気的接続状態を良好にするため
の熱処理(シンタリング)温度(400〜500°C)
におけるSiの固溶度より大きい為、熱処理中にSi基
板とAI配線膜とのコンタクト界面にAI中に含有され
ていたSiが析出して、コンタクト抵抗が増大すると云
う問題があった。この問題は、LSIの高集積化に伴っ
てコンタクト径が小さくなるにつれて、特に深刻な問題
となっている。
However, the Si content of 1 to 2% by weight is
Heat treatment (sintering) temperature (400 to 500°C) to improve the electrical connection between the wiring film and the Si substrate
Since the solid solubility of Si is larger than that of Si, there is a problem in that during heat treatment, Si contained in the AI precipitates at the contact interface between the Si substrate and the AI wiring film, increasing the contact resistance. This problem has become particularly serious as the contact diameter becomes smaller as LSIs become more highly integrated.

尚、従来、熱処理温度における固溶度(0,28重量%
4400°c、o、so重量%500°C,Hanse
n、M、Con5titution  ofbinar
y  alloys、McGraw−Hill、195
8)より多い量のSiをAl膜中に含有していた理由は
、Si基板からAl配線膜へのSiの拡散を確実に防止
しようとすると、固溶度より非常に高い濃度のSiをA
I中に含む必要があるからである。
In addition, conventionally, the solid solubility at the heat treatment temperature (0.28% by weight)
4400°C, o, so wt% 500°C, Hanse
n, M, Condition of binar
y alloys, McGraw-Hill, 195
8) The reason why a larger amount of Si was contained in the Al film is that in order to reliably prevent the diffusion of Si from the Si substrate to the Al wiring film, it is necessary to
This is because it needs to be included in I.

従って、従来の半導体の製造方法によれば、AIスパイ
クを防止しようとするとSi、33板とAI配線とのコ
ンタクト抵抗の増大を避けることが出来ないと云う課題
があった。
Therefore, according to the conventional semiconductor manufacturing method, there is a problem in that an increase in contact resistance between the Si, 33 board and the AI wiring cannot be avoided when trying to prevent AI spikes.

本発明はこのような従来の課題を解決するために、Si
基板とAI配線とのコンタクト抵抗の増大を生ずること
なくAIスパイクの発生を防止可能な、半導体装置の製
造方法を提供することを目的とする。
In order to solve such conventional problems, the present invention
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the occurrence of AI spikes without increasing the contact resistance between the substrate and the AI wiring.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成する為に、本発明は、絶縁膜が形成され
たSi基板に開孔処理を行った後、当該基板上にSiを
含有したAI膜を形成し、次いで熱処理をして成る半導
体装置の製造方法において、前記AI膜を形成する工程
は、Si濃度の異なる複数のAl膜を順次形成する工程
から成り、第1段階のAI膜形成工程は、前記熱処理温
度におけるSi固溶度よりも高い濃度のSiを含有する
AI膜を形成するものであり、次段階のAI膜形成工程
は、前記第1段階の5ifi度よりも低い濃度のSiを
含有するAI膜を形成するものである、ことを特徴とす
る。
In order to achieve the above object, the present invention provides a semiconductor formed by performing hole-opening treatment on a Si substrate on which an insulating film is formed, forming an AI film containing Si on the substrate, and then heat-treating the Si substrate. In the method for manufacturing the device, the step of forming the AI film consists of a step of sequentially forming a plurality of Al films with different Si concentrations, and the first step of forming the AI film is based on the Si solid solubility at the heat treatment temperature. The second step is to form an AI film containing a high concentration of Si, and the next step of forming an AI film is to form an AI film containing a lower concentration of Si than the 5ifi degree of the first step. , is characterized by.

〔作用〕[Effect]

上記本発明において、第1段階のAI膜を形成する工程
により、Si基板上にはSi濃度が高いAI配線膜が形
成される。従って、シンクリング時、Si基板からAl
膜中へSiが拡散するのをブロックすることになるので
、Alスパイクの発生を防止することが出来る。
In the present invention, in the first step of forming an AI film, an AI wiring film with a high Si concentration is formed on the Si substrate. Therefore, during sinkling, Al
Since diffusion of Si into the film is blocked, generation of Al spikes can be prevented.

一方、第2段階以降のAI膜を形成する工程では、前記
第1段階のAI膜上に、濃度の低いsiを含有するAI
膜が形成される。次いで、熱処理を行うと第1段階のA
I腹膜中Siが第2段階のAI腹膜中拡散してSi濃度
が平均化し、第1゜2段階のAI腹膜中Si濃度を固溶
度またはそれに近い値に小さくすることが出来るため、
Si基板とAI膜とのコンタクト界面にSiが析出する
のを防止することが出来る。
On the other hand, in the process of forming an AI film in the second and subsequent stages, an AI film containing low concentration of Si is formed on the AI film in the first stage.
A film is formed. Next, when heat treatment is performed, the first stage A
The Si in the I peritoneum diffuses into the AI peritoneum in the second stage, and the Si concentration becomes average, and the Si concentration in the AI peritoneum in the first stage can be reduced to the solid solubility or a value close to it.
It is possible to prevent Si from being deposited at the contact interface between the Si substrate and the AI film.

〔実施例〕〔Example〕

第1図に示す工程図を参照して、本発明の実施例につい
て説明する。
Embodiments of the present invention will be described with reference to the process diagram shown in FIG.

先ず第1図(1)の工程について説明する。First, the process shown in FIG. 1(1) will be explained.

Si半導体基板「方位、(100)、N形、ρ=1〜5
Ω・cm、径75〜100mmφ、厚さ450〜600
μ」; リンをドープしたN形Si単結晶つェーハ上にMOS)
ランジスタ素子を形成下稜、第1層絶縁膜lをSi基板
2上に成長させる。
Si semiconductor substrate "Orientation, (100), N type, ρ = 1 ~ 5
Ω・cm, diameter 75-100mmφ, thickness 450-600
MOS on a phosphorus-doped N-type Si single crystal wafer)
After forming the transistor element, a first layer insulating film 1 is grown on the Si substrate 2.

次に、写真蝕刻法とドライエツチング法を用いて、コン
タクト領域の上記酸化膜1を除去してコンタクトホール
3を形成する。
Next, using photolithography and dry etching, the oxide film 1 in the contact region is removed to form a contact hole 3.

次いで、上記Si基板をスパッタ装置の陽極に保持し、
一方スバッタ装置の陰極には、配線材料であるAl−S
i合金(1重量%のSiを含有)を保持して、上記コン
タクトホール3上に配線膜である。第1段階AI膜4を
被着させる。
Next, hold the Si substrate on the anode of a sputtering device,
On the other hand, the cathode of the spatter device is made of Al-S which is a wiring material.
A wiring film is formed on the contact hole 3 by holding an i alloy (containing 1% by weight of Si). First stage AI film 4 is deposited.

この第1段階AI膜4は、全Al膜厚の20%となるよ
うに形成され、1重量%のSiを含有するAl膜となる
。この第1段階AI膜4が形成された後、第1図(2)
の工程に示すようにAI膜4上に、前記スパッタリング
と同様に第2段階のAl膜5を被着形成する。この第2
段階AI膜5の形成の際、スバンタ装置の陰極には、0
.4重量%のSiを含有するAl−Si合金が使用され
、第2段階Al膜5は、0.4重量%のSiを含有する
Al層となる。この第2段階AI膜5は、全Al膜厚の
80%の厚さとなるように形成される。
This first stage AI film 4 is formed to have a thickness of 20% of the total Al film thickness, and is an Al film containing 1% by weight of Si. After this first stage AI film 4 is formed, as shown in FIG.
As shown in the process, a second-stage Al film 5 is deposited on the AI film 4 in the same manner as in the sputtering process. This second
During the formation of the stage AI film 5, the cathode of the Svanta device is
.. An Al-Si alloy containing 4% by weight of Si is used, and the second stage Al film 5 is an Al layer containing 0.4% by weight of Si. This second stage AI film 5 is formed to have a thickness of 80% of the total Al film thickness.

この第2段階AI膜5を形成した後、フォトレジストに
よる写真蝕刻法を使って、パターンを形成し、フォトレ
ジストをマスクにして、不用部分をドライエツチングで
除去し、フォトレジストを洗い落とす。
After forming the second stage AI film 5, a pattern is formed using photolithography using a photoresist, and using the photoresist as a mask, unnecessary portions are removed by dry etching and the photoresist is washed away.

次に、CVD法により、Si基板温度400°Cで、A
I膜5上にSi0g膜(第2層間絶縁膜)6を堆積形成
する。この第2層間絶縁膜6は、この絶縁膜上に形成さ
れる第2のAI配線と前記第1のAI配線(Al膜4.
5)とを絶縁するためのものである。
Next, by CVD method, A
A Si0g film (second interlayer insulating film) 6 is deposited on the I film 5. This second interlayer insulating film 6 connects the second AI wiring formed on this insulating film and the first AI wiring (Al film 4.
5).

この第2層間絶縁膜の形成終了後、Si基板に400°
C230分の加熱処理を行い、コンタクトホール3にお
けるSiとAIの電気的接続を良好にすることが行われ
る(シンタリング)。
After completing the formation of this second interlayer insulating film, the Si substrate is
A heat treatment for C230 minutes is performed to improve the electrical connection between Si and AI in the contact hole 3 (sintering).

以上説明した実施例において、第1段階AI膜4には、
1重量%のSiが含有されている。このSiの濃度は、
シンタリング、第2層間絶縁膜5の形成時に受ける処理
温度でのSiのAtに対する固溶度(0,3〜0.8重
量%)より高い為、基板2からSiがAl膜4に拡散す
るのを防止できる。この点からして、第1段階AI膜4
のSi濃度は、熱処理温度におけるSiの固溶度より十
分大きいことが必要である。具体的には、Al膜4は、
0.8〜2.0重量%程度のSiを含有していることが
望ましい。
In the embodiment described above, the first stage AI film 4 includes:
It contains 1% by weight of Si. The concentration of this Si is
Since the solid solubility of Si in At at the processing temperature during sintering and formation of the second interlayer insulating film 5 is higher than the solid solubility of At (0.3 to 0.8% by weight), Si diffuses from the substrate 2 into the Al film 4. can be prevented. From this point of view, the first stage AI film 4
It is necessary that the Si concentration is sufficiently higher than the solid solubility of Si at the heat treatment temperature. Specifically, the Al film 4 is
It is desirable that Si be contained in an amount of about 0.8 to 2.0% by weight.

0.8重量%未満であると、Al膜4の形成時、部分的
にsN4度の低い個所が生じ、この部分で基板2からS
iがAt膜4中に拡散し、その逆反応としてAlスパイ
クが生ずる虞が在るからである。一方、2.0重量%を
越えてSiが含有されると、熱処理時Siが析出しコン
タクトホール3のコンタクト抵抗が増大してしまうため
である。
If the amount is less than 0.8% by weight, when forming the Al film 4, there will be a portion where the sN4 degree is low, and in this portion, the SN will be removed from the substrate 2.
This is because there is a possibility that i diffuses into the At film 4 and Al spikes are generated as a reverse reaction. On the other hand, if Si is contained in an amount exceeding 2.0% by weight, Si will precipitate during heat treatment and the contact resistance of the contact hole 3 will increase.

一方、第2段階Al膜5は、0.4重量%のSiを含有
している。この濃度は、熱処理温度におけるSiの固溶
度に大体等しく、且つ第1段階Al膜4のSi濃度より
も低い値となっている。
On the other hand, the second stage Al film 5 contains 0.4% by weight of Si. This concentration is approximately equal to the solid solubility of Si at the heat treatment temperature and is lower than the Si concentration of the first stage Al film 4.

この第2段階AI膜のSi濃度が、第1段階のAl膜の
それより低い値となっているのは、熱処理時、第1段階
のAI膜4中に含有されているSiが、第2段階のAl
膜5中に拡散し、AI膜4゜5の間でSi濃度が平均化
されることにより、全体としてはSi濃度が低下するた
め、熱処理の際、Siの析出を防止し、コンタクト抵抗
の増大を避けることが可能となるからである。この点か
ら、第2段階のAl膜5中の5ii4度は第1段階のA
I膜5より低ければ良いが、その時の熱処理温度におけ
る固溶度またはそれ以下であることが望ましい。本実施
例では、0.3〜0.8重量%の5tfi度であること
が好ましい。0.3重量%未満であると、A!膜4の5
ifi度が必要以上に少なくなり、その結果、基板2か
らSiが拡散し゛ζ前記アルミスパイク発生の虞がある
からである。−方、0.8重量%を越えてSiが含有さ
れていると、AI膜4.5中のSi濃度が結果的に高く
なり、その結果Siの析出によるコンタクト抵抗の増大
が生ずるからである。
The reason why the Si concentration of the second stage AI film is lower than that of the first stage Al film is that during the heat treatment, the Si contained in the first stage AI film 4 is stage Al
Diffuses into the film 5 and averages the Si concentration between the AI films 4° and 5, reducing the overall Si concentration, which prevents Si precipitation during heat treatment and increases contact resistance. This is because it becomes possible to avoid. From this point, 5ii4 degree in the Al film 5 in the second stage is equal to A in the first stage.
It is sufficient if it is lower than the I film 5, but it is desirable that the solid solubility is at or below the solid solubility at the heat treatment temperature at that time. In this example, a 5tfi degree of 0.3 to 0.8% by weight is preferred. If it is less than 0.3% by weight, A! Membrane 4 of 5
This is because the degree of ifi becomes lower than necessary, and as a result, there is a possibility that Si is diffused from the substrate 2 and the above-mentioned aluminum spike occurs. - On the other hand, if Si is contained in excess of 0.8% by weight, the Si concentration in the AI film 4.5 will increase, resulting in an increase in contact resistance due to Si precipitation. .

次に、Al膜4,5の膜厚について考察する。Next, the thickness of the Al films 4 and 5 will be considered.

上記実施例において、第1段階Al膜4の膜厚は、全A
I膜に対して20%の厚さで形成されている。
In the above embodiment, the film thickness of the first stage Al film 4 is the total A
The thickness is 20% of that of the I film.

AI膜4は、基板2からのSiの拡散を防止する機能を
果たしている為、この機能を果たす上で十分な厚さを有
すれば足りる。具体的には、20〜50%の厚さである
ことが好ましい。一方このAI膜4の厚さから第2段階
Al膜5の厚さは、50〜80%であることが好ましい
Since the AI film 4 has the function of preventing the diffusion of Si from the substrate 2, it is sufficient if it has a thickness sufficient to fulfill this function. Specifically, the thickness is preferably 20 to 50%. On the other hand, it is preferable that the thickness of the second stage Al film 5 is 50 to 80% of the thickness of the AI film 4.

次に、1.5μmX1.5μmのコンタクトホール3が
形成されたSi基板に、1重量%のSiを含むAIを一
層で形成した比較例について、コンタクト抵抗を測定し
たところ、308Ωとなった。これに対し、同様に1.
5μmX1.5μmのコンタクトホール3が形成された
Si基板に上記実施例に基づいてAI膜を2層に形成し
た物についてコンタクト抵抗を測定したところ、30Ω
となった。この実験結果から、本実施例によれば、コン
タクト抵抗が改善されていることが分かる。
Next, for a comparative example in which a single layer of AI containing 1% by weight of Si was formed on a Si substrate in which a contact hole 3 of 1.5 μm×1.5 μm was formed, the contact resistance was measured and found to be 308Ω. On the other hand, similarly 1.
When the contact resistance was measured for a Si substrate in which a contact hole 3 of 5 μm x 1.5 μm was formed and two layers of AI film were formed based on the above example, it was 30Ω.
It became. From this experimental result, it can be seen that according to this example, the contact resistance is improved.

また、アルミスパイクの発生有無を、基板を横切断し顕
微鏡下で目視して調べたところ、アルミスパイクの発生
は観察されなかった。
Further, when the substrate was cross-cut and visually observed under a microscope to determine whether aluminum spikes were generated, no aluminum spikes were observed.

以上説明した実施例において、AI膜の形成を2段階に
行っているが、これに限定されず3段階以上でAl膜を
形成することも可能である。この時第2段階以降のAI
膜のSi1度は、第1段階Al膜のSi1度より低く形
成される。そして、第2.第3−  と進むにしたがっ
て、順次Si濃度を低くすることも可能である。
In the embodiments described above, the Al film is formed in two stages, but the invention is not limited to this, and it is also possible to form the Al film in three or more stages. At this time, AI from the second stage onward
The Si1 degree of the film is formed to be lower than the Si1 degree of the first stage Al film. And the second. It is also possible to sequentially lower the Si concentration as it progresses to the third stage.

上記実施例では、AI膜4.5の形成をスパッタリング
により行ったが、この他化学メツキ、CVD、真空蒸着
により行うことも可能である。
In the above embodiment, the AI film 4.5 was formed by sputtering, but it may also be formed by chemical plating, CVD, or vacuum evaporation.

以上説明した本発明方法は、バイポーラ集積回路、MO
3集積回路等種々の半導体装置に適用することが可能で
ある。
The method of the present invention described above applies to bipolar integrated circuits, MO
It is possible to apply the present invention to various semiconductor devices such as 3 integrated circuits.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明に係る半導体装置の製造方法
によれば、Al膜を形成する工程は、Si濃度の異なる
複数のAI膜を順次形成する工程から成り、第1段階の
Al膜形成工程は、前記熱処理温度におけるSi固溶度
よりも高い濃度のSiを含有するAI膜を形成するもの
であり、次段階のAI膜形成工程は、前記第1段階のS
i1度よりも低い濃度のSiを含有するAI膜を形成す
るものである為、Si基板とAl配線とのコンタクト抵
抗の増大を生ずることなくAIスパイクの発生を防止可
能な、半導体装置を提供することが出来る。
As explained above, according to the method for manufacturing a semiconductor device according to the present invention, the step of forming an Al film consists of the step of sequentially forming a plurality of AI films with different Si concentrations, and the first step of forming the Al film is is to form an AI film containing Si at a concentration higher than the Si solid solubility at the heat treatment temperature, and the next step of forming an AI film is to
To provide a semiconductor device which can prevent the occurrence of AI spikes without increasing the contact resistance between the Si substrate and the Al wiring because it forms an AI film containing Si at a concentration lower than i1 degrees. I can do it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例の工程を示す断面図である
FIG. 1 is a sectional view showing the steps of an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁膜が形成されたSi基板に開孔処理を行った
後、当該基板上にSiを含有したAl膜を形成し、次い
で熱処理をして成る半導体装置の製造方法において、前
記Al膜を形成する工程は、Si濃度の異なる複数のA
l膜を順次形成する工程から成り、第1段階のAl膜形
成工程は、前記熱処理温度におけるSi固溶度よりも高
い濃度のSiを含有するAl膜を形成するものであり、
次段階のAl膜形成工程は、前記第1段階のSi濃度よ
りも低い濃度のSiを含有するAl膜を形成するもので
ある、ことを特徴とする半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, in which a Si substrate on which an insulating film is formed is subjected to hole-opening treatment, an Al film containing Si is formed on the substrate, and then a heat treatment is performed. The step of forming a plurality of A
The first stage of the Al film forming step is to form an Al film containing Si at a higher concentration than the Si solid solubility at the heat treatment temperature,
A method for manufacturing a semiconductor device, wherein the next step of forming an Al film is to form an Al film containing Si at a lower concentration than the Si concentration in the first step.
JP27506588A 1988-10-31 1988-10-31 Manufacture of semiconductor device Pending JPH02121329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27506588A JPH02121329A (en) 1988-10-31 1988-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27506588A JPH02121329A (en) 1988-10-31 1988-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02121329A true JPH02121329A (en) 1990-05-09

Family

ID=17550351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27506588A Pending JPH02121329A (en) 1988-10-31 1988-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02121329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722412A (en) * 1993-06-23 1995-01-24 Nec Corp Al electrode wiring structure of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722412A (en) * 1993-06-23 1995-01-24 Nec Corp Al electrode wiring structure of semiconductor device

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