JPH02110895A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify the read-out operation of cell data and to eliminate a need of refresh operation by specifying a maximum interval between electrodes of ferroelectric capacitors. CONSTITUTION:When a maximum interval between electrodes of ferroelectric capacitors is made to (d) (cm) and a field intensity required by which spontaneous polarization of the ferroelectric is inverted and is scarcely changed is made to Et(v/cm), the value of the product (EtXd) is smaller than an about half of the difference between potentials corresponding to logical '1' and logical '0' of a bit line. Thus, a semiconductor memory which has the degree of integration in the same level as a conventional DRAM and does not require the refresh operation and can hold data with non-volatilization at the time of power-off and requires the read/write access time approximately equal to that of the conventional DRAM is obtained without considerably changing the circuit design and the process technique of the conventional DRAM.

Description

[Detailed description of the invention]

[Object of the invention] (Industrial application field) The present invention relates to a semiconductor memory using ferroelectric cells,
For example, the present invention relates to a semiconductor memory used in the field of semiconductor disks and image processing memory. (Prior Art) DRAM (dynamic random access memory) is conventionally a memory in which one information retention capacitor C1 and one charge transfer MOS transistor T1 are connected, as shown in FIG. It uses cells. In this memory cell, a constant cell plate voltage Vp is applied to the electrode at one end of the capacitor C1, and the word line WL
By setting transistor T1 (MOS) to high level and turning on transistor T1, capacitor C1 is connected from bit line BL to MO
S) Write charge through transistor f1 and write charge to word line W
By setting L to a low level and turning off the MOS transistor T1, the charge (data) in the capacitor C1 is held. As described above, DRAM is characterized by its simple cell structure and small cell area, and is most commonly used among semiconductor memories as a high-density storage element. However, a drawback of DRAM is that data is retained by the charge stored in the cell capacitor, so self-charge is lost due to leakage caused by various factors, such as subthreshold leakage of the two registers for charge transfer. There is. It is well known that in order to replenish the charge lost due to this leakage, a refresh operation must be performed at regular intervals to retain cell data. Further, DRAM is a so-called volatile semiconductor memory that can be read and written at high speed, but when the power is turned off, a refresh operation is no longer performed and the stored contents are lost. Efforts have therefore been made to research RAMs that can read and write at high speed, taking advantage of the high density of DRAM, and freeing them from the need for refresh and volatility when the power is turned off. In particular, a ferroelectric cell has recently been announced as an element with a memory function that is nonvolatile and allows data to be easily rewritten (Elcctron).
lcs/Pcb, 4.1988P, 32: Elcc
tron1cs/Pcb, 1g, 1988 P, 91-
P, 95). This ferroelectric cell is made of ferroelectric P Z T (Lead ZlrconaLe Tlt
data is retained by utilizing the spontaneous polarization characteristics of (anate). However, the method of applying this ferroelectric cell to RAM is to add extra elements to the SRAM cell, which reduces the cell area and
Even if the method is similar to DRAM cells, 2 bits per bit.
However, there are problems in that two cells are required and the cell data reading operation is complicated. (Problems to be Solved by the Invention) The present invention provides that the conventional method of applying a ferroelectric cell as described above to a RAM has problems such as a large cell area and a complicated cell data read operation. This was done in consideration of certain points, and it is possible to apply ferroelectric cells without significantly departing from conventional DRAM circuit design and process technology, eliminating the need for a refresh operation, and providing a nonvolatile semiconductor memory. The purpose is to [Structure of the Invention] (Means for Solving the Problems) The present invention provides an 11-conductor memory having a sense amplifier system that detects and amplifies potential changes in bit line pairs caused by memory cells. , the potential of one electrode of a ferroelectric capacitor having a structure in which an electric body A is sandwiched between capacitor electrodes is equal to the logical "1" of the bit line.
and “fixed at approximately the middle level of the potential corresponding to 0°,
A charge transfer transistor is connected between the other electrode of the ferroelectric capacitor and the bit line, and the maximum distance between the electrodes of the ferroelectric capacitor is d (cm), and the spontaneous polarization of the ferroelectric material is When the strength of the electric field required to invert and hardly change is expressed as Et (v/crn), the value of Et×d or the logical “1” of the bit line
It is characterized in that the difference between the potentials corresponding to and "O" is approximately less than ten minutes. (Function) The bit line pair is equalized to a level approximately equal to the cell plate potential level until the cell data access starts at 15:1, and the bit line pair is equalized to a level approximately equal to the cell plate potential level until the cell data access starts at 15:1. Immediately before turning on the transistor and the charge transfer transistor of the reference cell,
It is set to a level near one of the two power supply levels of Vcc, bt, and VSS'h. After that, the 715 m transfer transistor of the memory cell and the charge transfer transistor of the reference cell connected to the bit line paired with this memory cell are turned on, and the reference level is set to one bit line by the reference cell. A data level based on the data of the memory cell is generated on the other bit line. After this, conventional DR
Same as AM 1. As a measure, the level of this bit line pair is sense amplified. During a write operation, data can be written in the same way as in conventional DRAMs. (Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. Figure 1 shows a semiconductor memory that uses a sense amplifier system that senses and amplifies potential changes in bit line pairs caused by memory cells, such as a conventional DRA, M memory that has a ferroelectric capacitor in its cell data sense system. A part of a memory employing cells and reference cells (a portion corresponding to one column of a memory cell array r in which cells are arranged in rows and columns is representatively taken out) is shown. Here, BL and BL are bit line pairs, MC. and MC3 are memory cells connected to one bit line BL, MC2 and MC, , are memory cells connected to the other bit line B
Memory cells connected to L, WLi and WL2 are word lines connected to the gates of charge transfer transistors T1 and T3 of memory cells connected to one bit line BL, and WLI and WL2 are connected to the other bit line BL. The word line REF, which is connected to the gates of the charge transfer transistors T2 and T4 of the memory cells connected to the line BL, is a reference level that generates a reference level for the read level of memory cell data and supplies it to the bit line pair. A generation circuit, PR is a bit line precharge circuit, SA is a sense amplifier that detects and amplifies the potential change of the bit line pair, DQ and DQ are the data line pair, G and G.
Reference numeral 2 designates a bit line selection transistor connected between the bit line pair and the data line and whose switch is controlled by a column selection signal C5L. As shown in FIGS. 2(a) and 2(b), each of the memory cells MC and MC4 has a structure in which a ferroelectric material 20 is sandwiched between capacitor electrodes 2 and 22 made of a conductive material such as metal, The potential VPF of one electrode (cell plate) is approximately the middle level potential between the potential V11 corresponding to the logical “1” of the bit line and the voltage V1 corresponding to the logical “0” (Vll+V1,)/ A ferroelectric capacitor CF fixed at 2 is connected between the other electrode of the ferroelectric capacitor CF and one bit line BL or the other bit line BL, and the gate is connected to the word line WL. It consists of a charge transfer transistor TF. Maximum distance d (cm) between electrodes of ferroelectric capacitor CF
is made below a certain value, as described below. The reference level generation circuit REF has approximately 1 of the ferroelectric capacitor CF of each memory cell MC, -MC4.
Two reference ferroelectric capacitors having an area and a capacitance of /2, and two ? A reference cell consisting of a LL load reverse transfer transistor is used, and its details will be described later. Here, the properties of ferroelectric material are shown in FIG. The horizontal axis represents the external electric field applied to the ferroelectric material, that is, E (v/cm) = V (v) when a voltage of V (v) is applied between the electrodes 21 and 22 of the ferroelectric capacitor. /d (cm), the vertical axis is the spontaneous polarization P, which is a little over 55, and the relationship between P and E of the conductive material has a so-called hysteresis relationship. Now, let us consider the case where an electric field is applied from a state where the polarization domains of the ferroelectric material are discrete and do not exhibit polarization as a whole. First, as E increases in the positive direction, the polarization becomes O
It increases from to A. Polarization is like A, and deafness is caused by a tome with polarization in a certain direction.
The polarization hardly increases. The electric field at this time is expressed as Et. After this, even if E is reduced to zero, Ps is maintained even though the polarization becomes zero.If E is further increased in the opposite direction, the polarization changes from A according to the curve 41 in the figure. Changes to B. In the state where the polarization is B, there are only domains having polarization in the opposite direction to the state where the polarization is A, and the polarization hardly increases. The electric field at this time is represented by -Et. When E is increased again, the polarization changes from B to A according to the curve 42 in the figure. At this time, even if E is made zero, the polarization does not become zero and -Ps is maintained. As mentioned above, when a voltage that generates an electric field Et is applied to a strong conductive capacitor in which a ferroelectric material is sandwiched between electrodes,
Thereafter, even if the electrode is placed in a tf free state, the direction of polarization is maintained as spontaneous polarization. The surface charge of the ferroelectric material due to this spontaneous polarization does not disappear spontaneously due to leakage, etc., and unless an electric field in the opposite direction is applied and the polarization becomes zero, the direction of the polarization caused by the electric field Et is maintained and its value remains approximately 1 Psl. By the way, the maximum distance d (cm) between the electrodes of the ferroelectric capacitor shown in FIG. It must be set so that the direction of polarization of the ferroelectric material can be reversed by the potential Vl. That is, when the cell plate potential is expressed in VPF, it must be determined so as to satisfy Vll-VPF=VPF-VLz(Vll+VL)/2>Etxd. Here, E

[ is a field determined by the ferroelectric material used, and is the magnitude of the electric field sufficient to reverse the direction of polarization and saturate the value. For example, E t -100 (1v/cm, Vll-5
v, Vl, -0v then Vl) F-2,5v, so d<2,5v÷1000 v/cm -25B
It should be m. By setting the interelectrode spacing d in this way, it is possible to control the switch so that the polarization points in opposite directions when Vll is applied to the bit line and when VL is applied, and moreover, a forced reversal occurs. The spontaneous polarization is maintained as constant data until the polarization is stopped. be able to. Next, a specific structure of a memory cell having a ferroelectric capacitor as shown in FIG. 2(a) will be described. In a ferroelectric material, the direction of polarization changes only in the area where an electric field is applied. That is, since the polarization of that portion changes to a single domain structure, the polarization state of the partial portion can be changed even in a continuous ferroelectric layer. Therefore, FjI can be used in the same way as the oxide film of a conventional DRAM memory cell, and can maintain data in a non-volatile manner as a polarized state. What we must be careful about with nonvolatile memory is that the proportion of the diffusion layer of the node directly connected to the memory cell electrode must be as small as possible (to reduce coupling with the substrate potential level). If this coupling is not reduced, noise that reverses the spontaneous polarization may be generated in the memory cell via the substrate potential level when the power is turned on and off. The planar pattern and cross-sectional structure of the cell are shown in FIGS. Polysilicon, which is a first conductive layer that will become the gate electrode (and word line) 4 of the charge transfer transistor, is patterned on the substrate surface via a gate insulating film 3. Next, this gate 7u pole 4 is formed by patterning. An impurity diffusion layer region 5.5' that becomes the source or drain of the charge transfer transistor is formed as a mask, and an insulating layer 6 such as an oxide film is further formed on the substrate. After a contact hole is formed to reach the impurity diffusion layer region 5 which becomes the source (or drain) of the charge transfer transistor, a second conductive layer of polysilicon is formed on the insulating layer 6. 7 is deposited to make a conductive contact to the impurity diffusion layer region 5, and this polysilicon 7 is patterned into islands to form one electrode 7 of an independent ferroelectric capacitor as each memory cell. Next, a ferroelectric layer 8 common to the eight memory cells is formed on the substrate, and a third conductive layer, polysilicon 9, is deposited on top of the ferroelectric layer 8. The body layer 8 is patterned to form another electrode (plate electrode) 9 of the ferroelectric capacitor in common to each memory cell. The ferroelectric layer located at After a contact hole is formed to reach the other impurity diffusion layer region 5', a fourth conductive layer 11 of aluminum, polysilicon, or a composite film of polysilicon and silicide is formed on this interlayer insulating layer 10. is deposited to make a conductive contact to the impurity diffusion layer region 5', and this fourth conductive layer 11 is patterned to form a bit line 11. In this way, a memory cell with a ferroelectric capacitor is realized that has a structure that is almost the same as the stacked memory cell structure of conventional DRAM, so the area occupied by the memory cell is small and the degree of integration is low. is almost the same as conventional DRAM. Next, the RA that combines the sense system configured as described above is
The sensing operation of memory cell data in M will be explained. First, the amount of charge movement between the memory cell and the bit line will be explained. Figures 6 (a) and (b) schematically show the potential of each part in the initial state before the memory cell is connected to the bit line and in the final state (selected state) after it is connected. It is something. The potential of the cell plate of the ferroelectric capacitor CF of the above memory cell is VPI', and the data written in this memory cell is "O" or "0".
1 degree, the potential Vi of the opposing 71i1-m (electrode connected to the charge transfer transistor) is as follows: VL≦Vi≦VPl The frame is VPF≦V i ≦Vl
It becomes l. This means that when the written data is "O", first Vi=V1. After that, the charge transfer transistor is weakly turned on so that the state becomes Vi-vpp unless this memory cell is accessed for a long time, except during the read period. This is because vi becomes an intermediate level between VL and VPF depending on the interval. Similarly, when the written data is “1”, Vi-
In order to create a spontaneous polarization corresponding to "1" as Vll by k·l, vi can take an intermediate level between VII and VPF. Note that the reason why the final value is set to Vi-VPP is that if the electrode is left in a completely t9 free state, the charge will leak to the destination (for example, leak to the substrate potential level). This is because, depending on the situation, the potential of the electrode may reverse the written spontaneous polarization. Now, the initial level of the bit line capacitance cB is VSS. When the magnitude of spontaneous polarization is represented by PS, the opposing area of ferroelectric capacitor CF is represented by A, and its capacitance is represented by C, the bit line in the final state (selected state) after the memory cell is connected to the bit line is FIG. 6(b) shows potential Vf corresponding to Vt.
It is shown in When the written data is “0”, Vf = C-Vi/ (C + CB), and when the written data is “]”, Vf
-2Φ A -Ps / (C+CB)+C
−V i/(C+C11). In other words, for a memory cell in which the written data is "0" and a memory cell in which the written data is "1", the minimum Vf in 1 is 2・A・Ps/(C+C
I3) difference exists. Therefore, the level VI? shown in FIG. 6(b) is used as the reference level for "0" and "1". If IEL can be set, the data in the memory cell can be sensed regardless of Vi. On the other hand, if the bit line potential before reading 15 is V13 or V
cc, Vf in the final state (selected state) is shown in FIG. 6(b), and CO#Vcc/
(C+CB) is added. Next, the operation of creating the reference level will be explained with reference to FIGS. 7(a) and 7(b). Figures 7(a) and (b) are the references shown in Figure 3.
This diagram schematically shows the potentials of various parts of the nonce level generating circuit REF in the initial state before the reference cell is connected to the bit line and in the final state (selected state) after the connection. The two reference ferroelectric capacitors DCA and DCB of the reference cell each have an area A/2 and a capacitance c/2, which are approximately half of the ferroelectric capacitor CF of the memory cell. Then, the cell plate potential of one reference ferroelectric capacitor DCA is set to VPF (ferroelectric capacitor CF of the memory cell).
), and the cell plate potential of the other reference ferroelectric capacitor DCB is Vp (same as the cell plate potential of
ec potential or Vss potential). Further, the potential corresponding to Vi in FIG. 6 is set to VPP. Depending on whether the bit line potential VB before reading is Vss or Vcc,
- The initial state of the reference ferroelectric capacitor DCA is set as shown in FIG. 7(b). That is, at VB-VssO, the one reference ferroelectric capacitor DCA is set to "1". At Vll-VCC, one of the reference ferroelectric capacitors D
Write “0” to CA. In addition, in the initial state of the reference strong:A electric capacitor DCB, the potential of the counter electrode is VPII', so in Vp-VCC, "Q" vp
-vss is '1#. When the reference cell is connected to all bits, the reference ferroelectric capacitor DCB is connected so that the bit line potential VB before reading is Vs.
Since the cell plate potential is Vp regardless of whether it is at the level s or Vcc, the ferroelectric's “Oo”1
” does not change.Then, in the reference ferroelectric capacitor DCB, the bit line potentials V13 and VP
The relationship with P is set at such a level that when the reference cell is connected to the bit line, its contents are inverted, so that the final state f! after the reference cell is connected to the bit line is ! 5 (selected state), when the bit line potential VB before reading is Vss, V f =A-Ps/(C+CB)+C-VPI
ko/(C→-CB). This corresponds to the reference level VRI:P shown in FIG. 6(b). On the other hand, even when the bit line potential VB before reading is VCC, Vf is C to V REI' in FIG. 6(b).
The bit line potential VB before reading, which is the sum of B-VCC/(C+CB), becomes the reference level when VCC is VCC. As the reference level generation circuit REF for generating the reference level described above, a third configuration is provided which corresponds to the case where the bit line potential VB before reading becomes VSS.
Shown in the figure. That is, one reference cell RC and RC are connected to the bit lines BL and BL, respectively, and a bit line level set circuit LS is connected to the bit line pair. The reference cell RC connected to the bit line BL is connected to the ferroelectric capacitor CF of the memory cell.
Two reference ferroelectric capacitors (DC, and DC2
) and charge transfer transistors (DTl and DT2) respectively connected between one electrode of each of the two reference ferroelectric capacitors and one bit line BL. Similarly, the reference cell RC connected to the other bit line BL has two reference capacitors having an area A/2 and a capacitance C/2, which are approximately 1/2 of the 71i body capacitor CF of the memory cell. Dielectric capacitor (DC3
and DC, , ), and the charge transfer transistors (DT3 and It consists of DT,, ). Then, two '' connected to one bit line BL
15 d:j transfer transistors (DT and DT2
) is supplied with a dummy word line signal from the dummy word line DWL, and these two 733Q transfer transistors (DT and DT
2), the other electrodes of the reference ferroelectric capacitors (DC and DC2) respectively connected to the VSSSS electric wire and the logical "
The potential VB corresponding to "1" and the potential Vl corresponding to "O"
, which is approximately the intermediate level potential (VII+VL)/2. The spontaneous polarization of the reference ferroelectric capacitor DC2 to which the intermediate potential is applied is set in such a direction that it is inverted when the charge transfer transistor DT2 connected thereto is turned on during data sensing. A reference ferroelectric capacitor DC2 and a charge transfer transistor D are provided with the intermediate potential.
1 between the connection node Nd with T2 and the Vcc7ti level.
A reset transistor DS1 is connected to reset the potential of the connection node Nd every memory cycle, and a reset signal DC3T is applied to the gate of this transistor DS from a reset line. Similarly, a dummy word line signal is applied from the inverted dummy word line DWL to each gate of the two charge transfer transistors (DT3 and DT4) connected to the other bit line BL. The other electrodes of the reference ferroelectric capacitors (DC3 and DC4) connected to these two charge transfer transistors (DT and DT4) respectively are at the intermediate level potential and the Vss potential. The spontaneous polarization of the reference ferroelectric capacitor DC3, which is fixed at It is set. A reference ferroelectric capacitor DC3 and a charge transfer transistor D are provided with the intermediate potential.
At 1111 between the connection node Nd with T and the VCC potential,
A reset transistor DS2 is connected to reset the potential of the connection node "1" every memory cycle, and a reset signal DC8T is applied to the gate of the transistor DS2 from the reset line. Next, the operation of the memory having the cell data sense system shown in Fig. 1 will be explained with reference to the operating waveforms shown in Fig. 8 and the reference level generation circuit REF shown in Fig. 3. First, an outline of the operation will be described. The bit line pair is equalized to a level approximately equal to the level of the cell plate potential VPP until access of memory cell data is started, and when access is started, the charge transfer transistor of the memory cell and the reference cell are equalized. Immediately before the charge transfer transistor turns on, a level near one of two power supply levels, VCC potential and VSS potential (in this example,
ss potential). After that, the charge transfer transistor of the memory cell and the reference cell (J transfer transistor) connected to the bit line paired with this memory cell are turned on, and one of the reference cells is turned on. The spontaneous polarization of the dielectric capacitor is reversed to generate a reference level on one bit line, and a data level based on the data in the memory cell on the other bit line.After this, the conventional D
Similar to RAM, the level of this bit line pair is sense amplified. Next, the above operation will be explained in detail. Consider the case where word line WLI rises and memory cell MC is accessed. Before access starts, the dummy word lines DWL and DWL are each at "H" level, the charge transfer transistor DT+-DT4 of the reference cell is fully turned on, and all the word lines WL1, WLl, wL2.
...are charge transfer transistors T1 to T4 of memory cells
The level is such that it turns on. Further, the BLP signal is at "H" level, transistors P1 to P3 of the precharge circuit PR are on, and the bit line BL
and BL are each a VPP novel. Therefore, the potentials of the reference ferroelectric capacitor DC2 and the bit line side electrodes of DC (the connection notes Nd and Nd) are respectively VPP. The potentials of the bit line side electrodes of the memory cell ferroelectric capacitors C and -C4 are each at a level approximately close to vpp. Therefore, the reference ferroelectric capacitors DC and DC4 whose cell plate potential is VSS are each set at 1 m. Furthermore, the reference ferroelectric capacitors DC2 and DC3 whose cell plate potential is VPP are set to "1" at the end of the previous access. Now, when the address is decided and access is started, first, the dummy word lines DWL, DWL and all the word lines WL1, wLl, wL2... become the Vss level, and the charge transfer transistors DT of the reference cells, ...
DT, and i-transistor T for charge transfer of memory cells.
1 to T1 are turned off. After that, the BLP signal falls and the precharge circuit P
The transistors P1 to P of R are turned off, and the bit lines BL and BL are respectively set to VPI! separated from the level. Next, the BLST signal rises, transistors 5I-83 of the bit line level set circuit LS are turned on, and the bit lines BL and BL are each set to a level for detecting cell data. In this example, bit lines BL and BL are set to VSS level. After that, when the BLST signal falls, only the word line WLI and dummy word line DWL rise to transfer data to the bit lines BL and BL, and the charge transfer transistor T1 of the memory cell and the charge transfer transistor of the reference cell The transistors (DT and DT,) are fully turned on. The data transfer levels to the bit lines BL and BL are as shown in FIGS. 6 and 7, and a level difference of approximately A-Ps/(C+CB) occurs between the bit lines. Therefore, as a ferroelectric capacitor, the larger the area A, the larger the spontaneous polarization Ps of the ferroelectric, the smaller the bit line capacitance CB, the larger the amount of data transfer.
The difference from AM is that the cell capacity should be smaller. In this case, area A cannot be reduced, so
It is better to make the ferroelectric material thicker as long as the conditions for reversing the spontaneous polarization Ps allow. In addition, sense amplification after data is transferred to the bit lines BL and BL is similar to the conventional general RAN1, but the level of the bit lines BL and BL (-1 deviation may also be on the VSS side). Therefore, in the sense amplification in this embodiment, the SEP signal is first raised, sense is performed toward the VCC side by the PMO8I transistors SP1 and SF3 of the sense amplifier SA, and then the SE
N, and the level of the bit line on the Vss side is secured by NMO8) transistors SN and sN2. After the level difference between the bit line pair is sufficiently amplified, the selected CSL signal rises and transistors G and G2
is turned on, data is transferred to data lines DQ and DQ via transistors G1 and G2, and reading is completed. Next, the process begins to create an initial state for the next cycle. First, the word line WLI that had been up until now
and dummy word line DWL rises. After that, S.E.
The P signal rises, the 5EN1° signal also rises, the sense amplifier SA is reset, and at the same time the DC8T signal rises, transistors DS and DS2 are turned on, and the connection notes Nd and Nd become almost at the vec level. After the reference ferroelectric capacitors DC2 and DC3 whose previous cell plate potential is VPP are each written and set to the "1" state, the DC3T signal falls. During this time, the BLP signal rises, transistors p and -p are turned on, and bit lines BL and BL are precharged and equalized to VPF, respectively. When this equalization φ precharge is completed, dummy word lines DWL, DWL and all word lines WL1,
The levels of WL1, WL2, . . . are raised to lead the electrodes of the memory cells to the VPP level. At this time, the dummy words 1DWL and DWL are sufficiently raised, and the reference ferroelectric capacitor D is
It is necessary to keep the electrodes of C, ~DC1 the same as VPF, but for the memory cell, the voltage 6:j transfer transistors T1 to T4 compensate for the cell electrode leaking to nodes other than ■PF, It is sufficient that the charge transfer transistor T of the memory cell is turned on slightly so that an electric field that reverses the spontaneous polarization is not applied to the cell.
The word line WL to a level approximately equal to the threshold voltage VTH of 1 to T4.
1, WLl, WL2, etc. may be raised slowly. By doing this, all word lines WLI, WLI
, WL2, . . . power and current peaks when raising the levels can be minimized as much as possible. Therefore, when access is repeated in the minimum number of cycles, the charge transfer transistors T1 to T6 of the memory cells. may not turn on. Therefore, when the cycle is long, in other words, when the period during which the bit line pair is equalized to the intermediate level potential is long before memory cell data access is started, the memory self electrode leaks. Make up for VP
Protect the cell data from being destroyed by setting the charge transfer transistor of the memory cell to the on state (1) to keep it near the F level and prevent the ferroelectric spontaneous polarization from reversing. It becomes possible to do so. Above, we have explained the read operation when the VSS method is adopted when the bit line potential VB before reading becomes VSS, but when the Vcc method is adopted when the bit line potential before reading becomes V13 or Vec. (1) BLS
In order to set bit lines BL and BL to a level near VPF by transistors S and -S3 controlled by TfJ, one end of each of transistors S1 and S3 is connected to VCC potential, (2) DC8T
Transistors DS and DS2 controlled by signals
In order to write "0" into the reference ferroelectric capacitors DC2 and DC'4, one end of each of the transistors DS and DS2 must be connected to the VSS potential, and (3) the sense amplifier SA must be operated. PMO for
This differs from the case where the VSS method is adopted in that the operating order of the S transistors sp and SF3 and the NMOS transistors SN1 and SN2 is reversed from the above. Note that writing data into the memory cell is exactly the same as in a conventional general RAM, so a description thereof will be omitted. The above has explained the operation of data sense amplification, and in order to function as a nonvolatile RAM,
If sufficient attention is not paid to the order in which internal signals are set and reset when the power is turned on and off, the contents of the ferroelectric capacitor may be rewritten by a transient voltage. In particular, the cell plate level and the bit line pair level VPF are large depending on the load and change slowly when the power is turned on and off. Therefore, it is necessary to set a certain order for the VPF level and the timing at which the word line should be activated. That is, if the word line becomes active before the cell plate level and the level of the bit line pair reach VPP, the contents of the cell may be destroyed. FIG. 9 conceptually shows the order in which the levels of the δ node are raised when the power is turned on. Here, the cell plate level detection circuit 91 is a circuit that monitors the cell plate level, and the output vp is "L" when the power is turned on, but when the cell plate level reaches approximately VPP, the output Vp becomes "H".
''. The bit line precharge level detection circuit 92 is a circuit that monitors the potential level of the bit line, and the output VB is "L" when the power is turned on, or the BLP signal rises when the power is turned on. When the bit line begins to be precharged and its level reaches approximately VPP, VB goes to 'H.
The above two signals vp and vn are subjected to AND processing by the AND gate 93, and for the first time, the output of the word line level generation circuit 94 and the output of the dummy word line level generation circuit 95 are ANDed. It goes out to the word line and dummy word line through the gates 96 and 97, and the bit line side electrodes of the memory cell and reference cell change to VPI'.Until this time, the charge transfer transistor is off, so The above-mentioned bit line side electrode is in an lf-free state, and no electric field is applied to the ferroelectric material of the ferroelectric capacitor to the extent that its spontaneous polarization is reversed. Only after the level of the word line rises properly and the level of the bit line side electrode of the reference cell properly reaches VPP can the AND gate 98 accept external signals for memory control and generate internal signals. It becomes possible to access the cell without accidentally performing sensing. In other words, by the sequence of rising the potential level of each electrode node when the power is turned on, the cell plate level and the level of the bit line pair can be changed. Only when the output is sufficient can the transistor for charge transfer between the cell and the bit line turn on, and after that it can accept external signals for memory control and generate internal signals. Sensing of cell data becomes possible.When the power is turned off, the memory cell and reference cell must be completely disconnected from the bit line before the bit line level and cell plate level are turned off. A transient voltage that reverses the polarization occurs.In other words, the cell plate level VPF and the NMOS transistor S of the sense amplifier SA
It is necessary for the drive signal SEN of N and SN2 to follow changes in VCC with a sufficient time constant. The circuit configuration of this tank is schematically shown in FIG. Here, since VPF, which is the output of the cell plate level generation circuit] 01, and SEN, which is the output of the SEN level generation circuit 102, have sufficiently large capacitance as shown by the dotted line, they are connected to vec or VSS. Even if it is off, direct V
As long as the charge does not flow in the CC direction, it will discharge slowly enough and the level will drop. For this purpose, a diode 103 is inserted between the two level generation circuits 101 and 102 and the VCC node. As a result, the SEN output and the VPI' output are turned off by the circuit's own time constant, and after the word line level generation circuit 94 and the dummy word line level generation circuit 95 in FIG. 9 are turned off immediately after the power is turned off. Since it is turned off with sufficient time, the cell will not be destroyed. That is, due to the above-described sequence of raising the potential level of each electrode node when the power is turned off, each output of the cell plate level generation circuit and the sense amplifier drive level generation circuit receives an external signal for memory control and outputs an internal signal. After the circuit that generates the signal and the circuit that generates the signal that turns on the charge transfer transistor are turned off, it is completely turned off. In addition, in the above embodiment, the reference ferroelectric capacitor between the two reference cells has been described as having a capacitance approximately half of the capacitance of the ferroelectric capacitor of the memory cell. Strong: A
It is not necessary to have a capacitance that is approximately 1/2 of the capacitance of an electric capacitor, and the amount of polarization inversion corresponding to the difference from the capacitance of the ferroelectric capacitor of the memory cell can be obtained. Further, in the above explanation, an example was shown in which the two reference ferroelectric capacitors of the reference cell are each connected to one bit line via separate charge transfer transistors, but the present invention is not limited to this. As shown in Figure 11, two reference ferroelectric capacitors (DCI and DC2) are connected to one bit line BL through one charge transfer transistor DT, and similarly, two
Even if two reference ferroelectric capacitors (DC3 and DC, . . . ) are connected to the other bit line BL through one charge transfer transistor DT3, the same operation and effect as described above can be achieved. is obtained. [Effects of the Invention] As described above, according to the present invention, by configuring a RAM in the circuit system as described above using cells having ferroelectric capacitors having a predetermined structure as described above, It has the same level of integration as the DRA ki of
Moreover, refreshing is also an important factor, and semiconductor memory, which can hold data non-volatilely when the power is turned off and has read/write access times on par with conventional DRAM, is different from conventional DR.
This can be achieved without departing significantly from AM circuit design and process technology. Therefore, the semiconductor memory of the present invention is
It is very effective in the field of semiconductor memory as a replacement for magnetic disks.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a cell data sensing system of a conductive memory according to an embodiment of the present invention, and FIG. 2(a) is an equivalent circuit diagram of a memory cell having a ferroelectric capacitor in FIG. Circuit diagram, FIG. 2(b) is a cross-sectional view showing a 1M structure of the ferroelectric capacitor in FIG. 2(a), FIG. 3 is a circuit diagram showing an example of the reference level generation circuit in FIG. Figure 4 is a characteristic diagram showing the relationship between ferroelectric polarization and electric field, and Figure 5 (
Fig. 5(b) is a sectional view taken along line 3-B of Fig. 2(a), Fig. 6(a) and (b) is a diagram shown to explain method b of reading data from the memory cell in FIG. FIG. 8 is a waveform diagram showing the operation of the cell data sense system in FIG. Fig. 10 is a diagram shown to explain a method of resetting the output of the cell plate level generation circuit and the output of the SEN level generation circuit when the power is turned off, and Fig. 11 is a modification of the reference level generation circuit shown in Fig. '3. FIG. 12 is an equivalent circuit diagram of a conventional DRAM memory cell. lvl C, ~MC4...Memory cell, C, -C,.
...Memory cell ferroelectric capacitor, T, -T4...
・Mepricell charge transfer transistor, RCSRC...
Reference cell, DC, ~D C, ...Reference cell strength, conductive capacitor, DT, ~D T ,
,...Reference cell charge transfer transistor, W
L. WLl, WLl, WL2...word line, DWL. DWL...Dummy word line, BL, BL...Bit line, SA...Sense amplifier, sp, ~SP3...PMOS transistor of sense amplifier, SN, ~SN,...
- NMO of sense amplifier 3) transistor, PR... precharge circuit, LS... bit line level set circuit, 1... semiconductor substrate, 4... word line, 7... second conductor "J ( Ferroelectric capacitor electrode), 8...
Ferroelectric layer, 9... Third conductive layer (cell plate electrode of ferroelectric capacitor), 11... Bit line, 20...
・Ferroelectric material, 21.22...Electrode of 7IS body carrier bank, 91...Cell plate level detection circuit c)
2...Bit line precharge level detection circuit, 93
．． 96.97.98...AND gate, 94...Word line level generation circuit, 95...Dummy word line level generation circuit, 101...Cell plate level generation circuit,
102...5EN (sense amplifier drive signal) level generation circuit, 103...diode. Out Y1fi agent Patent attorney Suzu 11 Take 1 Hodai Figure Figure LST (a) (b) Figure PF VSS PF VSS Figure 11 ■P PF 5S (b) Figure

Claims (10)

[Claims] (1) In a semiconductor memory having a sense amplifier system that detects and amplifies potential changes in a bit line pair caused by a memory cell, the memory cell is a ferroelectric capacitor having a structure in which a ferroelectric material is sandwiched between capacitor electrodes. The potential of one electrode of the ferroelectric capacitor is fixed at a level approximately midway between the potentials corresponding to logical "1" and "0" of the bit line, and a voltage is set between the other electrode of the ferroelectric capacitor and the bit line. A charge transfer transistor is connected, and the maximum distance between the electrodes of the ferroelectric capacitor is set to d (cm).
), when the strength of the electric field required to reverse the spontaneous polarization of the ferroelectric material so that it hardly changes is expressed in Et (v/cm), the value of Et x d is the logic of the bit line. “
A semiconductor memory characterized in that the difference between potentials corresponding to 1 and "0" is less than approximately half. (2) The structure of the memory cell is such that a first conductive layer, which becomes the gate electrode (and word line) of the charge transfer transistor, is formed by patterning on the substrate surface of the element region of the semiconductor substrate via a gate insulating film. An insulating layer is formed on the gate electrode and the substrate, and a second conductive layer is patterned into islands on the insulating layer to form one electrode of an independent ferroelectric capacitor for each memory cell. At the same time, a conductive contact is made through the contact hole formed in the insulating film to the impurity diffusion layer region of the substrate which becomes the source (or drain) of the charge transfer transistor, and each layer is formed on the second conductive layer. A ferroelectric layer common to the memory cell and a third conductive layer are sequentially deposited and patterned to form the other electrode of the ferroelectric capacitor (
a plate electrode) is formed, an interlayer insulating layer is formed on this third conductive layer and on the substrate, and a fourth interlayer insulating layer is formed on this interlayer insulating layer.
A conductive layer is patterned to form a bit line, and the conductive layer is conductive to the impurity diffusion layer region of the substrate which becomes the drain (or source) of the charge transfer transistor through the contact hole formed in the interlayer insulating layer. 2. The semiconductor memory according to claim 1, wherein a contact is made between the semiconductor memory and the semiconductor memory. (3) In the reference level generation circuit that generates a reference level for a read level of data of the memory cell onto a bit line, a reference cell is connected to each bit line of the bit line pair, and the reference cell is configured to: 2. The semiconductor memory according to claim 1, wherein two reference ferroelectric capacitors are connected to one of the bit lines of the bit line pair via a charge transfer transistor. (4) The two reference ferroelectric capacitors each have substantially the same structure as the ferroelectric capacitor of the memory cell, and have approximately 1/2 the area and capacity of the ferroelectric capacitor of the memory cell. 4. The semiconductor memory according to claim 3, further comprising: (5) One of the two reference ferroelectric capacitors has a counter electrode facing the electrode on the charge transfer transistor side fixed to the potential of the power supply level, and the other capacitor is the one for charge transfer. A counter electrode opposite to the transistor side electrode is connected to the logical “” of the bit line.
The charge transfer transistor is fixed to a potential approximately at an intermediate level between the potential corresponding to "1" and the potential corresponding to "0", and when data is sensed in the memory cell, the charge transfer transistor is turned on and the capacitor is connected to the bit line. When connected, the ferroelectric spontaneous polarization of one capacitor with a counter electrode fixed at the potential of the power supply level is not reversed, and the polarization of the other capacitor with the counter electrode fixed at the potential of the intermediate level is reversed. Claim 4, wherein the ferroelectric spontaneous polarization is set in advance so that the dielectric spontaneous polarization is reversed.
The semiconductor memory described. (6) The bit line pair is at a potential approximately at an intermediate level between the potential corresponding to the logical "1" and the potential corresponding to the logical "0" of the bit line until access of memory cell data is started. The electrode of the reference ferroelectric capacitor in the reference level generation circuit on the charge transfer transistor side is also set to the intermediate level potential, and when access starts, charge transfer of the memory cell is performed. Immediately before the charge transfer transistor and the reference cell charge transfer transistor turn on, the potential of the bit line pair is set near the power supply level, and then,
The charge transfer transistor of the memory cell and the charge transfer transistor of the reference cell connected to the bit line paired with this memory cell are turned on, and one bit line of the bit line pair is connected to the memory cell. The bit line is configured such that a potential change occurs depending on the data, and the spontaneous polarization of one of the two reference ferroelectric capacitors is inverted to cause a potential change as a reference level on the other bit line. 6. The semiconductor memory according to claim 5, characterized in that: (7) When the power is turned on, after the intermediate level as a fixed potential applied to one electrode of the ferroelectric capacitor of the memory cell and the intermediate level applied to the bit line pair are determined, the memory cell The charge transfer transistor in the cell and the charge transfer transistor in the reference cell can be turned on, and it is only in this state that external signals for memory control are accepted, internal signals are generated, and memory cell data is accessed. 7. The semiconductor memory according to claim 6, wherein the semiconductor memory is configured as follows. (8) When the power is turned off, after the circuit that receives an external signal and generates an internal signal and the circuit that drives the charge transfer transistor are completely reset, apply a voltage to one electrode of the ferroelectric capacitor of the memory cell. A circuit that generates the intermediate level as a fixed potential applied to the bit line pair and the intermediate level potential applied to the bit line pair, and a sense drive signal generating circuit that detects and amplifies the level of the bit line pair are completely turned off. 7. The semiconductor memory according to claim 6, wherein the semiconductor memory is configured as follows. (9) When the period in which the bit line pair is equalized to the intermediate level potential is long until access of memory cell data is started, the charge transfer transistor of the memory cell is set to an on state. 7. The semiconductor memory according to claim 6, wherein the semiconductor memory is configured as follows. (10) Of the two reference ferroelectric capacitors, one of the capacitors, the opposing electrode of which is fixed at the potential of the intermediate level, has an electrode on the charge transfer transistor side connected to a power supply via one transistor. 6. The semiconductor memory according to claim 5, wherein the semiconductor memory is connected to a level potential.