JPH0155473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an automatic rhythm performance device for an electronic musical instrument such as an electronic organ.

Conventionally, this type of automatic rhythm performance device was
In addition to providing a rhythm pattern memory that stores rhythm patterns as instrument-specific drive data (binary logic data) for each rhythm instrument for each rhythm, a rhythm sound source circuit that generates an instrument sound signal for each rhythm instrument is provided, and a tempo signal calculation system is provided. There is a system in which musical instrument drive data of a predetermined rhythm is sequentially read out from the rhythm pattern memory in accordance with the numerical values, and the rhythm sound source circuit is driven by this musical instrument drive data.

By the way, in an actual rhythm performance, the method of playing the rhythm instruments (percussion instruments) changes slightly depending on the rhythm tempo, so if the rhythm tempo differs, the musical instrument sounds generated by each rhythm instrument will naturally differ. However, in the above-mentioned conventional automatic rhythm performance device, changing the rhythm tempo only changes the time interval of the generated instrument sounds, but does not change the instrument sounds themselves (i.e. pitch, timbre, envelope, etc.). The problem was that it was not as effective as actual rhythm performance.

In view of the above circumstances, the present invention provides an automatic rhythm performance device in which when the rhythm tempo is changed, the generated musical instrument sound is also changed according to the change in the rhythm tempo. a rhythm type selection means for selecting a tempo, a tempo setting means for setting a tempo of rhythm performance, a plurality of rhythm patterns corresponding to various rhythm types selectable by the rhythm type selection means, and a plurality of rhythm patterns corresponding to various rhythm types selectable by the rhythm type selection means; Rhythm pattern generating means for sequentially generating rhythm patterns corresponding to the selected rhythm type according to the tempo set by the tempo setting means, and storing rhythm instrument sound waveforms respectively corresponding to various rhythm instrument sounds; , a waveform memory storing a plurality of rhythm instrument sound waveforms having at least one of pitch and timbre different from each other in correspondence with different rhythm tempos for at least one rhythm instrument sound, and a rhythm generated by the rhythm pattern generating means; rhythm sound source means for generating each rhythm instrument sound by reading a rhythm instrument sound waveform corresponding to each rhythm instrument sound from the waveform memory according to a pattern; and a plurality of rhythm instrument sound waveforms for the at least one rhythm instrument sound. Rhythm sound control means for selecting and specifying a rhythm instrument sound waveform to be generated from the rhythm sound source means according to a tempo set by the tempo setting means, the rhythm instrument being generated from the rhythm sound source means. Automatic rhythm performance is performed according to the sound.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an automatic rhythm performance apparatus according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a schematic configuration of this embodiment. In this figure, rhythm pattern memory 1
is a read-only memory (ROM) in which instrument-specific drive data for each rhythm instrument (for example, cymbal, bass drum, conga, bongo, etc.) in each selectable rhythm (for example, waltz, swing, rumba, jazz rock, etc.) is stored. . That is, in this rhythm pattern memory 1, each bit corresponds to each rhythm instrument on a one-to-one basis, and instrument-specific driving data in which one word has the same number of bits as the type of rhythm instrument is stored in correspondence to each rhythm. It is memorized in the order in which the rhythm progresses. Next, a rhythm selection switch 2 is a switch for selecting a rhythm desired by the performer from the above-mentioned rhythms, and is provided on the operation panel of this electronic musical instrument. The rhythm selection switch 2 outputs a signal RS (code signal) indicating the selected rhythm. Reference numeral 3 denotes a slide-type operator for rhythm tempo adjustment provided on the operation panel section, and a tempo control data generator 4 generates data based on the resistance value of a variable resistor (not shown) that is linked to this operator 3. Accordingly, rhythm control data TMP indicating the rhythm tempo corresponding to the slide position of the operator 3 is output. The rhythm pattern reading circuit 5 supplies the address signal A1 generated based on the signal RS and the data TMP to the address input terminal AD of the rhythm pattern memory 1, and outputs the address signal A1 from the memory 1 selected by the rhythm selection switch 2. The rhythm pattern of the rhythm, that is, the driving data for each musical instrument of the same rhythm is sequentially read out. That is, the rhythm pattern readout circuit 5 sets the address signal A1 based on the signal RS to designate the area in the rhythm pattern memory 1 in which the group of instrument-specific drive data of the selected rhythm is stored;
The address signal A1 is sequentially changed at the rhythm tempo indicated by the data TMP, and thereby the drive data for each instrument in the area is sequentially and repeatedly read out at the rhythm tempo corresponding to the slide position of the operator 3. The instrument-specific drive data RD read from the rhythm pattern memory 1 is supplied to the rhythm sound source circuit 6. The rhythm sound source circuit 6 is provided with instrument sound signal generation means for rhythm instruments of different types, which correspond one-to-one to each bit of the instrument-specific drive data RD.
is supplied, each musical instrument sound signal generating means corresponding to the "1" bit in the musical instrument drive data RD is driven. In this case, the rhythm sound source circuit 6 changes the musical instrument sound signals generated by each musical instrument sound signal generating means in accordance with the data TMP supplied from the tempo control data generator 4. The musical instrument sound signals generated by each musical instrument sound signal generating means of the rhythm sound source circuit 6 are synthesized and then supplied to the amplifier 7.
Here, the sound is amplified and supplied to the speaker 8, where it is produced as a rhythm sound.

Next, the detailed structure of the rhythm tone generator circuit 6 in FIG. 1 will be explained with reference to the block diagram in FIG. 2.

First, to give an overview of the rhythm sound source circuit 6 shown in FIG. 2, this rhythm sound source circuit 6 uses a so-called continuous wave memory method, and can receive the musical instrument sound signals of 16 types of rhythm instruments. The musical instrument sound signal is configured to be generated in a time-division manner, and the generated musical instrument sound signal can be changed in four stages according to the rhythm tempo. That is, the second
As shown in FIG. 3, the waveform memory 10 in the figure has 16
The sounds of various rhythm instruments (cymbals, bass drum, high conga, ... maracas) are stored using four types of PCM codes according to the rhythm tempo of each instrument. In this case, taking the cymbal instrument sound as an example, cymbal #1 is the cymbal instrument sound when the rhythm tempo is the slowest, and cymbal #2 is the cymbal sound when the rhythm tempo is one step faster. Instrument sounds, below:
The areas in which the instrumental sounds of cymbals with fast rhythm tempos are stored are shown in the order of cymbals #3 and #4. The same applies to the sounds of the bass drum, high conga, maracas, and other instruments. Then, the instrument-specific drive data RD is supplied, and the same data
When reading the musical instrument sound of a rhythm instrument corresponding to the "1" bit in RD from this waveform memory 10, the musical instrument sound according to the data TMP is read out from the four types of rhythm instruments or the musical instrument sounds.

The rhythm sound source circuit 6 will be described in detail below.The tempo discrimination circuit 11 divides the rhythm tempo indicated by the data TMP into four stages, and outputs each of these stages as a 2-bit signal. That is, this tempo discrimination circuit 11 outputs a signal of "00" if the rhythm tempo belongs to the slowest stage, outputs a signal of "11" if it belongs to the fastest stage, and outputs a signal of "11" if the rhythm tempo belongs to the fastest stage. In the two stages, a signal of "01" is output if it belongs to the slower one, and a signal of "10" is output if it belongs to the faster one. This 2-bit signal is supplied as a lower bit side address signal to an address input terminal AD of an address memory 13, which will be described later. The channel counter 12 is a 4-bit binary counter that determines the reading order and timing when reading out the 16 types of rhythm instrument sounds (ie, information for 16 channels) in the waveform memory 10 in a time-division manner. This channel counter 12 constantly counts the clock φ and outputs the counted value as a 4-bit signal. Note that the period of the clock φ is sufficiently shorter than the minimum rhythm unit time in this electronic musical instrument. The 4-bit signal output from the channel counter 12 is supplied to the address input terminal AD of the address memory 13 as an address signal on the upper bit side. The address memory 13 is a read-on memory (ROM) in which a read start address (start address) and the number of read words (range) for reading musical instrument sounds from the waveform memory 10 are stored. In this case, the start address memory 13a of the address memory 13 has storage areas for each musical instrument sound (cymbal #1, cymbal #2, cymbal #2,
... each starting address of maracas #4) is L ₁ , L ₂ , L ₃ ,
..., L ₆₄ , and in the range memory 13b of this address memory 13, the number of words in the storage area for each musical instrument sound is stored in the order N1, N2, N3, ..., N64. . When an address signal is supplied from the tempo discrimination circuit 11 and channel counter 12, this address memory 13 operates as a start address memory 13.
Data is read out from range memory 3a and range memory 13b in parallel. That is, for example, when a signal "0000" is supplied from the channel counter 12 and a signal "00" is supplied from the tempo determination circuit 11, data "L1" is read from the start address memory 13a, and data "L1" is read from the range memory 13a. When the data "N1" is read out from the start address memory 13b, and for example, when the channel counter 12 supplies the signal "0001" and the tempo determination circuit 11 supplies the signal "11", the data "N1" is read from the start address memory 13a. Data "L8" is read out, and data "N8" is read out from the range memory 13b. The data SA read from the start address memory 13a is supplied to one input terminal A of the adder circuit 14, and the data RG read from the range memory 13b is supplied to one input terminal A of the comparator 15. Ru.

On the other hand, the instrument-specific drive data RD (in this case, 16
bit data) is parallel to serial converter circuit (hereinafter referred to as
(abbreviated as P/S conversion circuit) 16.
When the P/S conversion circuit 16 takes in the data RD in parallel, it sequentially outputs the same data RD bit by bit in series according to the clock φ. This P/S
The serial data outputted from the conversion circuit 16 is supplied to a 1-bit 16-stage shift register 18 via an OR gate 17, and taken into the shift register 18 by the clock φ. The serial output of this shift register 18 is transmitted to the waveform memory 10.
When the output signal of the inverter 19 is a "1" signal, it is supplied to the input terminal I of the shift register 18 via the AND gate 20 and the OR gate 17 in sequence. It's summery. Therefore, if the output signal of the inverter 19 is a "1" signal at that point, the "1" bit output from the shift register 18 is taken into the shift register 18 again by the next clock φ. It will never be lost.
The signal obtained at the output terminal O of this shift register 18 is also supplied to the enable terminal EN of the gate 21.

Next, a portion consisting of a gate 21, a shift register 22, and an adder circuit 23 is for time-divisionally advancing the data read address of the storage area of each musical instrument sound when reading each musical instrument sound from the waveform memory 10. . In this part, the shift register 22
is a 16-stage shift register in which each stage has enough bits to count the maximum number of words of the number of words N1 to N64, and shifting is performed in accordance with the clock φ. The output data D1 of the shift register 22 is supplied to the other input terminal B of the adder circuit 14 and also to one input terminal A of the adder circuit 23.
The other input terminal B of this adder circuit 23 has an LSB
The output data of this adder circuit 23 is
D2 is a value obtained by adding the value "1" to the data D1. This data D2 is supplied to the other input terminal B of the comparator 15 and also to the gate 21. This gate 21 is its enable terminal
When a "1" signal is supplied to EN, it becomes open and supplies the data D2 to the input terminal I of the shift register 22. Therefore, in the portion consisting of this gate 21, shift register 22, and adder circuit 23, the enable terminal EN of the gate 21 is
The data D1 outputted from the shift register 22 when the "1" signal is supplied to the gate 21 is added with the value "1" (that is, incremented) and taken into the shift register 22 again, while the enable terminal of the gate 21 The data D1 output from the shift register 22 when the "0" signal is supplied to EN is lost and becomes the value "0".

Next, the overall operation of the rhythm tone generator circuit shown in FIG. 2 will be explained below.

First, assume that the performer has set the rhythm tempo to the fastest state. In this case, the tempo determination circuit 11 outputs a signal "11". Assume now that instrument-specific drive data RD for generating the sounds of each instrument, cymbal and bass drum, ie, 16-bit data of "110...0" is read out from the rhythm pattern memory 1 of FIG.

In this case, the data RD is the P/S conversion circuit 1
6, one bit at a time is taken into the shift register 18, and in this shift register 18, when all the bits (16 bits) are taken in, "1" is sent from the output terminal O side to the input terminal I side. ”, “1”, “0”, . . . , “0” are arranged in this order. At this point, the count output signal of the channel counter 12 becomes "0000" (synchronization is achieved in this way). As a result, the value "L4" is read out from the start address memory 13a as data SA, and the range memory 1
The value "N4" is read out from 3b as data RG. Also, at this point, the previous instrument-specific drive data RD (the data immediately before the current data RD)
RD) has been completed, all the data in each stage of the shift register 22 is "0", and the data D1 is "0". Therefore, at this point, the output data of the adder circuit 14
D3 becomes the value "L4", and this data D3 is used as an address signal at the address input terminal of the waveform memory 10.
Supplied to AD. Also at this time, the waveform memory 10
Since the read command terminal RC of is supplied with the "1" signal from the output terminal O of the shift register 18,
The data at address L4 of the memory 10, that is, the PCM data of the first word of cymbal #4 is read out.
This PCM data is supplied to the accumulator 24. Also, at this point, the output data D2 of the adder circuit 23 is "1", so the comparator 1
5 outputs a "0" signal, which is the comparison result between the value "N4" and the value "1", from the output terminal EQ and supplies it to the inverter 19. Therefore, the output signal of this inverter 19 is a "1" signal. At this point, the "1" signal output from the shift register 18 is supplied to the input terminal of the shift register 18 via the AND gate 20 and the OR gate 17 in sequence. Also shift register 1
Since the "1" signal outputted by 8 has the gate 21 open, the data D2, that is, the value "1"
is supplied to the input terminal I of the shift register 22.

Now, assume that the next clock φ has occurred. In this case, the output signal of the channel counter 12 becomes "0001", so the value "L8" is read out as data SA from the start address memory 13a, and the value "N8" is read out as data RG from the range memory 13b. In this case, the shift registers 18 and 22 are each shifted by one stage, so the contents of the shift register 18 are "1", "0", "0", etc. from the output terminal O side to the input terminal I side.
..., "0", "1", and the contents of the shift register 22 become "0", ..., "0", "1" from the output terminal O side toward the input terminal I side. In other words, in this case, the data D1 is "0", the data D3 is the value "L8", the data D2 is "1", and the output terminal of the comparator 15
The EQ signal is a "0" signal, the output signal of the shift register 18 is a "1" signal, and the input data of the shift register 22 is a value "1". Therefore, in this case, the data at address L8 of the waveform memory 10, that is, the PCM data of the first word of bass drum #4, is read out, and the PCM data is read out from the accumulator 24.
supplied to

Suppose then that the next clock φ occurs. In this case, the output signal of the channel counter 12 is "0010", so the start address memory 1
The value "L12" is read as data SA from range memory 13a, while the value "N12" is read as data RG from range memory 13b. Also in this case,
Since the shift registers 18 and 22 are each shifted by one stage, the contents of the shift register 18 are "0", . . . from the output terminal O side to the input terminal I side.
..., "0", "1", "1", and the contents of the shift register 22 are "0", ..., "0", "1", " 1”. That is, in this case, data D1 is "0", data D3 is "L12", data D2 is "1", and comparator 15
The signal at the output terminal EQ of the shift register 18 is a "0" signal, the output signal of the shift register 18 is a "0" signal, and the input data of the shift register 22 is a "0" signal. Therefore, in this case, the address input terminal of the waveform memory 10
Although the value "L12" is supplied to AD, since the "0" signal is supplied to the read command terminal RC, data in the same waveform memory 10 is not read out.

Hereinafter, when the clocks φ are sequentially generated, the operation is performed based on the principle described above, but until the count output signal of the channel counter 12 reaches "1111", the output signal of the shift register 18 Since this is also "0", the PCM data in the waveform memory 10 is not read out.

The above is the current instrument-specific drive data RD mentioned above.
1 in the time-division readout process of musical instrument sounds for
This is a scanning action. In this first scan, the PCM data digitally synthesized by the accumulator 24 is supplied to the D/A converter 25, where it is converted into an analog signal and supplied to the amplifier 7 shown in FIG. Ru.

Next, assume that the next clock φ occurs following this point. In this case, channel counter 1
Since the output signal of 2 becomes "0000" again, data "L4" is read out as data SA from the start address memory 13a, and the output signal of range memory 1
Data "N4" is read out from 3b as data RG. In this case, the contents of the shift register 18 become "1", "1", "0", ..., "0" again from the output terminal O side toward the input terminal I side, and the contents of the shift register 22 become "1", "1", "0", ..., "0" again. "1", "1", "0", etc. from the output terminal O side to the input terminal I side
It becomes "0". That is, in this case, data D1 is "1", data D3 is "L4+1", data D2 is "2", and the signal at the output terminal EQ of the comparator 15 is "0".
The output signal of the shift register 18 is a "1" signal, and the input data of the shift register 22 is a "2" signal. Therefore, in this case, the data at address (L4+1) of the waveform memory 10, that is, cymbal #4
The PCM data of the second word of is read out.

Then, when the next clock φ occurs, (L8+1) of the waveform memory 10 is stored in the same manner as described above.
The data at the address, that is, the second word PCM data of bass drum #4, is read out, and the clock φ is sequentially generated, and while the count output signal of the channel counter 12 changes from "0010" to "1111", Data reading from waveform memory 10 is not performed.

The above is the second scan operation in the time-division reading process of musical instrument sounds for the data RD.

Similarly, every time the data other than "0" in each stage of the shift register 22 is shifted by 16 stages (every scan), it is incremented, thereby increasing the The PCM data after the word is read out sequentially.

Then, it is assumed that the N4th scan operation is started (assuming that N4<N8). In this case, if the channel counter 12 outputs "0000",
The value "L4" is read out as data SA from the start address memory 13a, and the value is read out from the range memory 13.
The value "N4" is read from b as data RG. In this case, the contents of the shift register 18 are "1" from the output terminal O side to the input terminal I side.
"1", "0", ..., "0", and the contents of the shift register 22 are changed from the output terminal O side to the input terminal I side.
Facing the side, "N4-1", "N4-1", "0", ...
It is "0". Therefore, in this case, data D1 is "N4-1", data D2 is "N4", and the signal at the output terminal EQ of comparator 15 is data RG and data
Since both D2 have the value "N4", the output signal of the shift register 18 is a "1" signal, the input signal of the shift register 18 is a "0" signal because the AND gate 20 is closed, and the shift register 22 output signal is a "1" signal. The input data will be the value "N4". Therefore, in this case, the data at address (L4+N4-1) of the waveform memory 10, that is, the PCM data (final data) of the N4th word of cymbal #4 is read out.

Next, when the next clock φ occurs, the contents of the shift register 18 become "1", "0", ... "0" from the output terminal O side to the input terminal I side, and so on.
The "1" bit corresponding to the cymbal changes to "0" and thereafter the PCM data of cymbal #4 is no longer read.

Furthermore, when the N8th scan operation is performed, the "1" bit corresponding to the bass drum in the shift register 18 changes to "0" in the same way as the N4th scan operation described above, and from then on, the bit "1" corresponding to the bass drum is changed to "0". Reading of PCM data for drum #4 is no longer performed.

In the manner described above, the time-division readout of musical instrument sounds for the current instrument-specific drive data RD described above is performed. Note that the read operation described above will be completed before the next instrument-specific drive data RD is supplied. Further, when the above-mentioned instrument-specific drive data RD is supplied, and the rhythm tempo is set to the slowest state, for example, each PCM data of cymbal #1 and bass drum #1 will be read out.

However, according to this embodiment, the pitch, timbre, envelope, etc. of the rhythm tones to be produced can be changed in four stages according to the rhythm tempo, thereby making it possible to achieve a performance effect close to that of an actual rhythm performance. can. In this embodiment, the timbre of the rhythm sound, etc. is changed in four stages, but it would be more effective if it were changed in more stages. Furthermore, in this embodiment, the rhythm sound source circuit is of a continuous wave memory type, but it is constructed of a conventional rhythm sound source circuit using a resonant circuit, a noise generator, a filter circuit, an opening/closing circuit, etc. Good too. Further, a rhythm selection signal RS is supplied to the tempo discrimination circuit 11 in this embodiment as shown by the dashed arrow in FIG.
The musical instrument sounds constituting the rhythm sound may change depending on the type of rhythm.

As is clear from the above description, according to the automatic rhythm performance device according to the present invention, when the rhythm sound source circuit is driven by the rhythm pattern read from the rhythm pattern memory to generate the instrument sound signal of each rhythm instrument, Since the rhythm sound control means changes at least one of the pitch and timbre of this instrument sound signal in accordance with the rhythm tempo, automatic rhythm performance is performed using an instrument sound that is extremely close to the actual rhythm performance. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an automatic rhythm playing device according to the present invention, FIG. 2 is a block diagram showing the detailed configuration of the rhythm sound source circuit 6 in the same embodiment, and FIG. 3 is a block diagram showing the detailed structure of the rhythm sound source circuit 6 in the same embodiment. FIG. 3 is a diagram showing the storage contents of the waveform memory 10 in FIG. 1... Rhythm pattern memory, 2... Rhythm selection switch, 4... Tempo control circuit (tempo control data generator), 6... Rhythm sound source circuit, 10...
...Waveform memory, 11...Tempo discrimination circuit, 13...
...address memory.

Claims (1)

[Claims] 1. Rhythm type selection means for selecting a rhythm type, tempo setting means for setting a tempo of rhythm performance, and a plurality of rhythm patterns corresponding to various rhythm types selectable by the rhythm type selection means. rhythm pattern generating means for storing rhythm patterns corresponding to the rhythm type selected by the rhythm type selection means and sequentially generating them in accordance with the tempo set by the tempo setting means; It has a waveform memory that stores a plurality of rhythm instrument sound waveforms that are different in at least one of pitch and timbre corresponding to a plurality of different rhythm tempos for at least one rhythm instrument sound. , rhythm sound source means for generating each rhythm instrument sound by reading a rhythm instrument sound waveform corresponding to each rhythm instrument sound from the waveform memory according to a rhythm pattern generated by the rhythm pattern generation means; Rhythm sound control means for selectively specifying a rhythm instrument sound waveform to be generated from the rhythm sound source means from among a plurality of rhythm instrument sound waveforms for rhythm instrument sounds according to a tempo set by the tempo setting means; An automatic rhythm performance device characterized in that it performs automatic rhythm performance according to rhythm instrument sounds generated from the rhythm sound source means.