JPH01287483A - Testing device for analog-digital hybrid ic - Google Patents

Abstract

PURPOSE:To accurately test the IC by employing constitution wherein the timing signal of a digital testing circuit synchronizes with the timing signal of an analog testing circuit. CONSTITUTION:A synchronizing circuit 15 receives the timing signal outputted by the timing signal generator 8 of the analog testing circuit 3 and synchronizes it with the operation timing of the timing generator 4 of the digital testing circuit 2. A voltage-controlled crystal oscillator 15A supplies a master clock to the programmable frequency divider 13A of the timing generator 4. The timing generator 4 extract a signal of a point where pulse intervals are adjusted by a delay element 13c with resolution of 1ns and supplies this signal to a phase comparator 15B. The phase comparator 15B compares the phases of the signal extracted from the timing generator 4 and the timing signal supplied from the timing generator 8 of the analog testing circuit 3 with each other to control the oscillation phase of the voltage-controlled crystal oscillator 15A according to the comparison output, thereby accurately testing the IC where the timing signals are synchronized at all times.

Description

Detailed Description of the Invention "Industrial Application Field" This invention is an analog-digital hybrid IC used to test ICs in which analog and digital circuits coexist, such as digital audio ICs or modems. related to test equipment.

"Prior Art" FIG. 3 shows a schematic configuration of a conventional analog-digital hybrid IC test device.

In the figure, 1 is the IC under test, 2 is the digital test circuit that tests the digital circuit of this ICI under test, and 3 is the I under test.
An analog test circuit for testing CI analog circuits is shown.

The digital test circuit 2 includes a timing generator 4, a pattern generator 5 that outputs a pattern signal in synchronization with the timing signal output from the timing generator 4, and a pattern signal output from the pattern generator 5 that converts the pattern signal into an actual waveform. The actual waveform generator 6 converts the digital response output from the ICI under test to the digital circuit of the ICI under test, and compares the digital response output from the ICI under test with the expected value data given from the pattern generator 5. The logic comparator 7 determines whether or not the digital system is operating normally.

The analog test circuit 3 includes a timing generator 8 for analog circuits, and performs DA conversion using the timing signal output from the timing generator 8, and provides an analog signal with an arbitrary waveform to the analog circuit of the ICI under test. an AD converter 11 that AD converts an analog signal output from an analog circuit of the ICI under test in synchronization with a timing signal given from a timing generator 8; A determination device 12 determines whether the signal matches an expected value and determines whether the analog circuit of the ICI under test is operating normally.

In this way, conventionally, the digital test circuit 2 and the analog test circuit 3 are operated by timing signals output from separate timing generators 4 and 8.

The reason why the digital test circuit 2 and analog test circuit 3 have separate timing generators 4 and 8 is as follows.

In digital systems, there is a test in which the period of a signal is changed with good resolution and the IC is operated while changing the phase of the timing to check whether it operates normally. For this purpose, the timing generator 4 used in the digital test circuit 2 is provided with a delay generator group 14 on the output side of the period generator 13, as shown in FIG.

In other words, the period generator 13 includes a programmable frequency divider 13A, an AND gate group 13B, a delay element group 13c, and an arithmetic circuit 13D that controls the AND gate group 13B.

In order to generate a period of 25 nanoseconds in the circuit of FIG. 4, the outputs of the programmable frequency divider 13A are 24NS, 24NS, 24NS as shown in FIG. 5A.

28NS, 24NS, 24NS, 28NS, etc., the first pulse is ONS, the second pulse is INS route, the third pulse is 2NS route, 4
If the gate group 13B is controlled so that the first pulse passes through a path of 3'NS, a pulse with a constant period of 25NS can be obtained as shown in FIG. 5B.

By using this period generator 13 in this way, I
The clock period can be changed with a resolution of NS.

The clock pulse output from the period generator 13 is given to a delay generator group 14, and by selectively extracting the pulses output from the delay generators 14A to 14N in the delay generator group 14, the clock pulse is It is possible to generate clocks with a plurality of different phases, or to generate a clock whose generation cycle changes every cycle.

Although this timing generation circuit 4 has the feature of being able to change the cycle of the timing signal with high resolution, it also switches and uses the delay elements of the delay element group 13C for each cycle of each timing signal, so the delay time of each delay element There is a drawback that jitter is imparted to the timing signal due to variations in the timing signal.

On the other hand, since analog circuits have a circuit structure that transmits changes in voltage or current in real time, for example, if jitter is applied to the clock pulse applied to the DA converter 9 or AD converter 11, the effect of the jitter is It has a drawback that it appears in analog signals and distorts the waveform of the analog signal.

For this reason, conventionally, the timing generator 8 used in the analog test circuit 3 is a timing signal generation circuit having a circuit structure that generates a timing signal with little jitter.

For this reason, conventionally, the digital test circuit 2 and the analog test circuit 3 are provided with separate timing generators 4 and 8. It's working.

"Problem to be Solved by the Invention" Synchronizing the operations of the digital test circuit 2 and analog test circuit 3 due to the structure in which the digital test circuit 2 and analog test circuit 3 are operated by timing generators 4 and 8 provided respectively. The frequency that can be achieved is limited to a limited number of frequencies.

In other words, even if the digital test circuit 2 and analog test circuit 3 are synchronized at a certain frequency, if the timing generation period of the digital test circuit 2 is shifted slightly,
The timing generator 8 of the analog test circuit 3 will go out of synchronization.

For this reason, it is conceivable to use the timing signal output from the timing generator 4 of the digital test circuit 2 in the analog test circuit 3, but the timing generator 4 provided in the digital test circuit 2 can be used as shown in FIG. Since the delay generators 14A to 14N are used as means for changing the period of the timing signal little by little, the delay generator 1
There is a drawback that jitter is imparted to the timing signal due to variations in the amount of delay from 4A to 14N.

This jitter is a shift amount 1 that can be tolerated by the analog test circuit 3.
The time is about 100 picoseconds, which is greater than 0 picoseconds, and cannot be used as a timing signal for analog test circuits.

"Means for Solving the Problem" In the present invention, a synchronization circuit is provided in the timing generator of the digital test circuit, and a timing signal is supplied from the timing generator of the analog test circuit to this synchronization circuit, thereby generating the timing of the digital test circuit. The device is configured to be synchronized with the timing signal of the analog test circuit.

According to the configuration of the present invention, the timing signal of the digital test circuit operates in synchronization with the timing signal of the analog test circuit, so that the analog test circuit and the digital test circuit always operate in synchronization, and normal test conditions can be maintained over a wide frequency range. can be maintained over a range.

Embodiment FIG. 1 shows an embodiment of the present invention. In FIG. 1, the portion designated by reference numeral 2 is a digital test circuit, and 3 is an analog test circuit.

The analog test circuit 3 has exactly the same structure as the conventional one.

The feature of this invention is that the timing generator 4 of the digital test circuit 3 is provided with a synchronization circuit 15.

This synchronization circuit 15 receives the timing signal output from the timing signal generator 8 of the analog test circuit 3, and
It is synchronized with the operation timing of the timing generator of the digital test circuit 2.

The configuration of the synchronization circuit is shown in FIG. 2, in which 15A is a voltage controlled crystal oscillator, 15B is a phase comparator, and 15C is a digital adder.

Voltage controlled crystal oscillator 15A provides a master clock to programmable frequency divider 13A of timing generator 4.

The timing generator 4 extracts the signal at the point where the pulse interval is adjusted with the resolution of INS by the delay element group 13C, and supplies this signal to the phase comparator 15B.

The phase comparator 15B compares the phases of the signal taken out from the timing generator 4 and the timing signal given from the timing generator 8 of the analog test circuit 3, and gives the phase comparison output to the voltage controlled crystal oscillator 15A, which performs voltage control. The oscillation phase of the type crystal oscillator 15A is controlled. At the same time, a phase comparison output is given to the digital adder 15C to correct the period setting value.

"Effects of the Invention" According to the present invention, the phase of the timing signal output from the timing generator 4 provided in the digital test circuit 2 is compared with the timing signal output from the timing generator 8 provided in the analog test circuit 3, The phase comparison output controls the oscillation phase of the voltage-controlled crystal oscillator 15A that generates a master clock, and the phase comparison output is sent to the adder 15C.
Since the structure is such that the cycle setting value is corrected based on , the timing signals of the analog test circuit 3 and the digital test circuit 2 can always be synchronized.

As a result, the digital test circuit 2 and the analog test circuit 3 can be operated in synchronization over a wide frequency range, so it is possible to operate the digital test circuit 2 and the analog test circuit 3 in synchronization.
The advantage is that C can be tested accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a block diagram for explaining the invention in detail, and FIG. 3 is a block diagram for explaining a conventional technique.
FIG. 4 is a block diagram for explaining the drawbacks of the conventional technique, and FIG. 5 is a timing chart for explaining a method for changing the pulse interval with good resolution. l...Test under test tC22...Digital test circuit, 3
...Analog test circuit, 4゜8...Timing generator, 5...Pattern generator, 6...Actual waveform generator,
7...Logical comparator, 9...DA converter, 11...
AD converter, 12... Judgment circuit, 15... Synchronization circuit, 15A... Voltage controlled crystal oscillator, 15B...
Phase comparator, 15C...digital adder. Utility model registration applicant Atopan Test Co., Ltd.
Professor Takusai Kusano 1
Figure O Figure 3

Claims (1)

[Claims] (1) A. A timing generator, a pattern generator that outputs a test pattern signal in synchronization with the timing signal output from this timing generator, and a pattern signal output from this pattern generator that converts it into an actual waveform signal. B. A digital test circuit equipped with an actual waveform generator that converts the signal and provides it to the IC under test; B. A DA converter that provides an analog signal with an arbitrary waveform to the analog circuit of the IC under test; and an analog system of the IC under test. An analog circuit equipped with an AD converter that converts an analog signal output from a circuit into a digital signal, and a judgment circuit that compares the digital signal output from this AD converter with an expected value and determines whether the IC under test is good or bad. C. A synchronization circuit that is provided in the timing generator of the digital test circuit and synchronizes the digital test timing signal with the timing signal provided from the timing generator provided in the analog test circuit. Test equipment for analog-digital hybrid ICs.