JP3147129B2 - Timing generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator for an LSI tester, and more particularly, to an edge signal having a period setting resolution higher than the period of a basic clock and having a high edge timing setting resolution. The present invention relates to a timing generator capable of performing the following.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional timing generator. In the figure, reference numeral 10 denotes a period generator which distributes and outputs a rate signal S _1d and an edge counting clock CLK _1d to a plurality of edge generators 20. In this embodiment, one edge generator 20 will be described as a representative.

[0003] In cycle generator 10, 11 an oscillator for supplying a basic clock CLK _0, 12 denotes a memory, data and delayed data rate signal S ₁ is stored.
A counter 13 counts down a value set from the memory 12 based on the basic clock CLK ₀ , and outputs a pulse to the coincidence detection circuit 14 when the count value of the count becomes “0”.

The coincidence detecting circuit 14 outputs a rate signal S ₁ to a delay circuit 15 based on a pulse inputted from the counter 13.
At the same time, and outputs a trigger for execution of the operation to the operation circuit 16. The counter 13 sets the next data from the memory 12 by the trigger of the coincidence detection circuit 14 and starts counting again. The arithmetic circuit 16 sets the delay time of the rate signal S _{1 in} the delay circuit 15 based on the next cycle data from the memory 12 and the delay data of the current cycle. Further, the arithmetic circuit 16 sets delay data for synchronizing the delayed rate signal S _1d with the basic clock CLK ₀ in the delay circuit 17.

The delay circuit 15 delays the rate signal S ₁ with a resolution of one cycle or less of the basic clock CLK ₀ based on the data of the arithmetic circuit 16 and outputs the delayed signal to the edge generator 20. On the other hand, the delay circuit 17 delays the basic clock CLK ₀ based on the delay data from the arithmetic circuit 16 and outputs the same to the edge generator 20 as an edge count clock CLK _1d .

In the edge generator 20, a counter 21 performs a synchronous clear operation. An edge count clock CLK _1d is input to a clock terminal, and a rate signal S _1d is input to a reset terminal. 22 is a match detection circuit, when the set value from the memory 23 matches the count value inputted from the counter 21, and outputs the edge signal S ₂ to the delay circuit 24. The delay circuit 24 is set with delay data for delaying the edge signal S _2d from the memory 23, delays the edge signal S ₂ input from the coincidence detection circuit 22 based on the delay data, and outputs it to a formatter (not shown). I do.

FIGS. 4A and 4B are time charts for explaining the operation of the conventional timing generator. FIG. 4A shows the basic clock CLK ₀ , FIG. 4B shows the rate signal S _1d output to the counter 21, and FIG. Is the edge count clock CLK _1d output to the counter 21; (D) is the count value of the counter 21; and (E) is the edge signal S output from the delay circuit 24.
_2d .

(1) The counter 21 is reset by the rising edge clock CLK _1d when the rate signal S _1d input from the cycle generator 10 is at a high level, and starts counting. (2) The counter 21 outputs the count value to the coincidence detection circuit 22. Coincidence detection circuit 22, when the count value reaches a value loaded from memory 23, and outputs this case the edge signal S ₂ to the delay circuit 24 by four counts. (3) delay circuit 24, an edge signal S ₂ input from the match detection circuit 22 time t _2d delayed specified from the memory 23, and outputs the Fomatta.

(4) When the basic clock CLK ₀ becomes n, the coincidence detection circuit 14 of the cycle generator 10 outputs the rate signal S ₁ to the delay circuit 15. The delay circuit 15 delays the rate signal S ₁ by a time t _{1d and} outputs it to the counter 21. (5) On the other hand, the (n + 1) th edge counting clock CLK _1d delayed by the delay circuit 17 so as to be synchronized with the rate signal S _1d is provided to the clock terminal of the counter 21.
Is entered. The counter 21 is reset based on the rate signal S _1d and the edge count clock CLK _1d, and starts counting again.

As described above, the edge signal S _2d is
The resolution of the period is increased by the delay circuit 17, and the resolution of the output timing is increased by the delay circuit 24.

[0011]

In such a conventional timing generator, the rate signals are delayed according to the delay of the edge count clock to synchronize them with each other, but within one cycle of the basic clock. Therefore, if the signal is distributed to a plurality of edge generators having different transmission distances, synchronization may be lost depending on the edge generator.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an edge count clock obtained by dividing the frequency of a basic clock, and an edge count clock having a frequency not less than the cycle width of the basic clock and not more than the cycle width of the edge count clock. An edge signal is obtained by a rate signal having a pulse width, a margin of synchronization between the rate signal and an edge count clock is increased, and a plurality of edge generators are provided without considering a synchronization shift by distribution. It is an object of the present invention to provide a timing generator capable of stably outputting an edge signal.

[0013]

In order to achieve the above object, the present invention provides a timing generator for outputting a rate signal to a pattern generator and outputting an edge signal to a formatter. A frequency divider that divides the frequency and a rate signal having a pulse width of at least one cycle of the basic clock based on the basic clock, and a cycle width of an edge count clock obtained by dividing the frequency signal by the frequency divider. A rate signal generation circuit obtained below,
The edge count clock is 1 of the basic clock.
A first delay circuit for delaying with a period or less, the Ejjikau
The rate signal is high level.
In the state, the edge delayed by the first delay circuit.
Reset by rising edge of the count clock
And a second delay circuit for delaying an edge signal output when the counter reaches a predetermined count value with a resolution of one cycle or less of the edge count clock, wherein the second delay circuit An edge signal delayed by a circuit is output to the formatter.

[0014]

The components of the present invention operate as follows. The frequency divider divides the frequency of the basic clock and outputs the result to the first delay circuit. A rate signal generating circuit for obtaining, based on the basic clock, a rate signal having a pulse width equal to or greater than the cycle of the basic clock and equal to or less than the cycle width of the edge count clock obtained by dividing the frequency by the frequency dividing circuit; Output to The first delay circuit delays the edge count clock with a resolution of one cycle or less of the basic clock and outputs the delayed clock to the edge generation circuit. The counter performs a counting operation based on an edge counting clock input through the first delay circuit and a rate signal input from the rate signal generating circuit. The second delay circuit has a resolution of one cycle or less of the edge counting clock, delays an edge signal output when the counter reaches a predetermined count value, and outputs the delayed edge signal to the formatter.

[0015]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a timing generator according to an embodiment of the present invention. In the figure, components having the same function as the configuration described in FIG. 3 are denoted by the same reference numerals, and the description will be omitted.

In the period generator 10, 30 is a frequency divider.
The basic clock CLK of the oscillator 11 ₀Obtained by dividing
Edge counting clock CLK_TwoTo the first delay circuit 3
It outputs to the counter 21 via 1. First delay circuit 3
1 is based on the data set by the arithmetic circuit 16
Clock for the edge count of the next synchronous edge signal
CLK_2dIs the basic clock CLK ₀Resolution of one cycle or less
And outputs it to the counter 21.

Reference numeral 32 denotes a rate signal generating circuit,
3, the rate signal S
₃ is output to the counter 21, and a reset signal and a load signal are output to the frequency divider 30 and the counter 13. still,
The rate signal S ₃ is generated by the rate signal generation circuit 32.
Is waveform shaped to divider circuit 30 at a period greater than width of the basic clock CLK ₀ is divided from edge count clock CLK ₂ in period width pulse width less.

In the edge generator 20, reference numeral 33 denotes an arithmetic circuit, which calculates data to be set in the coincidence detecting circuit 22 and the second delay circuit 34 based on the input edge data and cycle data, and writes the calculated data into the memory 23. . The coincidence detection circuit 22 outputs the edge signal S4 to the second delay circuit 34 when the count value is loaded from the memory 23 and when the loaded value matches the count value input from the counter 21.
The second delay circuit 34 can delay and set the edge signal S4 to a range of one cycle of the edge count clock CLK2d.

The second delay circuit 34 includes the coincidence detection circuit 22
The edge signal S4 output by the clock C for edge counting
LK2d can be delayed up to one cycle, and outputs an edge signal S4d delayed based on a value set from memory 23 to the formatter.

FIGS. 2A and 2B are time charts for explaining the operation of the timing generator of the present invention. FIG. 2A shows the basic clock CLK ₀ , and FIG. 2B shows the edge count clock C.
LK ₂ , (C) is the rate signal S ₃ output to the counter 21, and (D) is delayed by the first delay circuit 31, and the edge count clock CL output to the counter 21 is
K _2d , (E) is the count value of the counter 21, and (F) is the edge signal S _4d output from the second delay circuit 34. (1) The frequency divider 30 converts the edge count clock CLK ₂ obtained by dividing the basic clock CLK by 4 into the first delay circuit 3
Output to 1.

(2) The rate signal generation circuit 32 forms a rate signal S based on the pulse input from the counter 13 such that the pulse width is equal to or greater than the cycle width of the basic clock and equal to or less than the cycle width of the edge count clock. ₃ is output to the counter 21. (3) The counter 21 performs counting based on the edge count clock CLK _2d input via the first delay circuit 31, and outputs the count value to the coincidence detection circuit 22. (4) the coincidence detection circuit 22, when the set value from the memory 23 matches the count value, and outputs an edge signal S ₄ to the second delay circuit 34.

[0022] (5) a second delay circuit 34, based on the value set from the memory 23 delays the edge signal S ₄ inputted from the coincidence detection circuit, and outputs the Fomatta. The time chart indicates that “1” is output from the memory 23 to the match detection circuit 22.
Is set in the second delay circuit 34 and the delay time t _4d
Is set.

(6) The counter 21 again outputs the rate signal S ₃
Until the (n + 1) th edge count clock CLK _2d is input and reset, the edge count clock C input from the first delay circuit 31
The counting is continuously performed based on LK _2d . (N +
1) The first edge count clock CLK _2d is the first
_Is delayed by the time t _d by the delay circuit 31 of
Period of the edge signal S ₄ can be set by the following resolution of 1 period t of the basic clock CLK ₀ and (nt + t _d).

[0024]

As described above in detail, the timing generator according to the present invention comprises: an edge count clock obtained by dividing the basic clock; An edge signal is obtained by a rate signal having the following pulse width, and a margin for synchronization between the rate signal and the edge count clock is increased. For this reason, the rate signal and the edge count clock can be stably distributed to the plurality of edge generators without considering synchronization deviation, and a high-resolution edge signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a timing generator according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the timing generator of the present invention.

FIG. 3 is a configuration block diagram of a conventional timing generation device.

FIG. 4 is a time chart for explaining the operation of the conventional timing generator.

[Explanation of symbols]

 30 frequency divider 31 first delay circuit 32 rate signal generation circuit 33 arithmetic circuit 34 second delay circuit

Claims (1)

(57) [Claims] 1. A timing generator for outputting a rate signal to a pattern generator and outputting an edge signal to a formatter, comprising: a frequency divider for dividing the basic clock by n; A rate signal generating circuit that obtains a rate signal having a pulse width of at least one cycle or less by a cycle width of an edge count clock obtained by dividing the frequency by the frequency divider; Of 1
A first delay circuit for delaying the clock signal for a period equal to or less than a cycle , and counting the edge count clock;
Signal in the first delay circuit when the signal is in the high level state.
The rising edge of the edge counting clock
And a second delay circuit for delaying an edge signal output when the counter reaches a predetermined count value with a resolution of one cycle or less of the edge count clock, A timing generator for outputting an edge signal delayed by a second delay circuit to the formatter.