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JPH0122650B2 - - Google Patents

Info

Publication number
JPH0122650B2
JPH0122650B2 JP59094480A JP9448084A JPH0122650B2 JP H0122650 B2 JPH0122650 B2 JP H0122650B2 JP 59094480 A JP59094480 A JP 59094480A JP 9448084 A JP9448084 A JP 9448084A JP H0122650 B2 JPH0122650 B2 JP H0122650B2
Authority
JP
Japan
Prior art keywords
section
power supply
cpu
normal
process output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59094480A
Other languages
Japanese (ja)
Other versions
JPS60238943A (en
Inventor
Tetsuo Ishii
Akihiko Maekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59094480A priority Critical patent/JPS60238943A/en
Publication of JPS60238943A publication Critical patent/JPS60238943A/en
Publication of JPH0122650B2 publication Critical patent/JPH0122650B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はプログラマブルコントローラの故障
検出と故障検出した場合の処置に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to failure detection in a programmable controller and treatment when a failure is detected.

〔従来技術〕[Prior art]

第1図は従来のプログラマブルコントローラの
構成を示したブロツク図であり、図において、1
はプログラマブルコントローラの制御部で、
CPU部11、プロセス入力部(PI)12、プロ
セス出力部(PO)13とで構成されている。2
はプログラマブルコントローラの5Vロジツク電
源で、電源線202を通してプログラマブルコン
トローラ制御部1に電源を供給し、信号線201
にてCPU11に5Vロジツク電源2の正常を伝え
る。3はプロセス出力部用電源で、本装置例は
DC24Vを使用しており、電源線301を通じて
プロセス出力部13に電源を供給している。31
はプロセス出力部用電源3の正常でONする接
点、4はプロセス入力部用電源で、本装置例では
DC48Vを使用しており、電源線401を通じて
プロセス入力部12に電源を供給している。41
はプロセス入力部用電源4の正常でONする接
点、51はプログラマブルコントローラの正常で
ONするリレー、52,53はリレー51の接点
で、その接点53は前記電源線301に設けられ
ている。54はリレー51と並列に接続されたサ
ージキラーである。110はCPU11の正常を
伝える信号線で、前記接点31,41、リレー5
1が順次直列に接続してある。
FIG. 1 is a block diagram showing the configuration of a conventional programmable controller.
is the control part of the programmable controller,
It is composed of a CPU section 11, a process input section (PI) 12, and a process output section (PO) 13. 2
is a 5V logic power supply for the programmable controller, which supplies power to the programmable controller control unit 1 through the power line 202, and the signal line 201.
Informs the CPU 11 that the 5V logic power supply 2 is normal. 3 is the power supply for the process output section, and this device example is
DC24V is used, and power is supplied to the process output section 13 through the power line 301. 31
is the contact that turns ON when the power supply 3 for the process output section is normal, and 4 is the power supply for the process input section, in this device example.
DC48V is used, and power is supplied to the process input section 12 through a power line 401. 41
51 is the contact that turns on when the process input power supply 4 is normal, and 51 is the contact that turns on when the programmable controller is normal.
Relays 52 and 53 that are turned on are contacts of the relay 51, and the contact 53 is provided on the power line 301. 54 is a surge killer connected in parallel with the relay 51. 110 is a signal line that conveys the normality of the CPU 11, and is connected to the contacts 31, 41 and the relay 5.
1 are connected in series.

第2図はプログラマブルコントローラの制御部
1の構成要素であるプロセス出力部13の詳細を
示した回路図である。第2図において、13aは
CPU11とのインターフエース部、13bは出
力信号を保持するメモリ、13cは出力リレー、
13dは出力リレー13cの接点、13eは出力
リレー13cと並列に接続されたサージキラー、
13fは出力リレー13cと直列に接続されたス
イツチングトランジスタである。
FIG. 2 is a circuit diagram showing details of the process output section 13, which is a component of the control section 1 of the programmable controller. In Figure 2, 13a is
An interface section with the CPU 11, 13b is a memory that holds output signals, 13c is an output relay,
13d is a contact of output relay 13c, 13e is a surge killer connected in parallel with output relay 13c,
13f is a switching transistor connected in series with the output relay 13c.

次に動作について説明する。5Vロジツク電源
2の電圧が電源線202を通してプログラマブル
コントローラの制御部1に供給され、信号線20
1を通してCPU11へ5Vロジツク電源2の正常
の信号が印加されると、CPU11は自己チエツ
クを実施し、信号線110を通してCPU11の
正常の信号をプロセス出力部用電源3に送る。こ
の時、プロセス出力部用電源3が正常に動作して
いれば、接点31が“ON”となり、プロセス入
力部用電源4が正常に動作していれば、接点41
が“ON”となる。
Next, the operation will be explained. The voltage of the 5V logic power supply 2 is supplied to the control unit 1 of the programmable controller through the power supply line 202, and the voltage of the 5V logic power supply 2 is supplied to the control unit 1 of the programmable controller through the
When the normal signal of the 5V logic power supply 2 is applied to the CPU 11 through the signal line 110, the CPU 11 performs a self-check and sends the normal signal of the CPU 11 to the process output section power supply 3 through the signal line 110. At this time, if the power supply 3 for the process output section is operating normally, the contact 31 is turned "ON", and if the power supply 4 for the process input section is operating normally, the contact 41 is turned "ON".
becomes “ON”.

そこで、リレー51は上記接点31,41を介
して供給された上記CPU正常の信号により駆動
され、その接点52,53が“ON”となる。次
いで接点53が“ON”となることにより、プロ
セス出力部用電源3が電源線301を通じてプロ
セス出力部13に供給されて該プロセス出力部が
動作可能となる。
Therefore, the relay 51 is driven by the CPU normality signal supplied via the contacts 31 and 41, and the contacts 52 and 53 are turned "ON". Then, when the contact 53 is turned "ON", the power supply 3 for the process output section is supplied to the process output section 13 through the power line 301, and the process output section becomes operable.

すなわち、プロセス出力部13はCPU11の
指令をインタフエース回路13aで判別し、その
判別結果を出力メモリ13bに記憶し、出力駆動
トランジスタ13fにより出力リレー13cを駆
動し、出力接点13dを“ON”“OFF”するが、
前記プロセス出力部用電源3が接点53により
“OFF”になつておれば、外部出力がなされない
こととなる。これにより、電源装置CPUが正常
の場合にプロセス出力部用電源3がプロセス出力
部13に印加され、最終出力リレー13cの駆動
が可能となる。
That is, the process output unit 13 discriminates the command from the CPU 11 by the interface circuit 13a, stores the discrimination result in the output memory 13b, drives the output relay 13c by the output drive transistor 13f, and turns the output contact 13d "ON". OFF”, but
If the power supply 3 for the process output section is turned "OFF" by the contact 53, no external output will be made. Thereby, when the power supply device CPU is normal, the process output unit power supply 3 is applied to the process output unit 13, and the final output relay 13c can be driven.

従来のプログラマブルコントローラは以上のよ
うに構成されているので、プロセス入力部用電
源、プロセス出力部用電源に異常があつても、
CPUはその状態を知ることができず、電源装置
の異常を分離して監視できない欠点があつた。
Conventional programmable controllers are configured as described above, so even if there is an abnormality in the power supply for the process input section or the power supply for the process output section,
The drawback was that the CPU could not know its status, and it was not possible to isolate and monitor abnormalities in the power supply.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除
去するためになされたもので、全ての電源装置が
正常であることを検出し、その信号をCPUへ送
出し、CPUは電源装置が正常であることを確認
した後、CPUの動作、プロセス入力部、プロセ
ス出力部の動作チエツクを実施し、各々が正常で
あつた時に電源をプロセス出力部に印加する構成
としたことにより、CPUは全てを確認してから
実動作を開始することが可能となり、全ての電源
装置の正常を一括して監視することのできるプロ
グラマブルコントローラを提供するものである。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above. It detects that all power supplies are normal, sends the signal to the CPU, and the CPU detects that the power supplies are normal. After confirming that, we checked the operation of the CPU, the process input section, and the process output section, and when each was found to be normal, we applied power to the process output section, so the CPU confirmed everything. The purpose of the present invention is to provide a programmable controller that can start actual operation after the power supply is installed, and can collectively monitor the normality of all power supply devices.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を前記第1図と同一
部分に同一符号を付した第3図について説明す
る。第3図において、5は故障監視回路で、シス
テム正常で“ON”となるリレー51、そのリレ
ー51の接点52,53、リレー51と並列に接
続されたサージキラー54、電源装置2〜4の正
常を検出する為のAND回路55、信号線111
による電源装置正常の信号と信号線110による
システム正常の信号とのANDを取るAND回路5
6、システム正常を表示す表示器57、電源装置
正常を表示する表示器58とで構成されている。
An embodiment of the present invention will be described below with reference to FIG. 3, in which the same parts as in FIG. 1 are designated by the same reference numerals. In Fig. 3, 5 is a failure monitoring circuit, which includes a relay 51 that turns ON when the system is normal, contacts 52 and 53 of the relay 51, a surge suppressor 54 connected in parallel with the relay 51, and a fault monitoring circuit that turns on when the system is normal. AND circuit 55 and signal line 111 for detecting
AND circuit 5 that takes an AND between the signal indicating that the power supply is normal and the signal indicating that the system is normal via the signal line 110.
6. It is composed of a display 57 that indicates whether the system is normal, and a display 58 that indicates that the power supply is normal.

次に動作について説明する。電源ON時、各電
源装置2〜4は立上り、5Vロジツク電源2は電
源線202を通してプログラマブルコントローラ
の制御部1に供給され、プロセス出力部用電源3
は電源線301を通してプロセス出力部13に供
給され、プロセス入力部用電源4は電源線401
を通してプロセス入力部12に供給される。但
し、この時、接点53は開いている為、プロセス
出力部用電源3は断となつている。
Next, the operation will be explained. When the power is turned on, each power supply device 2 to 4 starts up, and the 5V logic power supply 2 is supplied to the control unit 1 of the programmable controller through the power line 202, and the power supply 3 for the process output unit is supplied.
is supplied to the process output part 13 through the power line 301, and the power supply 4 for the process input part is supplied to the power line 401.
The signal is supplied to the process input section 12 through. However, at this time, since the contact 53 is open, the power supply 3 for the process output section is cut off.

一方、故障監視回路5は各電源装置2〜4の正
常の信号を、信号線201,302,402を通
して取込み、AND回路55にて全ての電源装置
2〜4の正常信号を作成し、この電源正常信号を
信号線111を介してCPU11へ送り、表示器
58を点灯する。この間、プログラマブルコント
ローラの制御部1はリセツト状態にあり、上記電
源正常信号がCPU11に到達したことによりプ
ログラマブルコントローラの制御部1はイニシヤ
ル処理を実行する。
On the other hand, the failure monitoring circuit 5 takes in the normal signals of the power supplies 2 to 4 through the signal lines 201, 302, and 402, creates normal signals of all the power supplies 2 to 4 in the AND circuit 55, and A normal signal is sent to the CPU 11 via the signal line 111, and the display 58 is turned on. During this time, the control section 1 of the programmable controller is in a reset state, and when the power supply normal signal reaches the CPU 11, the control section 1 of the programmable controller executes initial processing.

このイニシヤル処理はCPU11の自己チエツ
ク(演算チエツク)を行ない、次に、CPU11
によりプロセス入力部12、プロセス出力部13
をアクセスして正常であることを確認した後、故
障監視回路5に信号線110を介してシステム正
常信号を送り、前記電源装置正常信号とのAND
をAND回路56で取り、リレー51を駆動する
と共にシステム正常表示器57を点灯する。
This initial processing performs a self-check (calculation check) of the CPU 11, and then
Process input section 12, process output section 13
After accessing and confirming that it is normal, a system normal signal is sent to the failure monitoring circuit 5 via the signal line 110, and an AND signal with the power supply normal signal is sent.
is taken by the AND circuit 56 to drive the relay 51 and light up the system normality indicator 57.

そこで、始めてリレー51の接点53がONと
なり、プロセス出力部13にプロセス出力部用電
源3から電源が供給され、プロセス出力が可能と
なる。すなわちプロセス出力部13の最終リレー
13cに電源が供給されて動作可能となる。ここ
まで動作を確認した後、CPU11は通常の動作
状態に入いる。
Then, the contact 53 of the relay 51 is turned on for the first time, and power is supplied to the process output section 13 from the process output section power supply 3, making process output possible. That is, the final relay 13c of the process output section 13 is supplied with power and becomes operational. After confirming the operation up to this point, the CPU 11 enters the normal operating state.

また、プログラムの実行サイクル毎のような定
周期で、CPU11の自己診断及びプロセス入力
部12、プロセス出力部13のチエツクを実施
し、異常を検出したらシステム正常信号110を
落とせば、プロセス出力部13の最終出力は
OFFされ、異常信号は出力されないこととなる。
In addition, the self-diagnosis of the CPU 11 and the checking of the process input section 12 and the process output section 13 are carried out at regular intervals such as every program execution cycle, and if an abnormality is detected, the system normal signal 110 is dropped, and the process output section 13 is checked. The final output of
It will be turned OFF and no abnormal signal will be output.

なお上記実施例ではプロセス入力部用電源4を
DC48V、プロセス出力部用電源3をDC24Vとし
たが、電圧の大きさはどのようなものでもよく、
ACでもよい。又システム正常の最終出力をリレ
ーとしたが、リレーの代りに半導体(例えばフオ
トカプラ)を使用してもよい。さらにプロセス出
力部13の詳細部として、第2図に1回路分を代
表して挙げたが、当然何回路でもよく、そのプロ
セス出力をリレーで構成したが、リレーの代りに
半導体(例えばフオトカプラ)を用いても同様の
構成が可能である。
In the above embodiment, the power supply 4 for the process input section is
We used 48V DC and 24V DC for the process output power supply 3, but the voltage may be of any magnitude.
AC may also be used. Further, although the final output of the system is assumed to be a relay, a semiconductor (for example, a photocoupler) may be used instead of the relay. Furthermore, as a detailed part of the process output section 13, one circuit is shown as a representative in FIG. A similar configuration is also possible using .

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、全ての電源
装置の異常を検出し、CPUが電源装置が正常で
あることを確認した後、CPUの動作、プロセス
入力部、プロセス出力部の動作チエツクを実施
し、各々が正常であつた時にプロセス出力部用電
源をプロセス出力部に印加するように構成したの
で、制御システムを安全に動作させることができ
る。また故障発生個所が明確になるという効果が
得られる。
As described above, according to the present invention, after detecting abnormalities in all power supplies and confirming that the power supplies are normal, the CPU checks the operation of the CPU, the process input section, and the process output section. The control system can be operated safely because the power supply for the process output part is applied to the process output part when each of the parts is normal. Moreover, the effect that the location where the failure occurs becomes clear can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプログラマブルコントローラの
構成を示したブロツク図、第2図はプロセス出力
部の詳細を示した回路図、第3図はこの発明の一
実施例によるプログラマブルコントローラの構成
を示すブロツク図である。 1はプログラマブルコントローラ制御部、2は
5Vロジツク電源、3はプロセス出力部用電源、
4はプロセス入力部用電源、5は故障監視回路、
11はCPU、12はプロセス入力部、13はプ
ロセス出力部。なお、図中、同一符号は同一、又
は相当部分を示す。
FIG. 1 is a block diagram showing the configuration of a conventional programmable controller, FIG. 2 is a circuit diagram showing details of the process output section, and FIG. 3 is a block diagram showing the configuration of a programmable controller according to an embodiment of the present invention. It is. 1 is a programmable controller control section, 2 is a
5V logic power supply, 3 is the power supply for the process output section,
4 is a power supply for the process input section, 5 is a failure monitoring circuit,
11 is a CPU, 12 is a process input section, and 13 is a process output section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1 CPU部とプロセス入力部とプロセス出力部
とを有するプログラマブルコントローラの制御部
と、前記の制御部とプロセス入力部とプロセス出
力部の夫々に対応して設けられた別個独立の複数
の電源装置と、前記各電源装置の正常信号に基づ
いて全ての電源装置の正常信号を前記CPU部に
送り、前記正常信号を受けた前記CPU部が自己
チエツクを行い、次いで前記プロセス入力部とプ
ロセス出力部のチエツクを実行した後、前記
CPU部からのシステム正常信号と前記全ての電
源装置の正常信号とに基づいて、前記プロセス出
力部に対し前記電源装置を接続して外部出力を可
能とする故障監視回路と、を備えたプログラマブ
ルコントローラ。
1. A control section of a programmable controller having a CPU section, a process input section, and a process output section, and a plurality of separate power supply devices provided corresponding to each of the control section, process input section, and process output section. , based on the normal signals of each power supply, the normal signals of all the power supplies are sent to the CPU section, and the CPU section that receives the normal signal performs a self-check, and then the process input section and the process output section are checked. After running the check, the above
A programmable controller comprising: a failure monitoring circuit that connects the power supply to the process output section to enable external output based on the system normal signal from the CPU section and the normal signals of all the power supplies. .
JP59094480A 1984-05-14 1984-05-14 Programmable controller Granted JPS60238943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59094480A JPS60238943A (en) 1984-05-14 1984-05-14 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59094480A JPS60238943A (en) 1984-05-14 1984-05-14 Programmable controller

Publications (2)

Publication Number Publication Date
JPS60238943A JPS60238943A (en) 1985-11-27
JPH0122650B2 true JPH0122650B2 (en) 1989-04-27

Family

ID=14111440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59094480A Granted JPS60238943A (en) 1984-05-14 1984-05-14 Programmable controller

Country Status (1)

Country Link
JP (1) JPS60238943A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092639A (en) * 1973-12-14 1975-07-24
JPS5359330A (en) * 1976-11-09 1978-05-29 Fuji Electric Co Ltd Mis-output preventing system
JPS5676849A (en) * 1979-11-27 1981-06-24 Nec Corp Fault relieving system for unmanned operation electronic computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092639A (en) * 1973-12-14 1975-07-24
JPS5359330A (en) * 1976-11-09 1978-05-29 Fuji Electric Co Ltd Mis-output preventing system
JPS5676849A (en) * 1979-11-27 1981-06-24 Nec Corp Fault relieving system for unmanned operation electronic computer system

Also Published As

Publication number Publication date
JPS60238943A (en) 1985-11-27

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