JPH01226168A - Manufacture of semiconductor device substrate - Google Patents
Manufacture of semiconductor device substrateInfo
- Publication number
- JPH01226168A JPH01226168A JP5299588A JP5299588A JPH01226168A JP H01226168 A JPH01226168 A JP H01226168A JP 5299588 A JP5299588 A JP 5299588A JP 5299588 A JP5299588 A JP 5299588A JP H01226168 A JPH01226168 A JP H01226168A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- layer
- sio2
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- -1 oxygen ions Chemical class 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 5
- 239000010453 quartz Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 13
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 238000003486 chemical etching Methods 0.000 abstract description 3
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 6
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明ＳＯ工（５ｉｌｉｃｏｎ Ｏｎ工ｎ５ｕｌａｔｏ
ｒ ） 基板の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention
r) Regarding a method for manufacturing a substrate.
従来、ＳＯ工基板は、Ｓｉ基板を石英又は他のＳｉ基板
に貼付け、前記Ｓｉ基板の裏面より機械研摩及び機械化
学研摩により研摩し、薄いｓ１１良を残すと云う方法が
用いられるのが通例であった〔発明が解決しようとする
課題〕
しかし、上記従来技術によると、Ｓｉｐの厚さのバラツ
キが例えば１．０μ風±［Ｌ５μｍ％度と１μｍ％度有
り、厚さがα５μｍ以下に出来ない等の問題があった。Conventionally, SO substrates have been produced by attaching a Si substrate to a quartz or other Si substrate, and polishing the back surface of the Si substrate by mechanical polishing or mechanochemical polishing to leave a thin S11 surface. [Problem to be solved by the invention] However, according to the above-mentioned conventional technology, the variation in the thickness of the SIP is, for example, 1.0 μm ± [L5 μm% degree and 1 μm% degree, and the thickness cannot be reduced to α5 μm or less. There were other problems.
本発明は、かかる従来技術の問題点をなくし、５ｔｌｌ
の厚さをｏ、５μｍ以下で且つ、Ｓ１膜の厚さのバラツ
キもα５μ扉±α１μｍと０．２μｍ以下に押えること
ができるＳＯ工基板の製造方法を提供する事を目的とす
る。The present invention eliminates the problems of the prior art and
It is an object of the present invention to provide a method for manufacturing an SO-engineered substrate in which the thickness of the S1 film can be kept to 0.5 μm or less, and the variation in the thickness of the S1 film can be kept to α5μ±α1 μm and 0.2 μm or less.
上記問題点を解決するために、本発明は、半導体装置基
板の製造方法に関し、
（１）３１基板の一主面上から酸素イオンあるいは窒素
イオンあるいは、その双方を打込み、該Ｓｉ基板のイオ
ン打込み面と石英基板あるいは他のＳｉ基板を貼り合わ
せ、前記イオン打込み、Ｓｉ基板の他の主面から機械研
摩と化学エツチング処理を施し、ＳＯ工構造となす手段
奪とる事、及び、
（２） イオン打込みを図形状レジスト・パターン介
して施す手段をとる事、
である。In order to solve the above-mentioned problems, the present invention relates to a method for manufacturing a semiconductor device substrate. (2) bonding the surface to a quartz substrate or another Si substrate, performing the ion implantation, mechanical polishing and chemical etching from the other main surface of the Si substrate to obtain a SO structure; and (2) ion implantation. The method is to perform implantation through a graphic resist pattern.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例をＳＯ工基板製造工程である
。すなわち、（α）Ｓｉ基板１の鏡面表面には５１０８
膜２が形成され、（ｂ）該Ｓｉ基板１０表面から酸素イ
オン打込みを行ない、酸素イオン打込み層３を形成し、
＜ｃ＞ｍ素、イオン打込み層を活性化する目的で９００
℃、３０分程度の窒素アニール処理を施して、Ｓｉｎ、
又はＳｉＯから成るＳ１０！層４を形成すると共に該３
１０２層４の上にＳｉ膜５が形成されることとなる。（
ｄ）次で、他のＳｉ基板６を前記イオン打込みしたＳｉ
基板１上のＳｉｎ、１％とをシラノール反応により貼付
け、（−）前記Ｓｉ基板１の裏面から、まず機械研摩を
施し、次で化学研摩を施すことにより裏面Ｓｉ層を除去
する。この場合、化学研摩時には５１０１層４はエツチ
ング・ストッパーとしての作用があり、機械研摩時のＳ
ｉ基板１のＳ１膜厚のバラツキを無くする作用があり、
該５１０２層４はそのまま残存させても良いが、本例で
は、該５１０１層４は除去したものとして示しである。FIG. 1 shows an SO engineered substrate manufacturing process according to an embodiment of the present invention. That is, on the mirror surface of the (α)Si substrate 1, there are 5108
A film 2 is formed, (b) oxygen ions are implanted from the surface of the Si substrate 10 to form an oxygen ion implanted layer 3;
<c>m element, 900 for the purpose of activating the ion implantation layer
After nitrogen annealing at ℃ for about 30 minutes,
Or S10 made of SiO! Forming layer 4 and forming layer 3
A Si film 5 is formed on the 102 layer 4. (
d) Next, another Si substrate 6 is made of the ion-implanted Si.
1% Si on the substrate 1 is attached by silanol reaction, and the back side Si layer is removed by first performing mechanical polishing and then chemical polishing from the back side of the (-) Si substrate 1. In this case, the 5101 layer 4 acts as an etching stopper during chemical polishing, and the S layer 4 acts as an etching stopper during mechanical polishing.
It has the effect of eliminating variations in the S1 film thickness of the i-substrate 1,
Although the 5102 layer 4 may be left as is, in this example, the 5101 layer 4 is shown as having been removed.
更に、Ｓｉ基板１０表面には必ずしもＳｉ０２膜２を形
成する必要はなく、その場合にはＳｉ基板６の貼付は面
には予しめＳ１０．膜を形成しておく必要があり、Ｓｉ
基板１，６いずれの貼付は面にもＳ１０．膜を形成して
おいても良く、Ｓｉ基板６は石英板であっても良い。Furthermore, it is not always necessary to form the Si02 film 2 on the surface of the Si substrate 10, and in that case, the Si substrate 6 is attached to the surface in advance in step S10. It is necessary to form a film, and Si
When attaching both substrates 1 and 6, S10. A film may be formed in advance, and the Si substrate 6 may be a quartz plate.
更に、イオン打込みは酸素のみならず窒素であっても良
く、又、酸素と窒素の双方を行っても良い。Furthermore, the ion implantation may be performed not only with oxygen but also with nitrogen, or with both oxygen and nitrogen.
第２図は、本発明の他の実施例を示すＳＯ工基板の製造
工程である。すなわち、
（α） ｓｌ基板１１の表面にはＳ１０．膜１２を形
成し、該ＳｉＯ□膜上にレジスト１３の膜を通常のホト
・エツチング法により図形状に形成し、
（ｂ） その表面から酸素イオン打込みを施し、図示の
如く、素子分離領域となる部分を含んで醗紫イオン打込
み層１４を形成し、レジストを除去して、
（Ｃ） イオン打込み層の活性化の為のアニール処理を
施し、５１０１層１５とＳ１膜１６を形成して、
（ｄ） ｓ１基板１７等の表面を３１基板１１０表面
とをシラノール反応により貼付け、（＊） Ｓｉ基板
１１の裏面より機械研摩と化学エツチング研摩を施し、
３１０□層１５をストッパーとして、Ｓ１膜１６をＳＯ
工榊造に形成する事が出来る。本例の場合は５１０１層
１５は素子分離領域を含んで全面残存させた構造として
いるが、素子分離領域のみ５１０１層１５を残し、５１
０８層１５０表面はエツチング除去されても良い。FIG. 2 shows the manufacturing process of an SO engineered substrate showing another embodiment of the present invention. That is, (α) S10. A film 12 is formed, and a film of resist 13 is formed on the SiO□ film into a figure shape by a normal photo-etching method. (b) Oxygen ions are implanted from the surface to form an element isolation region as shown in the figure. (C) Annealing treatment is performed to activate the ion implantation layer, and a 5101 layer 15 and an S1 film 16 are formed. (d) The surface of the s1 substrate 17 etc. is attached to the surface of the 31 substrate 110 by silanol reaction, (*) mechanical polishing and chemical etching polishing are performed from the back surface of the Si substrate 11,
Using the 310□ layer 15 as a stopper, the S1 film 16 is
It can be formed into Kosakaki-zukuri. In this example, the 5101 layer 15 remains on the entire surface including the element isolation region, but only the element isolation region 5101 layer 15 is left and the 5101 layer 15 is
The surface of the 08 layer 150 may be removed by etching.
本発明により、ＳＯ工構造基板のＳｉ膜を極めて薄く形
成できる効果があると共に、その厚さバラツキも小さく
押える事ができる効果がある。The present invention has the effect that the Si film of the SO-engineered structure substrate can be formed extremely thin, and the variation in the thickness can be kept small.
更に、予しめ素子分離を誘電体分離したＳＯ工基板が提
供できる効果もある。Furthermore, it is possible to provide an SO engineered substrate in which element isolation is dielectrically separated in advance.
第１図（α）〜（−）は本発明の一実施例を示すＳＯ工
基板の製造工程を示す図であり、第２図（α）〜（ａ）
は本発明の他の実施例を示すＳＯ工基板の製造工程を示
す図である。
１．１１，６．１７・・・・・・Ｓｉ基板２．１２
・・・・・−３ｉ Ｏ，膜３．１４ ・
・・・・・酸素イオン打込み層４．１５ ・・・
・・・ＳｉＯ□層５．１６ ・・・・・・Ｓｉ
膜以上
出願人 セイコーエプソン株式会社
代理人 弁理士最上務（他１名）
第１図FIGS. 1(α) to (-) are diagrams showing the manufacturing process of an SO engineered board showing one embodiment of the present invention, and FIGS. 2(α) to (a)
FIG. 3 is a diagram illustrating a manufacturing process of an SO engineered substrate showing another embodiment of the present invention. 1.11, 6.17... Si substrate 2.12
...-3i O, film 3.14 ・
...Oxygen ion implantation layer 4.15 ...
...SiO□ layer 5.16 ...Si
Applicant above: Seiko Epson Co., Ltd. Representative Patent Attorney Mogami (1 other person) Figure 1
Claims (2)
イオンあるいはその双方を打込み、該Ｓｉ基板のイオン
打込み面と石英基板あるいは他のＳｉ基板を貼り合わせ
、前記イオン打込みＳｉ基板の他の主面から機械研摩と
、化学エッチング処理を施し、ＳＯＩ（Ｓｉｌｉｃｏｎ
ＯｎＩｎｓｕｌａｔｏｒ）構造となす事を特徴とする半
導体装置基板の製造方法。(1) Oxygen ions, nitrogen ions, or both are implanted from one main surface of the Si substrate, and the ion-implanted surface of the Si substrate is bonded to a quartz substrate or another Si substrate, and the other main surface of the ion-implanted Si substrate is bonded. The surface is mechanically polished and chemically etched to form an SOI (Silicon
1. A method for manufacturing a semiconductor device substrate, characterized in that the substrate has an on-insulator structure.
て施す事を特徴とする第１項記載の半導体装置基板の製
造方法。(2) The method for manufacturing a semiconductor device substrate according to item 1, wherein the ion implantation is performed through a graphical resist pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5299588A JPH01226168A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5299588A JPH01226168A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01226168A true JPH01226168A (en) | 1989-09-08 |
Family
ID=12930507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5299588A Pending JPH01226168A (en) | 1988-03-07 | 1988-03-07 | Manufacture of semiconductor device substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01226168A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5183769A (en) * | 1991-05-06 | 1993-02-02 | Motorola, Inc. | Vertical current flow semiconductor device utilizing wafer bonding |
| US5383993A (en) * | 1989-09-01 | 1995-01-24 | Nippon Soken Inc. | Method of bonding semiconductor substrates |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
-
1988
- 1988-03-07 JP JP5299588A patent/JPH01226168A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5383993A (en) * | 1989-09-01 | 1995-01-24 | Nippon Soken Inc. | Method of bonding semiconductor substrates |
| US5183769A (en) * | 1991-05-06 | 1993-02-02 | Motorola, Inc. | Vertical current flow semiconductor device utilizing wafer bonding |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| US8389385B2 (en) | 2009-02-04 | 2013-03-05 | Micron Technology, Inc. | Semiconductor material manufacture |
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