JPH01183912A - Input signal switching circuit - Google Patents

Abstract

PURPOSE:To decrease the number of active elements and to simplify a circuit by providing a time constant circuit including a capacitor charged when a first signal is a high level or open and discharged when the said signal is a low level. CONSTITUTION:When an input terminal 8 is a low level and an NPN transistor Q8 is turned off, a code Co3 supplied to a terminal 5 is a low level and the charge accumulated at a capacitor C3 is discharged through a resistance R10 and a diode D2. Next, when the terminal 5 is returned to 'open', the capacitor C3 is charged by a time constant T4 determined by the capacitor C3, resistances R11, R12 and R13 and the potential of a D point is advanced. By the above, when the code Co3 is supplied to the terminal 5, a code Co4 supplied to an input terminal 6 is muted, the code Co3 supplied from an output terminal 7 to the terminal 5 is outputted as a highlevel at the time of the 'open', and the low level is outputted as the low level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input signal switching circuit, in which a plurality of input signals input from a plurality of input terminals are prioritized and one input signal is output. relates to an input signal switching circuit that mutes other input signals.

BACKGROUND OF THE INVENTION FIG. 2 shows a circuit diagram of an input signal switching circuit conventionally used in a VTR. In the same figure, the circuitry inside the broken line indicates the part that is actually implemented as an IC. Input terminal 1
The positive logic signal code Co1 supplied to the input terminal 2 is a serial pulse signal of the operation code of the VTR, and the positive logic signal code Go2 supplied to the input terminal 2 is as follows.
This is the serial pulse signal of the remote control code that has been received, amplified, detected, and waveform shaped in the previous stage.

When a high level code Co1 is input to the input terminal 1, the capacitor C+ is charged by the time constant T1 determined by the resistor R+ * R2 and the capacitor C+, the potential at the 0 point rises, and the NPN transistor QI is turned on. At the same time, the PNP transistor Q2 is also turned on, the capacitor C2 is charged, and the 0 point becomes high level. Therefore, the NPN transistor Q3 is turned off, the code GO2 supplied to the input terminal 2 is muted, and the collector of the NPN transistor Q3 is in an open state. At this time, since the NPNt-transistor Q4 is on, the output terminal 3 becomes low level.

Next, when the code Col returns to low level, the charge stored in the capacitor C1 is discharged with a time constant T2 determined by the resistor RI and the capacitor C1, but here the resistor R
+, by setting R2 to an appropriate value, TI < 72
Then, since the NPN transistor QL remains on for a while after the code CO1 becomes low level, the NPN transistor Q3 is also off during this period, muting the code Co2 supplied to the input terminal 2. Continue to do so. On the other hand, the NPN transistor Q4 has a code Co1
When becomes low level, it is immediately turned off and the collector of NPN transistor Q4 becomes open, but since the output terminal 3 is pulled up by resistor R3, it becomes high level.

From the above, input terminal 1. When the code CO1 is supplied to the input terminal 2, the code GO2 supplied to the input terminal 2 is muted, and the code CO1 supplied from the input terminal 1 is inverted and outputted to the output terminal 3.

Furthermore, when the input terminal 1 remains at a low level for a certain period of time or more, the charge in the capacitor C1 is completely discharged through the resistor R1, the 0 point becomes a low level, and both the NPN transistor Q+ and the PNP transistor Q2 are turned off. TePN
The collector of P transistor Q2 is in an open state,
The mute state of the code GO2 supplied to the input terminal 2 is released. At this time, the collector of NPN transistor Q4 is open. Furthermore, NPN transistor Q3
The base of the input terminal 4 is connected to the base-emitter voltage (V
When the code CO2 supplied from the input terminal 2 becomes high level, the NPN transistors Qs and Qs turn on, and the saturated output resistance of the NPN transistors Qs and Q3 increases. If the sum with the resistor R4 is sufficiently smaller than the resistor R3, a low level signal is output from the output terminal 3.

Next, when a low level signal is supplied to input terminal 2,
The NPN transistor Qs is turned off, the collector of the NPN transistor Qs is in an open state, and since the potential at the 0 point becomes 2V8E, the NPN transistor Q3 is turned off. At this point, the collector of the NPN transistor Q3 becomes open, and a high level signal is output from the output terminal 3 by the pull-up resistor R3.

From the above, if code CO1 is not supplied to input terminal 1 for a certain period of time or more, code G is supplied from input terminal 2.
o2 is inverted and output from the output terminal 3.

Problems to be Solved by the Invention In the conventional circuit shown in FIG. 2, in order to mute the code CO2 supplied to the input terminal 2, the NPN transistor Q1 is
Furthermore, since the muting operation must be performed by the PNP transistor Q2 and the switching must be performed by the NPN transistor Q3, there is a problem that the number of circuit elements increases.

Furthermore, in the circuit shown in Figure 2, input terminals 1 and 2 are both input-only terminals, so two circuits similar to those shown in Figure 2 are provided, and in order to send and receive signals between these circuits, these circuits are required. The problem was that a complicated circuit was required between the comrades.

The present invention was created in view of the above points,
It is an object of the present invention to provide an input signal switching circuit which has a simple circuit configuration and can easily transmit and receive signals by providing two such circuits.

Means for Solving the Problems The input signal switching circuit according to claim 1 has a first terminal to which a first signal of binary logic of high level and low level or open and low level is supplied; A time constant circuit including a capacitor that is charged when the first signal is high level or open and discharged when the first signal is low level; A signal is supplied and the capacitor is charged,
When the base potential is above a predetermined level, the 26th signal is turned on when it is at a low level, and turned off when it is at a high level.
a transistor that outputs a signal from its collector and turns off regardless of the logic level of the second signal to prevent transmission of the second signal when the capacitor is discharged and the base potential is below a predetermined level; an output circuit having at least a pull-up resistor connected to the collector of the transistor and a third terminal corresponding to the second signal when the first signal is not input to the first terminal for a certain period of time or more. outputs the signal from the second terminal connected to the pull-up resistor, and when the first signal is input to the first terminal, it corresponds to the first signal regardless of the logic level of the second signal. The second terminal is configured to output the fourth signal preferentially from the second terminal.

The input signal switching circuit according to claim 2 has a first terminal to which a 28ft logic first signal of open and low level is supplied, and when the first signal is open, it is charged and the first signal is A second signal of binary logic of low level and high level is supplied to a time constant circuit including a capacitor that is discharged when it is at a low level and an emitter, and the capacitor is charged and its base potential is set to a predetermined level. When the second signal is at a low level, the second signal is turned on, and when it is at a high level, it is turned off and outputs the second signal from its collector.When the capacitor is discharged and the base potential is below a predetermined level, the second signal is turned on. an output circuit having at least a transistor that is turned off to prevent transmission of the second signal regardless of the logic level of the second signal; and a pull-up resistor connected to the first terminal and the collector of the transistor; and mouth
an input circuit that supplies a third signal having a level to a connection point between the output circuit and the first terminal;
When there is no input to the terminal for a certain period of time, a fourth signal corresponding to the second signal is output from the second terminal connected to the pull-up resistor, and the first signal is input to the first terminal. When the signal is open, the fifth signal corresponding to the first signal is preferentially output from the second terminal regardless of the logic level of the second signal, and when the first signal is open, the fifth signal is output from the second terminal. The device is configured to output a sixth signal corresponding to the signal from the first terminal.

The working transistor performs switching for the signal supplied to the emitter, and when a high level or open logic level signal is supplied to the first terminal and the capacitor in the time constant circuit is charged, the signal is supplied to the emitter. outputs the signal to the second terminal.

Furthermore, if the logic level of the signal supplied to the first terminal is set to low level and an input circuit is added to the connection point between the first terminal and the output circuit, no signal is supplied to the emitter of the transistor. When a low level signal is supplied from the input circuit to the connection point between the first terminal and the output circuit while the first terminal is open, the first terminal becomes low level. Further, when the connection point between the first terminal and the output circuit is opened from the input circuit, the first terminal becomes open. Therefore, the first terminal can also be used as an output terminal.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the present invention. This is the second
Similar to the figure, this is an embodiment in which the present invention is applied to an input signal switching circuit used in a VTR. In the same figure, 5
9 is a time constant circuit, Q6 is an NPN transistor that is a switching circuit, 10 is an output circuit, and 12 is an input circuit. Further, 11 is a circuit portion that is part of an infrared remote control module IC (not shown). A negative logic signal code Co3 is supplied to the terminal 5, and an input terminal 6 is supplied with the signal code Co3 that receives, amplifies, detects, and
A positive logic signal code Co4 that has been subjected to waveform shaping etc. is supplied. However, the difference is that the logic level of the code Co3 is low and open, whereas the code Co1 of the conventional circuit is high and low.

Terminal 5 is the cathode of diodes D2 and D3 and NPN
Connected to the collector of transistor Q8 and connected to diode D
Node 2 is connected to the base of NPN transistor Q6 via resistors Rm and Ru. Resistance R+o, Ru
The connection point of is connected to the power supply Vcc via the resistor R+a and the capacitor C! is grounded through
A connection point between the resistor Ru and the base of the NPN transistor Q6 is grounded via a resistor Rv.

The base of the NPN transistor Q7 is connected to the input terminal 6, and the emitter is grounded. NPN transistor Q
7 is connected to the power supply Vcc via a resistor R5, and is also connected to the emitter of an NPNt transistor Q6.

The emitter of the NPN transistor Q8 is grounded, the base is connected to the terminal 8, and the collector is connected to the cathode of the diode D3 and the terminal 5. Diode D! The 7th node is connected to the collector of the NPN transistor Q6 and the output terminal 7, and further connected to the voltage IVcc via the resistor RI4.

Next, the operation of the circuit shown in FIG. 1 will be explained.

When the input terminal 8 is at a low level and the NPNt transistor Q8 is off, when the code Co3 supplied to the terminal 5 is at a low level, the charge stored in the capacitor +I03 is transferred to the resistor R16% diode D2. is discharged with a time constant of 3.

As a result, the potential at the 0 point decreases and the NPN transistor Q
6 is turned off regardless of the potential at the 0 point, the collector of the NPN transistor Q6 becomes open, and the code CO4 supplied to the terminal 6 is muted. Also, at this time, diode D3 is turned on and output terminal 7 is connected to diode D.
3, it immediately becomes a low level.

Next, when the terminal 5 returns to open, the capacitor C3 is charged with a time constant T4 determined by the capacitor C3, resistors Ru, RI2, and Ro, and the potential at the 0 point increases. However, if T4 is set well here, the NPN transistor Q6 will remain off for a while after the terminal 5 returns to open, and the code CO4 supplied to the input terminal 6 will continue to be muted. On the other hand, the diode D3 is immediately turned off, and the output terminal 7 becomes high level because it is pulled up by the resistor RI4.

From the above, when the code Co3 is supplied to the terminal 5, the code Co4 supplied to the input terminal 6 is muted, and the code CO3 supplied from the output terminal 7 to the terminal 5 is high level when open, and low level when low level. This will be output as .

Next, when code Co3 is not supplied to terminal 5 for a certain amount of time or more (when terminal 5 is open for a predetermined period or more)
, the capacitor C3 is charged via the resistor Ru, and the potentials at the 0 point and the 0 point rise. In this state, when the code Co4 supplied to the input terminal 6 becomes high level, the NPN transistor Q7 is turned on and the potential at the 0 point is lowered, so that the NPN transistor Q6 is also turned on and the output terminal 7 becomes low level. . Also, when the code CO4 returns to low level, the NPN transistor Q7 turns off, and since the 0 point is pulled up by the resistor R6, the NPN transistor Q7 turns off.
Transistor Q6 is also turned off, and output terminal 7 is connected to resistor R)
By 4, 1 Lua is added and becomes high level.

As described above, when the code CO3 is not supplied for a certain period of time or more, the code CO4 supplied to the input terminal 6 is inverted and output from the output terminal 7.

Furthermore, the code Co3. If input terminal 8 is set to high level when Co4 is not supplied, NPN transistor Q
8 is turned on and the level of E'F5 becomes low. Further, when the input terminal 8 is set to a low level, the NPN transistor Q8 is turned off and the terminal 5 is opened. Therefore, the terminal 5 can also be used as an output terminal. In this case, while outputting a signal pulse from terminal 5, if code C
Even if o3 is supplied to terminal 5, the problem of short circuit between the two signals does not occur because the logic level of code Co3 is low and open.

This has the advantage that when there are two systems 1 having the circuit configuration shown in FIG. 1, data can be exchanged using one signal line by connecting the terminals 5 together.

Although this embodiment shows an example in which a bipolar transistor is used as the active element constituting the circuit, the present invention is not limited to this. Of course, the operation can be realized.

Effects of the Invention As mentioned above, according to the present invention, compared to the conventional circuit, the circuit elements,
In particular, since the number of active elements can be reduced, the circuit configuration can be simplified, reducing costs, and one of the input terminals can be used as an output terminal.
When two similar circuits are provided, it has the advantage that it is possible to send and receive signals between these two circuits using one signal line without causing short-circuits between the two circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional circuit. QI, Qs, Q4, Qs, Q6, Qy, Qa・
”NPN transistor, Q2...PNP transistor, C1, C2, C3...capacitor, GO1~Co4
... code signal, 1.2.4, 6.8 ... input terminal, 3.7 ... output terminal, 5 ... terminal, 9 ... time constant circuit, 10 ... output circuit , 12...input circuit. Patent applicant: Victor Japan Co., Ltd. Patent attorney: Kaneyuki Matsuura 1
. Figure 1 Figure 2

Claims (2)

[Claims] (1) A first terminal to which a first signal of binary logic of high level and low level or open and low level is supplied, and when the first signal is high level or open, it is charged and connected. A time constant circuit including a capacitor that is discharged when the first signal is at a low level, and a second signal having a binary logic of low level and high level are supplied to the emitter;
When the capacitor is charged and its base potential is above a predetermined level, the second signal is turned on when it is at a low level and turned off when it is at a high level, and outputs the second signal from its collector. a transistor that turns off and blocks transmission of the second signal regardless of the logic level of the second signal when the capacitor is discharged and the base potential is below a predetermined level; the first terminal and the transistor; an output circuit having at least a pull-up resistor connected to the collector of the output circuit, and when the first signal is not input to the first terminal for a certain period of time or more, a third signal corresponding to the second signal is output. is output from a second terminal connected to the pull-up resistor, and when the first signal is input to the first terminal, the first signal is output regardless of the logic level of the second signal. An input signal switching circuit characterized in that a fourth signal corresponding to the input signal is outputted preferentially from the second terminal. (2) A first terminal to which a first signal of binary logic of open and low level is supplied; when the first signal is open, it is charged; when the first signal is low level, it is charged; is a time constant circuit including a capacitor to be discharged, and a second logic circuit with low level and high level binary logic at the emitter.
When the second signal is supplied, the capacitor is charged, and its base potential is above a predetermined level, the second signal is turned on when it is at a low level, and turned off when it is at a high level.
The second signal is output from its collector, and when the capacitor is discharged and the base potential is below a predetermined level, the second signal is output from the collector.
an output circuit having at least a pull-up resistor connected to the first terminal and the collector of the transistor; and an input circuit that supplies a third signal having a low level to a connection point between the output circuit and the first terminal, and when the first signal is not input to the first terminal for a certain period of time or more. outputs a fourth signal corresponding to the second signal from the second terminal connected to the pull-up resistor, and when the first signal is input to the first terminal, the fourth signal corresponding to the second signal is output from the second terminal connected to the pull-up resistor. The fifth signal corresponding to the first signal is preferentially output from the second terminal regardless of the logic level of the signal, and when the first signal is open, the third signal An input signal switching circuit characterized in that a sixth signal corresponding to the signal is output from the first terminal.