JPH01145580A - Detecting circuit of abnormal signal - Google Patents

Abstract

PURPOSE:To deliver an abnormality signal even when the period of an input signal is longer than that of a fundamental signal, by providing a detector which compares a counter output one clock before the input signal with the present counter output and delivers an abnormality output when the two counter outputs are in the same state. CONSTITUTION:A QA output of a counter 5 repeats 1010 when the period of a fundamental signal and that of an input signal coincide with each other, and said output turns to be 100...100... when the period of the input signal is longer than that of the fundamental signal, while the counter 5 outputs a count value 3 (decimal) when the period of the input signal is shorter than that of the fundamental signal. Then, the present counter output and a counter output one clock before the input signal are compared with each other by a detector 6, and judgement as normal is made when these outputs are all of different signs, while judgement as abnormal is made and an alarm is delivered when they are of the same sign. According to this method, abnormality can be detected even when the period of the input signal is longer than that of the fundamental signal.

Description

[Detailed Description of the Invention] [Summary] For example, regarding an abnormal signal detection circuit used to detect whether the cycle of an input signal supplied from the outside is normal or not, when the cycle of the input signal becomes long, The purpose of this is to detect abnormalities without error, and to detect the rising edge of the frequency-divided signal obtained by dividing the basic signal, and to detect the rising edge from the frequency-dividing/rising edge detection means. After being initialized with the detection signal.

It is configured to have a counter that counts input signals, and a detector that compares the counter output one clock before the input signal with the current counter output and sends out an abnormal output if they are in the same state.

[Industrial application field]

The present invention relates to an abnormal signal detection circuit used, for example, in detecting whether the cycle of an input signal supplied from the outside is normal or not.

For example, if the device operates using a reference clock supplied from an external clock generator, the cycle may be shortened due to superimposition of high frequency noise on this reference clock, or the cycle may be lengthened due to missing clocks. (If this happens, the device will malfunction.

Therefore, it is necessary to detect whether this reference clock is normal or abnormal by comparing it with the internally generated basic clock, and to send an alarm in the event of an abnormality, but even if the period of the reference clock is longer than the period of the basic clock, It is necessary to be able to detect without error.

[Conventional technology]

4 is a block diagram of the conventional example, FIG. 5 is an explanatory diagram of the operation of FIG. 4, and FIG. 5(a) is an explanatory diagram of the operation when the period of the input signal is equal to the period of the basic signal. (b) shows an explanatory diagram of the operation when the period of the input signal is shorter than the period of the basic signal. The operation shown in FIG. 4 will be explained below with reference to FIG.

First, a basic signal (corresponding to the above basic clock) as shown in Fig. 5 (al-■) is input, and the rising edge detector 1 passes the signal component as it is and a section in which multiple inverters are connected in series. By passing the phase-shifted signal component through the NAND gate, a rising point as shown in FIG. , clear this counter.

On the other hand, since an input signal (corresponding to the above-mentioned reference clock) as shown in FIG. 5 (al-0) is applied to this counter 2, it counts up from 0 to 1.

Since the next rising detection signal is input to the CLR terminal, it is cleared and becomes 0. However, the count value becomes 1 again with the next input signal, but is cleared again with the rising signal, and the operation is repeated (see FIG. 5(a)-(2)).

At this time, Q, , Q, , Q, output of counter 2, inverter 31 . The output of NAND gate 32 is D because of O.
-The output of the FF 33 becomes O, and no alarm of abnormality signal is sent out (see FIG. 5 (al-■)).

Next, as shown in Figure 5(b)-■, when noise is superimposed on the * marked part of the input signal and the period becomes shorter than the basic signal period, the count value of counter 2 is not cleared, so it changes from 1 to 1. 2 (see Figure 5(b)-■). At this time, the output of the counter port is 1, and the output of Q, ,Q is O.
Therefore, l from NAND gate 32 is D-FF 33
The output 1 from this is sent out as an alarm, and an abnormality in the input signal is notified.

[Problem that the invention seeks to solve]

Here, when the period of the input signal is longer than the period of the basic signal, after the counter 2 is cleared by the rising detection signal as shown in FIG. Before the next input signal enters the counter, n rising edge detection signals are input and rearranged n times, so n O's are consecutive.

Since this state is repeated, 01 +QC+Q
There is a problem in that the D output is always O, which is the same state as in the normal state described above, and no abnormality signal alarm is sent out.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 4 is a frequency division/rise detector that detects the rise of a frequency-divided signal obtained by frequency dividing the basic signal, and 5 is a frequency division/rise detector that is initialized with a rise detection signal from the frequency division/rise detection means. After that, there is a counter that counts input signals. Further, 6 is a detector which compares the counter output one clock before the input signal with the current counter output and sends out an abnormal output if they are in the same state.

[Effect]

The present invention detects an abnormality based on how many times the input signal comes during one period of the basic signal, and if the periods of the basic signal and the input signal match, the QA ratio output of the counter 5 is 10.
10 is repeated, and when the input signal is longer than the period of the basic signal, the counter becomes 100...100..., and when the input signal is shorter than the period of the basic signal, the counter becomes the count value 3.
(decimal number) is output.

Therefore, the current counter output and the counter output one clock before the input signal are compared by the detector 6, and if they are of different signs, it is considered normal, and if they are the same, an alarm is sent out as abnormal.

Thereby, an abnormality can be detected even when the period of the input signal is longer than the period of the basic signal.

〔Example〕

2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, FIG. 3(a) is an explanatory diagram of the operation when the input signal is longer than the period of the basic signal, Figure 3 fb) shows an explanatory diagram of the operation when the input signal has a shorter period than the basic signal. Here, the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3, assuming that the frequency division number is 2.

(1) When the input signal is longer than the period of the basic signal, first,
After the frequency of the input basic signal is divided into two by the o-pp 41, the rising point is detected by the rising detector 42, and the counter 5 is cleared with the obtained rising detection signal C (Fig. 3(a)-■
~■See).

On the other hand, since an input signal as shown in FIG. 3fa)-■ is applied to the counter 5, the count value becomes 1 (Qa=1.(1
m・0), but since the counter 5 is cleared by the rising edge detection signal d, the count value becomes 0 (QA=O).

Q* = 0), and in this state it is further cleared by the rising edge detection signal e, and as a result, the QA, Q, and output of the counter 5 become as shown in Figure 3 (a)-〇, ■, so the NAND gate 61 Output 1 from D-FF62 preset (pr
e) applied to the terminal.

Here, if 1 is added to the preset terminal of D-FF 62, the output of the 10th terminal will be delayed by one clock of the QA input to the D terminal, and if 0 is added, 1 will be output regardless of the state of QA. Ru.

Then, the EX-NOR gate 63 compares the QA ratio output one clock before the current QA ratio output input signal, detects an abnormality in the part with the same sign, and by holding this, an alarm is sent out (the (See Figure 3 ta+-■).

(2) When the input signal is shorter than the period of the basic signal (11
After clearing the counter 5 with the rising edge detection signal C in the same manner as in section 3, the counter 5 counts up with the input signal shown in FIG.
, 11, but when both +QA+QB outputs are 1, the counter 5 is cleared by the rising detection signal d, and 9 counts, ,Q,
The output repeats the counting operation from OO (Figure 3 (b)
−〇, see ■).

Now, since the OA ratio output is added to the D terminal of the D-FF 62, the Q terminal output delayed by one clock is obtained and added to the EX-NOR gate 63 as in the case (1). - On the other hand, since the QA ratio output of the counter is directly added here, it is compared and an output as shown in Figure 3 (bl-〇) is obtained, and an alarm indicating a signal abnormality is sent at the point ■. .

In addition, when the pre terminal is O as mentioned above, (Fig. 3 fb) -
Q7 of counter 5 in the * marked part of 〇. NA of QIl output
NO output) The output of the Q terminal is l.

In other words, even if the period of the input signal is longer than the period of the basic signal,
An abnormal signal can be sent even if it is short.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that an abnormal signal can be sent even if the period of the input signal is longer than the period of the basic signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The operation explanatory diagram of FIG. 4 is shown. In the figure, 4 is a frequency division/rise detector, 5 is a counter, and 6 is a detector stand. 77th episode 1 Zugun 2 Diagram (α) ＾, Power'i Bei No. 1 Regular Salary ``9 Figure 4 ■ O■'O・ ■ ■ ■ ■ ■ O■ ■

Claims (1)

[Claims] A frequency division/rise detector (4) detects the rising edge of the frequency-divided signal obtained by frequency dividing the basic signal, and after being initialized with the rising edge detection signal from the frequency dividing/rising detection means, A detector (6) that compares the counter output one clock before the input signal with the current counter output and sends out an abnormal output if they are in the same state. Abnormal signal detection circuit.