JP3282195B2 - Phase difference detection circuit of AC power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference detecting circuit for an AC power supply.

[0002]

2. Description of the Related Art An AC uninterruptible power supply having a first AC power supply for constant power supply and a second AC power supply for emergency power supply and operating in synchronization with each AC power supply is known. There is.

In such an AC power supply device, in order to operate the AC power supplies in synchronization with each other, it is essential to detect a phase difference between the AC power supplies.

A conventional example of the phase difference detection circuit of the AC power supply device described above will be described with reference to FIG.

In FIG. 3, reference numeral 1 denotes a first AC power supply for constant power supply, and 2 denotes a second AC power supply for emergency power supply. Zero-cross detection circuits 3 and 4 for generating signals, a logic circuit 5 for generating and transmitting a phase difference signal in a period corresponding to the phase difference between the AC power supplies based on the zero-cross signal, and an input of the phase difference signal. A counter 6 for counting the number of clock pulses in the period of time being provided, and a monitoring circuit 7 for monitoring the count value of the number of clock pulses and transmitting a phase difference abnormality signal when the count value is equal to or greater than a set value. I have.

The operation of the phase difference detection circuit of the above-described conventional AC power supply will be described with reference to the timing chart of FIG.

Symbols (a) to (f) given to each waveform in FIG.
Corresponds to the points added to the circuit diagram of FIG.
(A) and (b) are the zero cross signal waveforms from the zero cross detection circuits 3 and 4, respectively. The zero cross signal waveform (a) corresponding to the first AC power source 1 and the second AC power source 2 are shown. The phase of the zero cross signal (b) is opposite to that of the zero cross signal (b). (C) is an output waveform from the AND gate 51 in the logic circuit 5, which is an AND output of the zero cross signal waveforms (a) and (b). The output (c) is input to the reset terminal R of the counter 6 and one terminal of the NAND gate 71 in the monitoring circuit 7 via the integrating circuit 52 and the inverter 53, and is directly input to the other terminal of the NAND gate 71. Is also entered. Accordingly, the phase difference signal (d) corresponding to the phase difference is input to the reset terminal R of the counter 6, and the clock from the clock pulse generator 8 is generated by the counter 6 only when the phase difference signal (d) is at the L level. The number of pulses is counted, and the count value is
The signal is sent to the decision unit 72 inside. The determiner 72 sends a signal to the clock input terminal CK of the D flip-flop 73 in the monitoring circuit 7 when the count value reaches the set value. Since the D flip-flop 73 is cleared when the output (e) from the NAND gate 71 changes from the H level to the L level, the signal output from the decision unit 72 changes the Q output from the L level. H
Level, and transmitted as a phase difference abnormality signal (f). In the case of FIG. 4, the D flip-flop 73 is cleared at time t ₀ , and a signal is sent from the determiner 72 to the clock input terminal CK of the D flip-flop 73 at time t ₁ . Then, the Q output of the D flip-flop 73 becomes H level by the signal.

[0008]

In the above-described phase difference detection circuit of the AC power supply device, the output (e) for clearing the D flip-flop 73 causes the Q output of the D flip-flop 73 to once become H level. To the L level, there is a problem that even when a signal is sent from the decision unit 72 to the clock input terminal CK of the D flip-flop 73, the phase difference abnormality signal is canceled.

When the count value of the counter 6 is near the set value for transmitting the abnormal phase difference signal, the abnormal phase difference signal and the change of the Q output from the L level to the H level due to the clearing of the D flip-flop 73 change. There is a problem that the phase difference abnormal signal becomes unstable when approaching.

[0010]

In order to solve the above-mentioned problems, the present invention comprises a first AC power supply for constant power supply and a second AC power supply for emergency power supply. In the phase difference detection circuit of the AC power supply device for detecting the phase difference of
Generating a zero cross signal which rises or falls at the time of a zero cross of the AC power supply voltage of each of the AC power supplies;
Two zero-cross detection circuits, a delay circuit that delays one of the zero-cross signals from the two zero-cross detection circuits and sends out a one-shot signal at one of its rising and falling edges, A logic circuit for generating and transmitting a phase difference signal in a period corresponding to a phase difference between AC power supplies, and counting the number of clock pulses in a period in which the phase difference signal and the clock pulse are input and the phase difference signal is input And a monitoring circuit that monitors the count value of the number of clock pulses and sends out a phase difference abnormality signal when the count value is equal to or greater than a set value. A latch circuit for latching the transmission is provided, and the one-shot signal from the delay circuit is input to the latch circuit so that the phase It is characterized in providing the function of transmitting an abnormality signal.

[0011]

Therefore, according to the present invention, a latch circuit for latching the transmission of the abnormal phase difference signal is provided, and the one-shot signal from the delay circuit is input to the latch circuit to transmit the abnormal phase difference signal. Therefore, a signal for clearing the inside of the monitoring circuit is not sent out like a phase difference abnormal signal.

Further, since the set value of the count value of the number of clock pulses for transmitting the abnormal phase difference signal is given a hysteresis, the abnormal phase difference signal does not become unstable near the set value.

[0013]

Embodiments will be described below with reference to embodiments. FIG. 1 is a circuit diagram of a phase difference detection circuit of an AC power supply device according to the present invention. Portions having the same functions as those in FIG. 3 are denoted by the same reference numerals, and the following description is omitted.

A feature of the present invention is that a zero-cross signal sent from the zero-cross detecting circuit 4 at the time of a zero-cross of the voltage of the second AC power supply 2 is input to the delay circuit 9 and the output of the delay circuit 9 is monitored. 7, and the output from the D flip-flop 73 is transmitted as an abnormal phase difference signal via the latch circuit 74.

The operation of the phase difference detection circuit of the AC power supply according to the present invention will be described with reference to the timing chart of FIG.

Symbols (a) to (h) given to each waveform in FIG.
Correspond to the points added to the circuit diagram of FIG. 1, and (a) to (f) are the same as the waveforms of FIG. In the case of FIG. 2, at time t ₁ , a signal is sent from the decision unit 72 to the clock input terminal CK of the D flip-flop 73 and the D flip-flop 7
The Q output of No. 3 becomes H level, but its output (f) is not transmitted as it is as a phase difference abnormal signal. That is,
Output (f) is input to the D terminal of the latch circuit 74, the input signal of the D terminal by an output from the delay circuit 9 (g) is inputted to the clock input terminal CK of the latch circuit 74 at time t ₂ Is output to the Q output as a signal (h). When the signal (h) changes from the L level to the H level, a phase difference abnormality is displayed, and when the signal (h) changes from the H level to the L level, it indicates that the signal has returned to the normal state. Therefore, while the output (h) is at the H level, the abnormal phase difference signal is being transmitted.

Normally, when such a phase difference abnormality occurs, the phase difference abnormality acts between the first and second AC power supplies, and the output (h) changes from the H level to the L level in the subsequent cycle. Will change. Therefore, the output (h) is input to the determiner 72 and the set value is given a hysteresis to prevent the transmission of the abnormal phase difference signal from becoming unstable.

In the above embodiment, the zero cross detection circuits 3 and 4 are operated every cycle of the first and second AC power supplies 1 and 2 using the AND gate 51 in the logic circuit 5. By using an EX-OR circuit instead of the AND gate 51, each zero cross detection circuit 3,
4 can also be operated.

[0019]

As described above, according to the present invention, the abnormal phase difference signal can be stably transmitted, and the first and second phase difference abnormal signals can be transmitted.
The synchronous operation between the AC power supplies can be easily performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a phase difference detection circuit of an AC power supply device of the present invention.

FIG. 2 is a timing chart of the above circuit.

FIG. 3 is a circuit diagram of a phase difference detection circuit of a conventional AC power supply device.

FIG. 4 is a timing chart of the above circuit.

[Explanation of symbols]

 3 Zero cross detection circuit 4 Zero cross detection circuit 5 Logic circuit 6 Counter 7 Monitoring circuit 9 Delay circuit

Claims (2)

(57) [Claims] [Claim 1 further comprising a first AC power source constantly feeding, and a second AC power supply for emergency power supply, the phase between the AC power source
In a phase difference detection circuit of an AC power supply for detecting a difference,
Generating a zero cross signal which rises or falls at the time of a zero cross of the AC power supply voltage of each of the AC power supplies;
Two zero cross detection circuits, and the two zero cross detection circuits
Delays one of the zero-cross signals from
Or send a one-shot signal at one of the falling edges
Output a delay circuit, and a phase difference signal is created in a period corresponding to the phase difference between each AC power source by each of the zero cross signals .
A logic circuit to send , the phase difference signal and a clock pulse
Counter and, the clock but is input, counts the number of clock pulse duration which phase difference signal is input
Have a monitoring circuit for sending a phase difference abnormality signal when the count value is equal to or greater than the set value by monitoring the count value of the pulse number
And the phase difference abnormality signal is sent to the monitoring circuit.
A latch circuit for latching the latch
Input the one-shot signal from the delay circuit
Phase difference detecting circuit of the AC power supply apparatus characterized by having a function of sending out the phase difference error signal by the. 2. A clock pulse for transmitting a phase difference abnormal signal.
2. The phase difference detecting circuit according to claim 1, wherein a hysteresis is given to a set value of the count value of the number of pulses .