JPH01300563A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent wire breaking and bridge of a wiring part formed later by inclining a polysilicon edge and grading drain concentration. CONSTITUTION:Ion implantation of phosphorous is executed after coating a polysilicon 13, and a part to form a gate is covered with a photoresist 15 and the polysilicon 13 at the part not covered with the photoresist is dry-etched. Accordingly, since the place high in impurity concentration at the surface has a great etching rate, the polysilicon edge has an inclination. Next, the photoresist 15 is removed, and ion implantation of source drain is executed, and by the inclination of the edge of the polysilicon 13, source drain concentration is graded. Thereafter, when required thermal oxidation is executed after source drain annealing, jumping of the polysilicon is restrained. Hereby, wire breaking and bridge of a wiring part formed later becomes hard to occur.

Description

[Detailed description of the invention] Industrial applications The present invention relates to manufacturing semiconductor devices.

Prior Art A conventional manufacturing method is shown in FIG. In FIG. 2(a), a thermal oxide film 12 is grown on a P-type silicon substrate 11, and polysilicon is deposited thereon.

In FIG. 2(b), the portion where the gate will be formed is covered with photoresist, and the polysilicon portion not covered with the photoresist is dry-etched.

In FIG. 2C, the photoresist is removed and impurities are introduced into the source and drain regions by, for example, ion implantation of 10@15 arsenic.

Figure 2(d) shows that after annealing the introduced impurities,
It was subjected to thermal oxidation.

Problems to be Solved by the Invention In such a conventional method, there is a problem in that the drain breakdown voltage becomes low because the electric field is concentrated between the gate oxide film 12 and the drain 16 shown in FIG. 3(d).

In addition, as shown in Figure (d) 18, polysilicon bulges out, which impairs the flow condition of the interlayer insulating film that is subsequently deposited, and can also cause disconnections and bridges in the interconnects that are subsequently formed. Become.

Means for Solving the Problem The etching rate of the polysilicon surface is increased so that the polysilicon edges have a slope. Add a scent to the drain concentration.

If the source/drain region is formed by ion implantation using an appropriate accelerating voltage with the film thickness at the edge of the active polysilicon being sloped, the drain concentration will be affected, and the subsequent oxidation process will increase the film thickness of the polysilicon. Even if the thin area lifts up, it will not rise above the thick area.

Embodiment An embodiment of the present invention will be described with reference to FIG. In FIG. 1, the same parts as in FIG. 2 are given the same numbers.

Figure 1(a) shows that after the polysilicon has been deposited in the same way as in Figure 2, 10I6eta-
Phosphorus ion implantation was performed on the order of 2.

In FIG. 1(b), the portion where the gate is to be formed is covered with photoresist 15, and the polysilicon portion not covered with the photoresist is dry-etched. Since the etch rate is high in areas with high impurity concentration on the surface, the polysilicon edge has this slope. Figure 1 (C) is
The photoresist has been removed and source/drain ions have been implanted. Since the edges of polysilicon have a slope, the source/drain concentration has a scent.

In FIG. 1(d), necessary thermal oxidation was performed after source/drain annealing. Splashing of polysilicon is suppressed.

Effects of the Invention As described above, according to the present invention, when polysilicon is formed, disconnection and bridging of wiring portions formed later are less likely to occur.

In this embodiment, the case of an NMOS transistor has been explained, but it goes without saying that it can also be used for PMOS and CMOS.

[Brief explanation of the drawing]

FIG. 1 is a sectional view in the order of manufacturing steps of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view in order of the manufacturing steps of a conventional semiconductor device. 11...P-type silicon substrate, 12...
Gate oxide film, 13... Polysilicon, 14.
...Impurity (phosphorus), 15...Photoresist, 16...Source/drain region, 17...
...Thermal oxide film. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2

Claims (1)

[Claims] In a MOS transistor, by forming sloped surfaces at both ends of a polysilicon electrode that will become the gate electrode, and then implanting ions into the regions that will become the gate and source/drain, the source/drain concentration distribution at the end of the gate electrode can be changed. A method for manufacturing a semiconductor device, characterized in that the angle of inclination of the end portion is controlled accordingly, and later a thin portion of polysilicon is partially removed by oxidation to obtain a required transistor.