JPH01125541U - - Google Patents
Info
- Publication number
- JPH01125541U JPH01125541U JP1988021139U JP2113988U JPH01125541U JP H01125541 U JPH01125541 U JP H01125541U JP 1988021139 U JP1988021139 U JP 1988021139U JP 2113988 U JP2113988 U JP 2113988U JP H01125541 U JPH01125541 U JP H01125541U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- bonding
- component chip
- chip
- wire connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案ワイヤボンデイング用パツドを
形成した回路基板の平面図、第２図は従来のボン
デイング用パツドを形成した回路基板の平面図で
ある。
１は回路基板（パツケージ）、２は部品チツプ
、３１，３２，３３はワイヤボンデイング用パツ
ド、３′は不良パツド、４は導体パターン、５は
導体スルーホール、６はチツプ側端子、７はボン
デイングワイヤである。
FIG. 1 is a plan view of a circuit board on which a wire bonding pad of the present invention is formed, and FIG. 2 is a plan view of a circuit board on which a conventional bonding pad is formed. 1 is a circuit board (package), 2 is a component chip, 31, 32, 33 are wire bonding pads, 3' is a defective pad, 4 is a conductor pattern, 5 is a conductor through hole, 6 is a chip side terminal, 7 is a bonding It's a wire.
Claims (1)
チツプの端子６と、回路基板上に形成してあるボ
ンデイング用パツドとの間をワイヤボンデイング
７にて接続する構造において、部品チツプ２の１
端子６あたり複数のボンデイング用パツド３１，
３２，３３を形成したことを特徴とする、回路基
板のワイヤ接続用パツドパターン。 ２ ボンデイング用パツド３１，３２，３３は対
応する部品チツプ２の端子６に対し一直線上に複
数配列されている請求項１記載のワイヤ接続用パ
ツドパターン。[Claims for Utility Model Registration] 1. A component chip 2 is mounted on a circuit board 1, and a wire bonding 7 is used to connect the terminal 6 of the component chip to a bonding pad formed on the circuit board. In the structure, part chip 2, 1
Multiple bonding pads 31 per terminal 6,
A pad pattern for wire connection of a circuit board, characterized in that 32 and 33 are formed. 2. The wire connection pad pattern according to claim 1, wherein a plurality of bonding pads (31, 32, 33) are arranged in a straight line with respect to the terminals (6) of the corresponding component chip (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988021139U JPH01125541U (en) | 1988-02-22 | 1988-02-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988021139U JPH01125541U (en) | 1988-02-22 | 1988-02-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125541U true JPH01125541U (en) | 1989-08-28 |
Family
ID=31238104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988021139U Pending JPH01125541U (en) | 1988-02-22 | 1988-02-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125541U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012094866A (en) * | 2010-10-22 | 2012-05-17 | Paragon Semiconductor Lighting Technology Co Ltd | Multi-chip package having direct electric connection with alternating current power supply |
-
1988
- 1988-02-22 JP JP1988021139U patent/JPH01125541U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012094866A (en) * | 2010-10-22 | 2012-05-17 | Paragon Semiconductor Lighting Technology Co Ltd | Multi-chip package having direct electric connection with alternating current power supply |