JPH0964734A - Pll circuit and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change an oscillation output of the PLL circuit at a low frequency interval at a high frequency band and to reduce a time till an oscillating frequency of a PLL circuit is locked to a desired frequency with a simple circuit configuration. SOLUTION: A mixer circuit 13 mixes signals whose frequencies are f1, f2 from voltage controlled oscillator circuits 11, 12. A band pass filter 15 extracts a component whose frequency is f1-f2 in output signals of the mixer circuit 13 and a frequency divider circuit 16 divides the component into 1/N. A phase comparator circuit 17 compares a phase of an output signal of the frequency divider circuit 16 with a phase of a signal with a reference frequency fr. A low frequency component in the output signal of the phase comparator circuit 17 is extracted by a low pass filter 18 and its output voltage Vc controls oscillating frequencies f1, f2 of the voltage controlled oscillators 11, 12 so that a relation of f1-f2=N.fr is obtained. A component whose frequency is f1+f2 in output signals from the mixer circuit 13 is extracted by a band pass filter 14 as an oscillation output of the PLL circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit (phase-locked loop) and a telephone such as a mobile phone or a mobile phone or a receiver such as a radio receiver or transceiver using the PLL circuit.

[0002]

2. Description of the Related Art PLL circuits are widely used in equipment such as radio receivers and transceivers to obtain signals for channel selection and frequency conversion.

As shown in FIG. 4, this PLL circuit basically comprises a voltage controlled oscillator circuit 71, a frequency divider circuit 72, a phase comparison circuit 73 and a low pass filter 74. A signal whose output frequency is fo is divided in the frequency dividing circuit 72 by a frequency division ratio 1 / N set by the signal Sn from the terminal 77, and the frequency of the output of the frequency dividing circuit 72 is fo / N. In the phase comparison circuit 73, the signal is phase-compared with the signal of the reference frequency fr from the terminal 79, and the low-pass component in the output signal of the phase comparison circuit 73 is taken out by the low-pass filter 74.

The output voltage Vc of the low pass filter 74 causes the frequency f of the output signal of the frequency dividing circuit 72.
so that o / N matches the reference frequency fr, that is, f
The oscillation frequency fo of the voltage control oscillation circuit 71 is controlled so that o = N · fr, and the oscillation signal of the voltage control oscillation circuit 71 is taken out as the oscillation output of the PLL circuit.
Then, by changing N, the oscillation output frequency fo can be changed in steps of fr.

The frequency dividing circuit 72 and the phase comparing circuit 7
The part 3 is integrated as a PLL IC, for example, and N can be controlled from the outside.

In such a PLL circuit, the oscillation frequency fo of the voltage controlled oscillation circuit 71 must be increased and the reference frequency fr in the phase comparison circuit 73 must be lowered in order to obtain an oscillation output of a high frequency. There are cases.

For example, in a digital cellular mobile phone, the received signal of the phone is set to a high frequency such as 1.5 GHz band and the channel interval is 25.
It is spaced at a low frequency such as kHz, and
The received signal with the channel interval of 25 GHz in the 5 GHz band is frequency-converted into the first intermediate frequency of 100 MHz,
Further, the signal of the first intermediate frequency is frequency-converted into the second intermediate frequency of 500 kHz.

Therefore, when the above PLL circuit is used for tuning a digital cellular mobile phone, for example,
The oscillation frequency fo of the voltage controlled oscillation circuit 71 is 1.6 GHz.
Band, the reference frequency fr is set to 25 kHz, and the oscillation output of the PLL circuit is set to 2 in the 1.6 GHz band.
It is necessary to be able to change at intervals of 5 kHz.

However, as described above, the voltage controlled oscillator circuit 71
Of the reference frequency fr
In the case of lowering the frequency, it is necessary to increase the frequency division number N in the frequency dividing circuit 72, and there is an inconvenience that it takes time for the oscillation frequency fo of the voltage controlled oscillation circuit 71 to lock to the desired frequency.

Further, when the frequency dividing circuit 72 and the phase comparing circuit 73 are integrated into an IC as described above, an IC capable of handling high frequencies is required.

Therefore, a mixing down type PLL circuit or a mixing up type PLL circuit provided with two PLL circuit sections each having a voltage controlled oscillator circuit, a frequency divider circuit, a phase comparison circuit and a low pass filter. Is being considered.

In the mixing down type PLL circuit, as shown in FIG. 5, one PLL circuit section 80 includes a voltage controlled oscillator circuit 81, a mixing circuit 85, a band pass filter 86,
It is composed of a frequency dividing circuit 82, a phase comparison circuit 83 and a low pass filter 84, and the other PLL circuit section 90 is composed of a voltage controlled oscillator circuit 91, a frequency dividing circuit 92, a phase comparison circuit 93 and a low pass filter 94.

In the PLL circuit section 80, the signal whose frequency of output of the voltage controlled oscillation circuit 81 is fo is output to the mixing circuit 8
5, the voltage controlled oscillator circuit 91 of the PLL circuit unit 90
Is mixed with the signal of fx whose frequency is lower than fo, and the frequency in the output signal of the mixing circuit 85 is fo-
The fx component is extracted by the bandpass filter 86.

Further, a signal whose frequency of output is fo-fx of the band pass filter 86 is divided by the signal Sn from the terminal 87 in the frequency dividing circuit 82, and the frequency division ratio 1 is set.
The frequency of the output of the frequency dividing circuit 82 is (fo-fx) / N, and the oscillation output of the fixed oscillation circuit 88 is frequency-divided by the frequency dividing circuit 89 in the phase comparison circuit 83. The obtained signal is compared in phase with the signal of the reference frequency fr1 and the low-pass component in the output signal of the phase comparison circuit 83 is extracted by the low-pass filter 84.

The output voltage of the low pass filter 84 causes the frequency (fo) of the output signal of the frequency dividing circuit 82.
The oscillation frequency fo of the voltage controlled oscillation circuit 81 is controlled so that −fx) / N matches the reference frequency fr1, that is, fo−fx = N · fr1.

In the PLL circuit section 90, a signal whose frequency of the output of the voltage controlled oscillation circuit 91 is fx is divided by the frequency dividing circuit 9
2, the frequency is divided by the frequency division ratio 1 / N set by the signal Sn from the terminal 87, and the signal whose frequency of the output of the frequency dividing circuit 92 is fx / N is input to the phase comparison circuit 93.
The oscillation output of the fixed oscillation circuit 88 is phase-compared with the signal of the reference frequency fr2 obtained by frequency division by the frequency division circuit 99, and the low frequency component in the output signal of the phase comparison circuit 93 is
It is taken out by the low pass filter 94.

The output voltage of the low-pass filter 94 causes the frequency fx / of the output signal of the frequency dividing circuit 92.
So that N matches the reference frequency fr2, that is, fx
The oscillation frequency fx of the voltage-controlled oscillation circuit 91 is controlled so that = N · fr2.

The reference frequencies fr1 and fr2 are, as is clear from the above equation, fr2 / fr1 = fx / (fo-f
x). Then, the oscillation signal of the voltage controlled oscillation circuit 81 of the PLL circuit unit 80 is taken out as the oscillation output of the PLL circuit including the PLL circuit units 80 and 90.

According to this mixing down type PLL circuit, the frequency dividing circuit 82 and P of the PLL circuit section 80 are provided.
The frequency dividing number N in the frequency dividing circuit 92 of the LL circuit unit 90 is the frequency dividing number N in the frequency dividing circuit 72 of the PLL circuit shown in FIG.
It can be smaller than

For example, when the oscillation output of the PLL circuit is changed at 25 kHz intervals in the 1.6 GHz band as described above, the frequency division number N is 64,0 in the PLL circuit shown in FIG.
In the mixing down type PLL circuit shown in FIG. 5, for example, the oscillation frequency fx of the voltage controlled oscillation circuit 91 is 0.8 GHz.
If the band is set and fr1 = fr2 = 25 kHz, the frequency division number N may be changed around 32,000. However, in that case, the frequency dividing circuit 99 is not necessary, and the output signal of the frequency dividing circuit 89 may be supplied to the phase comparison circuit 93.

Therefore, the mixing down type PL
According to the L circuit, the time until the oscillation frequency fo of the PLL circuit is locked at the desired frequency is shortened.

Although not shown, the mixing-up type PLL circuit has a PLL circuit section such as the PLL circuit section 90 of FIG. 5 having a voltage controlled oscillation circuit having an oscillation frequency of fx, and a voltage having an oscillation frequency of fy. Having a controlled oscillator circuit,
Similarly, a PLL circuit unit such as the PLL circuit unit 90 of FIG. 5 is provided, and the oscillation outputs of the voltage controlled oscillation circuits of both are mixed in the mixing circuit, and the frequency in the output signal of the mixing circuit is fo = fx + fy. The component is extracted as the oscillation output of the PLL circuit.

Also in this mixing-up type PLL circuit, the frequency division number in the frequency dividing circuit of each PLL circuit section can be made small, and the time until the oscillation frequency fo of the PLL circuit is locked to the desired frequency is shortened. Be converted.

[0024]

However, the above-mentioned mixing-down type or mixing-up type PLL circuit has two independent circuits each having a voltage controlled oscillator circuit, a frequency dividing circuit, a phase comparison circuit and a low pass filter. Since the PLL circuit section is provided, there is a drawback that the circuit configuration of the entire PLL circuit becomes complicated.

Therefore, according to the present invention, the oscillation output of the PLL circuit can be changed at a low frequency interval in a high frequency band, and the frequency division number can be reduced to make the
In order to shorten the time until the oscillation frequency of the L circuit locks to the desired frequency, even when using two variable frequency oscillation circuits, the frequency dividing circuit, the phase comparison circuit and the low pass filter are One for each, PLL
The circuit configuration of the entire circuit can be simplified.

[0026]

According to the present invention, the PLL circuit includes a first variable frequency oscillation circuit and a second variable frequency oscillation circuit having an oscillation frequency lower than the oscillation frequency of the first variable frequency oscillation circuit. And a mixing circuit that mixes the oscillation outputs of the first and second variable frequency oscillation circuits to obtain an oscillation signal of the sum and difference frequencies of the oscillation frequencies of the first and second variable frequency oscillation circuits. A frequency divider circuit that divides the oscillation signal of the difference frequency, a phase comparison circuit that compares the output signal of this frequency divider circuit with the signal of the reference frequency, and a low-frequency component in the output signal of this phase comparison circuit. A low pass filter for controlling the oscillation frequencies of the first and second variable frequency oscillation circuits is provided, and an oscillation signal of the sum frequency is taken out as an oscillation output of the PLL circuit.

In the PLL circuit of the present invention thus constructed, the difference fd between the oscillation frequency f1 of the first variable frequency oscillation circuit and the oscillation frequency f2 of the second variable frequency oscillation circuit from the mixing circuit is fd = An oscillation signal having a frequency of f1-f2 is obtained by dividing the frequency by 1 / N, and a signal having a frequency of fd / N = (f1-f2) / N of the output of the frequency dividing circuit is
The phase comparison circuit performs phase comparison with the signal of the reference frequency fr, and the low-frequency component in the output signal of the phase comparison circuit causes the frequency fd / N = (f1-f of the frequency division circuit output signal.
Oscillation frequencies f1 and f2 of the first and second variable frequency oscillator circuits are controlled so that 2) / N matches the reference frequency fr, that is, f1-f2 = N · fr.

Therefore, the oscillation output of the PLL circuit can be changed at low frequency intervals in the high frequency band, and the frequency division number N in the frequency divider circuit can be reduced, so that the oscillation frequency fa of the PLL circuit becomes the desired frequency. The time to lock can be shortened.

For example, if the oscillation output of the PLL circuit is 1.6 G
When the frequency is changed at intervals of 25 kHz in the Hz band, as an example, the oscillation frequency f1 of the first variable frequency oscillation circuit is 0.
In the 85 GHz band, the oscillation frequency f2 of the second variable frequency oscillation circuit is in the 0.75 GHz band, fr = 10 kHz, and the frequency division number N is 100 MHz / 10 kHz = 10,0.
You can change it around 00.

Further, in the present invention, as a receiver, the received signal is frequency-converted by the oscillation signal of the above sum frequency fa = f1 + f2, which is the oscillation output of the PLL circuit of the present invention.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment of the Invention of Claim 1] FIG. 1 shows an embodiment of a PLL circuit of the invention of claim 1.

The PLL circuit 10 of this embodiment includes two voltage controlled oscillation circuits 11 and 12, a mixing circuit 13, two band pass filters 14 and 15, a frequency divider circuit 16, a phase comparison circuit 17 and a low pass filter. It comprises a filter 18. The oscillation frequencies f1 and f2 of the voltage controlled oscillation circuits 11 and 12 are different from each other. That is, f1> f2.

In the PLL circuit 10, the signals having the frequencies f1 and f2 of the outputs of the voltage controlled oscillation circuits 11 and 12 are mixed in the mixing circuit 13, and the mixing circuit 13 is mixed.
The component whose output signal has a frequency of fa = f1 + f2 is extracted by the bandpass filter 14, and the component whose output signal of the mixing circuit 13 has a frequency of fd = f1-f2 is extracted by the bandpass filter 15.

Further, the signal whose frequency of the output of the band pass filter 15 is fd = f1-f2 is divided by the frequency division circuit 16 by the signal Sn from the terminal 21 in the frequency division circuit 16.
The frequency of the output of the frequency dividing circuit 16 is f
The signal of d / N = (f1-f2) / N is the phase comparison circuit 1
7, the phase comparison is performed with the signal of the reference frequency fr from the terminal 22, and the low-pass component in the output signal of the phase comparison circuit 17 is taken out by the low-pass filter 18.

The output voltage Vc of the low pass filter 18 causes the frequency f of the output signal of the frequency dividing circuit 16 to be changed.
Oscillation frequencies f1 and f of the voltage controlled oscillation circuits 11 and 12 so that d / N = (f1−f2) / N matches the reference frequency fr, that is, f1−f2 = N · fr.
2 is controlled.

Here, in the voltage controlled oscillation circuits 11 and 12,
As shown by the solid lines F1 and F2 in FIG. 2, the characteristics of changes in the oscillation frequencies f1 and f2 with respect to the control voltage Vc are shown in solid lines F1 and F2. ) Kv1 and Kv2 are made different from each other.

This is because when the change rates Kv1 and Kv2 of the oscillation frequencies f1 and f2 with respect to the control voltage Vc are equal, the frequency fd = f1-f2 of the above difference is relative to the control voltage Vc as indicated by a broken line Fd in FIG. Does not change and always becomes a constant value, and the frequency f of the above sum, which is the oscillation frequency of the PLL circuit,
This is because a = f1 + f2 cannot be controlled by the control voltage Vc.

As the change rates Kv1 and Kv2 of the oscillation frequencies f1 and f2 with respect to the control voltage Vc are made different, the characteristic of the change of the sum frequency fa = f1 + f2 with respect to the control voltage Vc is as shown by the solid line Fa in FIG. Then, the difference frequency fd = f1-f2 is controlled as shown by the broken line Fd in FIG. 2, so that the oscillation frequency fa = f of the PLL circuit
1 + f2 can be controlled.

Therefore, the oscillation frequency fa of the PLL circuit
The control amount of = f1 + f2 is determined by the change rates Kv1 and Kv2 of the oscillation frequencies f1 and f2 with respect to the control voltage Vc.

For example, if the oscillation output of the PLL circuit 10 is 1.
When the frequency is changed at 25 kHz intervals in the 6 GHz band, the oscillation frequency f1 of the voltage controlled oscillator circuit 11 is set to 0.
In the 85 GHz band, the oscillation frequency f2 of the voltage controlled oscillator circuit 12 is in the 0.75 GHz band, fr = 10 kHz, and the frequency division number N is 100 MHz / 10 kHz = 10,000.
You can change it around 0.

In this case, when N = 9,999, f1 = 0.85 GHz-17.5 kHz, f2 = 0.75 GHz-7.5 kHz, fd = f1-f2 = 100 MHz-10 kHz, fa = f1 + f2 = 1.6 GHz-25 kHz, and when N = 10,000, f1 = 0.85 GHz ± 0 kHz, f2 = 0.75 GHz ± 0 kHz, fd = f1-f2 = 100 MHz ± 0 kHz, fa = f1 + f2 = 1. 6 GHz ± 0 kHz, and when N = 10,001, f1 = 0.85 GHz + 17.5 kHz, f2 = 0.75 GHz + 7.5 kHz, fd = f1-f2 = 100 MHz + 10 kHz, fa = f1 + f2 = 1.6 GHz + 25 kHz, .

Therefore, the oscillation output of the PLL circuit 10 can be changed at low frequency intervals in the high frequency band, and the frequency division number N in the frequency dividing circuit 16 can be reduced, so that the oscillation frequency fa of the PLL circuit 10 can be reduced. The time required to lock to the desired frequency can be shortened.

According to the first aspect of the present invention, the oscillation output of the PLL circuit 10 can be changed at low frequency intervals in the high frequency band as described above, and the frequency division number N can be reduced to reduce the frequency division number N. In order to shorten the time until the oscillation frequency fa of 10 locks to the desired frequency, two voltage controlled oscillation circuits 1
Even when 1 and 12 are used, the frequency dividing circuit, the phase comparing circuit and the low pass filter may be one each as shown by the frequency dividing circuit 16, the phase comparing circuit 17 and the low pass filter 18, and the PLL circuit may be used. The circuit configuration of the entire 10 can be simplified.

A current controlled oscillator circuit can be used as the first and second variable frequency oscillator circuits.

[Embodiment of the Invention of Claims 2 and 3] FIG.
Shows an embodiment of the receiver of the invention of claims 2 and 3.

In this embodiment, the inventions of claims 2 and 3 are applied to a digital cellular mobile phone, and a received signal with a channel interval of 25 GHz in the 1.5 GHz band is obtained.
100 MHz by the oscillation output of the PLL circuit 10 of the invention
The frequency is converted to the first intermediate frequency fi1 of z, and the signal of the first intermediate frequency fi1 is further converted into the second intermediate frequency fi of 500 kHz by the oscillation signal from the fixed oscillation circuit 23.
This is the case of frequency conversion into 2.

That is, 1.5 GH from the antenna 31
The channel spacing of the 1.5 GHz band received by the band pass filter 32 having the z band as the pass band is 25 kHz.
The received signal of z is passed through the amplifier circuit 33 to the first mixing circuit 3
4 is supplied. Further, the sum frequency fa = from the band pass filter 14 of the PLL circuit 10 shown in FIG.
The oscillation signal of f1 + f2 is supplied to the first mixing circuit 34.

In this case, fb = from the fixed oscillation circuit 23
The oscillation signal having a frequency of fi1 + fi2 = 100.5 MHz is frequency-divided by the frequency dividing circuit 24 at a predetermined frequency division ratio,
A signal having a frequency of fr = 10 kHz is obtained from the frequency dividing circuit 24, and the signal having a frequency of fr = 10 kHz from the frequency dividing circuit 24 is supplied to the phase comparison unit 17 of the PLL circuit 10 as described above.

In the PLL circuit 10, as described above, for example, the oscillation frequency f1 of the voltage controlled oscillation circuit 11 is 0.85.
In the GHz band, the oscillation frequency f2 of the voltage controlled oscillation circuit 12
Is set to 0.75 GHz band, fr = 10 kHz, and the frequency division number N in the frequency dividing circuit 16 is changed around 10,000 to set the sum frequency fa = f1 + f2, which is the oscillation frequency of the PLL circuit 10, to 1. 1 from 5 GHz
It is arranged such that it can be changed at intervals of 25 kHz centered on 1.6 GHz, which is higher by 00 MHz.

Then, in the first mixing circuit 34, the reception signal and the oscillation output of the PLL circuit 10 which is 100 MHz higher than the frequency f0 of the reception signal are mixed, so that the first mixing circuit 34 outputs the first intermediate signal. A signal of 100 MHz having a frequency fi1 and a signal having a frequency of 2f0 + fi1 are obtained.

The signal from the first mixing circuit 34 is the first
The signal of fi1 = 100 MHz is supplied from the first intermediate frequency circuit 35 to the first intermediate frequency circuit 35 having a characteristic of passing the band centered on the intermediate frequency fi1 and the signal of 100 MHz is mixed with the second mixed signal. It is supplied to the circuit 36. In addition, fb = 10 from the fixed oscillation circuit 23
The oscillation signal having a frequency of 0.5 MHz is supplied to the second mixing circuit 36.
Is supplied to.

Therefore, from the second mixing circuit 36, a signal of 500 kHz which is the second intermediate frequency fi2 and a signal of the frequency fb + fi1 are obtained.

The signal from the second mixing circuit 36 is the second
It is supplied to the second intermediate frequency circuit 37 having a characteristic of passing a band centered on the intermediate frequency fi2, a signal of fi2 = 500 kHz is taken out from the second intermediate frequency circuit 37, and the signal of 500 kHz is output to the demodulation circuit 38. Is supplied to and demodulated. After demodulation, although not shown, digital processing as a digital cellular mobile phone is performed.

The inventions of claims 2 and 3 as a receiver can be applied to a radio receiver, a transceiver and the like.

[0055]

As described above, according to the present invention, P
It is possible to change the oscillation output of the LL circuit at low frequency intervals in a high frequency band, and shorten the time until the oscillation frequency of the PLL circuit locks to the desired frequency by reducing the frequency division number. To
Even when two variable frequency oscillation circuits are used, only one frequency divider circuit, one phase comparison circuit, and one low pass filter are required, and the circuit configuration of the entire PLL circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a PLL circuit of the present invention.

FIG. 2 is a characteristic diagram for explaining the PLL circuit of FIG.

FIG. 3 is a block diagram showing an example of a receiver of the present invention.

FIG. 4 is a block diagram showing a basic configuration of a PLL circuit.

FIG. 5 is a block diagram showing a mixing down type PLL circuit.

[Explanation of symbols]

 10 PLL Circuit 11 Voltage Controlled Oscillation Circuit (First Variable Frequency Oscillation Circuit) 12 Voltage Controlled Oscillation Circuit (Second Variable Frequency Oscillation Circuit) 13 Mixing Circuit 14 Bandpass Filter 15 Bandpass Filter 16 Frequency Divider 17 Phase Comparison Circuit 18 Low pass filter

Claims (3)

[Claims] 1. A first variable frequency oscillator circuit, a second variable frequency oscillator circuit having an oscillation frequency lower than the oscillation frequency of the first variable frequency oscillator circuit, and the first and second variable frequency oscillator circuits. A mixing circuit for obtaining the oscillation signals of the sum and difference frequencies of the oscillation frequencies of the first and second variable frequency oscillation circuits, and a frequency divider for dividing the oscillation signals of the difference frequency. Circuit, a phase comparison circuit that compares the phase of the output signal of the frequency divider circuit with a signal of the reference frequency, and the oscillation of the first and second variable frequency oscillation circuits due to the low-frequency components in the output signal of the phase comparison circuit. A PLL circuit that includes a low-pass filter that controls the frequency, and extracts an oscillation signal of the sum frequency as an oscillation output of the PLL circuit. 2. A receiver for frequency-converting a received signal by an oscillation signal of the sum frequency of the PLL circuit according to claim 1. 3. The PLL circuit according to claim 1, wherein the received signal is frequency-converted into a first intermediate frequency by the oscillation signal of the sum frequency, and the first intermediate frequency signal is converted into a second intermediate frequency by a predetermined frequency signal. Receiver that converts frequency.