JPH08249266A - Data transfer circuit - Google Patents

Abstract

PURPOSE: To continuously perform the operation of plural data transfer channels, to prevent a free clock cycle from being generated in a transfer bus, and to speed up the data transfer. CONSTITUTION: A transfer channel for transferring data through a data bus 233 is set between I/O devices 213 and 214 and a memory 215. When a data transfer request nDRQ is issued from the I/O devices 213 and 214. it is received by request signal confirmation parts 221 and 222 and the channel for transferring the data is decided corresponding to priority predetermined in a priority confirmation part 223. Corresponding to the decided channel, transfer preparation parts 224 and 225 and transfer parts 226 and 227 are operated, addresses from address counters 229 and 231 are selected by an address selector 232 and the memory 215 is accessed through an address bus 234. The selected I/O devices 213 and 214 start the operation by confirmation smgnals nDAK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit having a plurality of data transfer channels and capable of high speed data transfer in response to a transfer request.

[0002]

2. Description of the Related Art Conventionally, computer systems have been
The function of direct memory access (hereinafter abbreviated as "DMA") that directly transfers data between an input / output device (Input Output Device, hereinafter abbreviated as "I / O device") and a memory is for high-speed data transfer. Is equipped with. High-speed data transfer between the I / O device and the memory is necessary for data transfer between the computer system and the external storage device, graphic image output, and the like. Generally, in the DMA, a central processing unit (hereinafter abbreviated as “CPU”) executes I / O by a program operation.
Higher-speed data transfer is possible than data transfer between the O device and the memory. Such a computer system is equipped with a DMA controller that controls the operation of the DMA. The I / O device transfers data while performing a handshake with an external device of the computer system. The basic operation procedure of the DMA controller is as follows.

(1) The CPU sets the address of the transfer source memory or I / O device in which the CPU wants to transfer data, the number of transfer data, the transfer destination memory or I / O address, the transfer method, etc. in the DMA controller. . By such setting, one data transfer channel is set between the I / O device and the memory.

(2) The CPU performs a normal program operation until a data transfer request is issued from the set data transfer channel. When a transfer request signal is generated from an I / O device belonging to the set data transfer channel, D
The MA controller makes a DMA request to the CPU. When the transfer preparation of the external device on the partner side is not completed, the transfer request signal from the I / O device is not generated.

(3) When a plurality of request signals are generated, the DMA controller prepares for data transfer to the highest priority data transfer channel according to a preset priority order.

(4) The CPU accepts the DMA request,
When the mastership of the data bus and the address bus over the memory and the I / O device is released, the DMA controller uses these buses as transfer buses to transfer data between the memory and the I / O device. Data transfer is performed while the transfer request signal continues. I / O requesting transfer
The device stops the transfer request signal when the required amount of data has been transferred, and the data transfer for that channel ends.

Of the basic data transfer procedure described above, the actual data transfer is performed in steps (3) and (4). Each of these procedures is executed for one clock cycle, and this transfer mode is called cycle steal. In a transfer mode generally called burst transfer, once a request signal is detected, data transfer for the set number of transfer data is continuously performed at once. For the second and subsequent data transfers, the process of (3) can be omitted and the process of transfer can be performed once. However, during the transfer, the transfer bus is completely occupied by one channel, and other devices such as the CPU stop in the state in which the mastership of the bus is released. When the CPU is stopped, acceptance of interrupt processing and the like is also stopped. In some interrupt processing, it is necessary to execute a certain amount of processing within a certain time after the request is generated. For example, this is a case where various timer operations are being performed. For this reason, the cycle steal transfer mode, which requires the procedure of (3) and (4) twice, is often used.

FIG. 6 shows the configuration of a data transfer circuit that operates according to the above-mentioned conventional technique. The transfer circuit 111 is
Data transfer processing is performed with the basic cycle of the clock signal CLOCK generated from the oscillator 112 as a unit cycle of the operation. A plurality of channels 0 and 1 for data transfer are set between the plurality of I / O devices 113 and 114 and the memory 115, respectively. In the transfer circuit 111, I / O
Data transfer request nDRQ from devices 113 and 114
Request signal confirming unit 12 for confirming presence / absence of 0, nDRQ1
1, 122, priority confirmation unit 123, transfer preparation unit 12
4, transfer unit 125, transfer counter 126 and address counter 12 for one I / O device 113
7. Transfer counter 1 for other I / O devices 114
28, an address counter 129, and an address selector 130. The data in each transfer channel is transferred via the data bus 131, and the address of the memory 115 involved in the data transfer is the address bus 132.
Specified via. Note that the leading "n" in the case of being written as "nDRQ0" indicates that the signal is true when it has a negative logic, that is, a logical value "0".

The operation of the circuit of FIG. 6 is as follows.

(1) I / O having a plurality of data transfer channels
After being set in relation to the devices 113 and 114, each I
Transfer request signal nD from the I / O devices 113 and 114.
With RQm = 0 (m = 0, 1), a data transfer request is generated to the transfer circuit 111.

(2) In the transfer circuit 111, when the request signal confirmation units 121 and 122 receive the transfer request signal nDRQm, the result is transmitted to the priority order confirmation unit 123. When a plurality of transfer requests are generated, the priority order confirmation unit 123 determines a data transfer channel according to a preset priority order.

(3) The determined data transfer channel is transmitted to the transfer preparation unit 124. The transfer preparation unit 124 gives a memory access request signal to the transfer unit 125, and responds to the determined data transfer channel by the address selector 13
Switch 0.

(4) The transfer unit 125 sets the response signal nDAKm = 0 to the I / O devices 113 and 114 of the determined data transfer channel and sets the address counters 127 and 129 corresponding to the determined data transfer channel.
From the address bus 13 via the address selector 130
2 causes the address signal to be derived. The address of the memory 115 designated by this address signal and the I / O device 1 selected by the data transfer response signal nDAKm = 0
13 and 114, the data transfer occupying the data bus 131 is performed by the clock signal CLO from the oscillator 112.
It is performed only for one cycle of CK.

(5) After the transfer is completed, the transfer counters 126 and 128 of the data transfer channel in which the data is transferred are set to 1
However, the address counters 127 and 129 change to the next address. Since the transfer data numbers are initially set in the transfer counters 126 and 128, when the count values become 0, a signal for stopping the reception of the transfer request is generated to the corresponding request signal confirmation units 121 and 122, The transfer for the data transfer channel is completed.

7 and 8 show the procedure of the transfer operation described above and the transfer timing which is performed in synchronization with the clock signal CLOCK. Step 10
When the power switch is turned on at 0 and the operation of the computer system is started, generation of the clock signal CLOCK by the oscillator 112 is also started. Transfer circuit 111
Allows data transfer after the data transfer channel is enabled in step 101. Step 102
Checks the presence / absence of a transfer request signal nDRQm from the I / O devices 113 and 114 included in the set data transfer channel, and if there is a transfer request signal, step 10
Move to 3. Steps 101 and 102 are carried out with the clock signal CLOCK = 1, ie half a clock period.

At step 103, the priority confirmation unit 12
The highest priority channel is confirmed by step 3, and step 1
In 04, the transfer preparation for the channel is made in the transfer preparation unit 1.
24. Steps 103 and 104
Are processed during one clock period.

At step 105, data transfer is performed by occupying the data bus 131. It is necessary to finish the access to the I / O devices 113 and 114 and the memory 115 within this time. When the period in which the clock signal CLOCK = 0, that is, one half of one clock period is associated with this time, the frequency of the clock signal COLOCK is determined.

In step 106, the transfer counter 126,
The remaining transfer data number is determined from the count value of 128,
If not 0, the process returns to step 101. If the number of remaining transfer data is 0, the data transfer channel is disabled in step 107 and the process returns to step 101. Steps 106 and 107 are clock signal CLOCK.
In the half of one clock cycle where = 1, steps 101 and 102 are executed simultaneously.

As shown in FIG. 8, the I / O device 11
The data transfer channels to which 3 and 114 are respectively related,
The transfer requests nDRQ0 and nDRQ1 may conflict with each other and be generated. Assuming that the channel 0 on the I / O device 113 side has a higher priority, the presence / absence of a transfer request signal is confirmed in step 102 of FIG. 7, and then the I / O device 113 side is selected as the highest priority channel in step 103. To be judged. In step 104, transfer preparation is performed, and in step 105, data transfer is performed. Higher priority I /
When the transfer channel on the O device 113 side requests data transfer twice, the I / O device 11
Data transfer is performed for the channels on the 4-side.

Prior arts relating to parallel processing involving data transfer include, for example, Japanese Patent Laid-Open No. 63-301351, Japanese Patent Publication No. 5-70867 (Japanese Patent Laid-Open No. 1-2232461), and Japanese Patent Laid-Open No. 4-195361. Etc. are also disclosed. Japanese Unexamined Patent Publication No. 63-301351 discloses a control method when a plurality of processors operate in parallel and perform data communication with each other. Japanese Patent Publication No. 5-70867 discloses a technique of allocating a plurality of processing requests among a plurality of processors constituting a multiprocessor system and performing parallel processing. Japanese Unexamined Patent Publication No. 4-195361 discloses a technique related to adjustment when data is transferred in burst mode between a plurality of input / output ports.

[0021]

As shown in FIG. 8, when data transfer step 104 and data transfer step 105 are sequentially repeated every clock cycle, one data transfer is performed. Therefore, the next data transfer is always performed after a time of one clock cycle. In recent years, in CPUs, RISC (Reduced Instrument
ction set computer), and enabled pipeline processing, and developed a high-speed CPU, high-speed accessible memory or I / O device that can process one data transfer in one clock cycle. There is. In a computer system including such a device, if a time of 2 clock cycles or more is required for each DMA transfer, high speed cannot be fully utilized.

When a request for a channel with a high priority, for example, channel 0 related to the I / O device 113 is continuously input, only the data transfer channel is transferred. For channels associated with other I / O devices 114, data bus 131 prepares for transfer step 10.
Despite being free at 4, we have to wait forever until the end of the channel 0 transfer.

If data transfer is performed in the burst mode, continuous data transfer is possible within the range of the condition set at the beginning without generating an empty cycle. However, once the transfer request is input and the transfer is started, even if the request is canceled next time, the transfer is performed once again. This is because the request signal confirmation and the transfer are executed at the same time, so that the transfer ends when the request signal confirmation is performed. Therefore, the transfer in the burst mode can be effectively used only when the number of transfer data is fixed or when transfer is performed with a partner having a buffer. In other cases, the extra transferred data cannot be received, and the operation may be wasted or cause a malfunction. This is the same even if data transfer and preparation of the next data are performed in parallel by pipeline processing.

JP-A-63-301351, JP-B-5-70867 or JP-A-4-195361.
Even in the prior art such as Japanese Patent Publication, no countermeasure is taken against the occurrence of an empty cycle in the transfer bus when performing sequential data transfer.

An object of the present invention is to perform, as a whole, alternating transfer preparation such as confirmation of a transfer request and data transfer occupying a transfer bus alternately for each of a plurality of data transfer channels. An object of the present invention is to provide a data transfer circuit capable of continuous data transfer without opening a transfer bus.

[0026]

The present invention provides a data transfer circuit having a plurality of data transfer channels for a common transfer bus in which a transfer clock defining a time required for data transfer is set. In each data transfer channel, as a data transfer process, a plurality of transfer clock cycles that are less than or equal to the number of data transfer channels are preset, and the transfer bus is occupied for one cycle of preparation and transfer clock necessary for data transfer. Configured for data transfer and
Data characterized by comprising arbitration means for causing data transfer processing to be performed in parallel by a plurality of data transfer channels having a transfer request, and switching a data transfer channel for occupying a transfer bus for data transfer according to a predetermined priority order. It is a transfer circuit. Further, the arbitration means of the present invention is switched so that after one data transfer channel occupies the transfer bus for one cycle of the transfer clock, another data transfer channel occupies the transfer bus for one cycle of the transfer clock. It is characterized by Also, the data transfer channel of the present invention is provided for a direct memory access operation of a computer system.

[0027]

According to the present invention, there are a plurality of data transfer channels for the common transfer bus, and data transfer is performed according to the time defined as the cycle of the transfer clock.
Each data transfer channel prepares for data transfer without occupying the transfer bus, and occupies the transfer bus for one cycle of the transfer clock to perform data transfer. The arbitration means causes the plurality of data transfer channels having transfer requests to perform data transfer processing in parallel, and switches the transfer channels occupying the transfer bus according to the priority order. Since the data transfer channels with high priority do not occupy the transfer bus when preparing for data transfer, it is possible for the data transfer channels with low priority to occupy the transfer bus, and the parallel data transfer processing as a whole can be performed. It can be done at high speed. Since each data transfer channel has a preparatory stage before data transfer, the required number of data transfers can be performed.

According to the invention, after one data transfer channel occupies the transfer bus for one cycle of the transfer clock, the other data transfer channels occupy the transfer bus for one cycle of the transfer clock. , The data transfer channels of higher priority do not continuously occupy the transfer bus, and the data of the data transfer channels of lower priority are transferred through the transfer bus during the preparation for transfer of the data transfer channels of higher priority. be able to.

Further, according to the present invention, since direct memory access of the computer system can be performed at high speed for a plurality of channels, the CPU and memory I / O
Even if the speed of the device is increased, a sufficiently high speed DMA operation can be performed.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an electrically equivalent structure of an embodiment of the present invention. The transfer circuit 211 is a DMA controller provided in the computer system, and a clock signal CLO regularly generated from an oscillator 212.
The DMA operation is performed in synchronization with CK. For example, the basic cycle of the clock signal CLOCK is set according to the access time of the memory or device, and the data transfer process is performed as fast as possible using this as a unit cycle of the operation. A plurality of channels 0, 1 for data transfer are provided for a plurality of I / O devices 2
13 and 214 and the memory 215, respectively.

In the transfer circuit 211, the I / O device 2
Data transfer request nDRQ0, nDR from 13, 214
Request signal confirmation unit 22 that receives Q1 and confirms the presence or absence of Q1
1, 222 are provided. Request signal confirmation unit 221, 22
The output from 2 is given to the priority confirmation unit 223.
The transfer preparation units 224 and 225 and the transfer units 226 and 227 are
It is provided corresponding to each of the channels 0 and 1. Further, a transfer counter 228 and an address counter 229 for channel 0, a transfer counter 230 and an address counter 231 for another channel 1, and an address selector 232 are included. Each transfer channel 0,
The data for transfer in 1 is transferred via the data bus 233, and the address of the memory 215 involved in the data transfer is designated via the address bus 234.

FIGS. 2 and 3 show the procedure of the transfer operation for each data transfer channel according to the embodiment of FIG. 1 and the transfer timing performed in synchronization with the clock signal CLOCK. The power switch is turned off in step 200.
When the N state is entered and the operation of the computer system is started, the generation of the clock signal CLOCK by the oscillator 212 is also started. The transfer circuit 211 can transfer data after the data transfer channel is set valid in step 201. In step 202, the I / O devices 213 and 214 included in the set data transfer channel are included.
Whether or not the transfer request signal nDRQm has been received is checked, and if the transfer request signal has been received, the process proceeds to step 203. Steps 201 and 202 are clock signal C
It is executed in the period of LOCK = 1, that is, in half of one clock cycle.

In step 203, the priority confirmation section 22
According to 3, it is confirmed whether or not there is a transfer request simultaneously from a data transfer channel having a higher priority. If there is a transfer request from a data transfer channel having a higher priority, the state of step 203 is repeated.
If there is no other high-priority transfer request, step 204
Then, transfer preparation for the data transfer channel is performed by the transfer preparation unit 224 or 225. In steps 203 and 204, the clock signal is CLOCK =
It is processed during one clock cycle where 0 and CLOCK = 1.

In step 205, data transfer is performed by occupying the data bus 233. This time is CLOCK
= 0, that is, half of one clock cycle, and it is necessary to finish the access to the I / O devices 213, 214 and the memory 215 within this time.

In step 206, the transfer counter 228,
The remaining transfer data number is determined from the count value of 230,
If not 0, the process returns to step 201. If the number of remaining transfer data is 0, the transfer of the data transfer channel is disabled in step 207, and then the process returns to step 201. In steps 206 and 207, the clock signal CL
In half of one clock cycle where OCK = 1, step 2
01 and 202 are executed in parallel at the same time.

As shown in FIG. 3, the I / O device 21
A plurality of data transfer channels to which 3 and 214 are respectively related may generate transfer requests nDRQ0 and nDRQ1 in competition with each other. Assuming that channel 0 on the I / O device 213 side has a higher priority, step 2 in FIG.
Even if they are handled in the same way until the presence or absence of the transfer request signal is confirmed in 02, it is determined in step 203 that the I / O device 213 side has a higher priority. In step 204, transfer preparation is performed, and in step 205, data transfer is performed. The transfer request from the I / O device 214 side is accepted, and immediately after the transfer from the I / O device 213 side, I
The transfer on the side of the / O device 214 is performed. Therefore I / O
When two data transfer requests from the device 213 side and one data transfer request from the I / O device 214 side are simultaneously input, the I / O device 213 side transfer, the I / O device 214 side transfer, and the I / O device 214 side transfer are performed. O device 213 side transfer,
Data transfer is performed alternately.

The operation of the transfer circuit 211 shown in FIG. 1 is as follows. Note that the two data transfer channels are associated with the I / O devices 213 and 214, respectively, and between these channels 0 and 1, the channel 0 side has a higher priority. Further, it is assumed that channel 0 requires data transfer twice, and channel 1 requires data transfer once.

(1) From each of the I / O devices 213 and 214, the transfer request signal is activated at nDRQm = 0 (m = 0, 1), and a data transfer request is issued to the transfer circuit 211.

(2) In the transfer circuit 211, when the request signal confirmation units 221 and 222 receive the transfer request signal nDRQm, the result is transmitted to the priority order confirmation unit 223. The priority confirmation unit 223 selects and determines channel 0 as a data transfer channel according to a preset priority.

(3) The transfer preparation section 224 associated with the determined channel 0 is given a transfer start instruction from the priority order confirmation section 223 and sends a memory access request signal to the transfer section 2.
26 and switches the address selector 232 so as to derive the address value from the address counter 229 on the channel 0 side to the address bus 234. Until the transfer on the channel 0 is completed, the priority order confirmation unit 223 does not give the transfer preparation unit 225 on the channel 1 side a start instruction indicating the start of transfer. The channel 1 side waits until there is a start instruction.

(4) The transfer unit 225 sends a response signal nDAK to the I / O device 213 on the same channel 0 side.
0 = 0 is set, and an address signal is derived from the address counter 229 via the address selector 232 to the address bus 234. Between the address of the memory 215 designated by this address signal and the I / O device 213 selected by the response signal nDAK0 = 0, the data bus 23
The data transfer occupying 3 is performed only for one cycle time of the clock signal CLOCK from the oscillator 212. The transfer counter 228 is decremented by 1, and the address counter 2
A predetermined calculation is applied to the value of 29.

Since the priority confirmation section 223 has completed the transfer preparation for channel 0, it selects another channel 1,
A start instruction is given to the transfer preparation unit 225. Transfer preparation unit 22
5 derives the memory access request signal and causes the value of the address counter 231 to be derived from the address selector 232 to the address bus 234. This allows the memory 215
Between the I / O device 214 and the I / O device 214, the data transfer occupying the data bus 233 is continuously performed on the channel 0. The transfer counter 230 becomes 0 when only 1 is subtracted, so that the request signal confirmation unit 222 can be instructed not to accept the request and the transfer process for the channel 1 can be ended.

(5) For channel 0, the second data transfer request nDRQ0 = 0 is generated from the I / O device 213. The request signal confirmation unit 221 and the priority confirmation unit 223 select the channel 0 again, and after the transfer is completed, the transfer counter 228 of the channel 0 is decremented by 1 and becomes 0 in the same manner as the above (3). As a result, the request signal confirmation unit 221 is also instructed not to accept the transfer request, and the transfer can be ended.

FIG. 4 and FIG. 5 respectively show a schematic configuration of a computer system including the transfer circuit 211 described above as a DMA controller, and DMA operation timings performed in synchronization with the clock signal CLOCK. The CPU 235 and the transfer circuit 211 can be a bus master for the data bus 233 and the address bus 234. Normally, the CPU 235 has control of the bus, and performs predetermined processing by a program operation. The transfer circuit 211 is also treated as one of the subordinate peripheral devices, and the transfer counters 228 and 23 are used for channel setting.
Necessary data is written in or read out from the internal registers such as 0 and the address counters 229 and 231. In the DMA operation, the transfer circuit 211 uses the I / O device 2
In response to the transfer request nDRQ0, 1 from the transfer request 13, DR, the bus request nBREQ is given to the CPU 235,
It is initiated by the 235 returning nBAK and going into an inactive state.

In the operation flow 300 of FIG. 5, the CPU 235
Performs normal operation, and the transfer circuit 211 outputs nDRQ0 = nD
RQ1 = 0 and transfer requests are received from both channels 0 and 1. In the operation flow 301, the CPU 235 continues the normal operation, and the transfer circuit 211 sets the bus request nBREQ = 0 in order to prepare for the transfer and prompts the CPU 235 to release the bus. In operation flow 302, the CPU 235 continues normal operation and changes from nBAK = 1 to nBAK = 0 to indicate that the bus is released in the clock cycle of the next cycle. The transfer circuit 211 outputs the transfer address DMA01 of channel 0 to the address bus 233 in preparation for transfer.

In operation flow 303, the CPU 235 hands over the mastership of the bus to the transfer circuit 211 to release the bus. The data D01 is transferred to the memory 2 as channel 0.
It is performed between the 15th address DMA01 and the I / O device 213. In the meantime, in preparation for the transfer of the next channel 1, the next transfer address DMA1 is stored in the address bus 233.
1 is output. In the operation flow 304, the CPU 235
Is releasing the bus, and the address DMA11 of the memory 215 is
The data D11 is transferred between the I / O device 214 and the I / O device 214. During this period, the next address DMA02 is prepared.

In operation flow 305, the CPU 235 is releasing the bus, and the data D02 of channel 0 is transferred. Since the transfer requests nDRQ0 and 1 are lost, nBRQ
Return to EQ = 1. In operation flow 306, the CPU 235 returns to normal operation and regains control of the bus. Transfer circuit 21
1 waits until a transfer request is input. CPU23
During the normal operation of 5, the address bus 234 has, for example, C
Output the values of PU1, CPU2, CPU3, CPU4,
Corresponding to this, data DC1, D on the data bus 233
Transfer of C2, DC3 and DC4 is performed.

Although the transfer circuit 211 is used as an independent DMA controller in the above embodiment, the CPU can be integrated on the same LSI chip as a core. In addition, DM of data bus and address bus
It can be used not only for arbitration with respect to A, but also for a multiprocessor system or an interface bus such as GPIB or SCSI.

Further, in the above-mentioned embodiment, the case where the number of data transfer channels is two is shown, but the case of three or more channels can be similarly implemented. However, when three or more transfer requests are input at the same time, and each request requires data transfer of two or more times, two data transfer channels with high priority occupy the bus, and other data transfer channels Is kept waiting until the upper transfer is completed. For applications in which such a situation is difficult, a circuit such as a round robin that automatically sets the priority of the channel to which transfer is performed to the lowest level is required.

[0050]

As described above, according to the present invention, a plurality of data transfer channels have a function of preparing transfer such as confirmation of a transfer request signal for each data transfer channel, and the transfer bus is provided with a transfer clock. The data is actually transferred by occupying each one cycle. By the arbitration means switching the data transfer channel that occupies the transfer bus, high-speed and sequential data transfer can be performed without leaving the transfer bus as a whole.

Further, according to the present invention, after occupying the transfer bus for one cycle of the transfer clock for one data transfer channel, if there is another data transfer channel requesting the transfer, that data transfer is performed. The channel can occupy the transfer bus for only one cycle of the transfer clock to transfer data. This effectively avoids situations where certain data transfer channels, such as high priority data transfer channels, continue to occupy the transfer bus and other data transfer channels cannot use the transfer bus for a long time. it can.

Further, according to the present invention, the direct memory access operation of the computer system can be performed at high speed for a plurality of channels as a whole. In particular, C
Even in a computer system capable of high-speed operation as a whole by using a RISC type processor for the PU,
It is possible to realize a DMA capable of operating at sufficiently high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an equivalent electrical configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

FIG. 3 is a time chart showing the operation timing of the embodiment of FIG.

4 is a block diagram showing an electrical configuration of a computer system including a transfer circuit according to the embodiment of FIG.

5 is a time chart showing the operation of the computer system of FIG.

FIG. 6 is a block diagram showing an electrical configuration of a conventional transfer circuit.

FIG. 7 is a flowchart showing the operation of the configuration of FIG.

FIG. 8 is a time chart showing the operation of the configuration of FIG.

[Explanation of symbols]

 211 transfer circuit 212 oscillator 213, 214 I / O device 215 memory 221 and 222 request signal confirmation unit 223 priority order confirmation unit 224 and 225 transfer preparation unit 226 and 227 transfer unit 228 and 230 transfer counter 229 and 231 address counter 232 address selector 233 Data bus 234 Address bus 235 CPU

Claims (3)

[Claims] 1. In a data transfer circuit having a plurality of data transfer channels for a common transfer bus in which a transfer clock defining a time required for data transfer is set, each data transfer channel is a data transfer channel. As a process, a configuration necessary to prepare for data transfer and to occupy the transfer bus for one cycle of the transfer clock and to perform the data transfer with a plurality of predetermined transfer clock cycles equal to or less than the number of data transfer channels A plurality of data transfer channels that have transfer requests are performed in parallel, and an arbitration unit that switches the data transfer channels that occupy the transfer bus and perform data transfer according to a predetermined priority is provided. Data transfer circuit. 2. The arbitration means is arranged such that, after one data transfer channel occupies the transfer bus for one cycle of the transfer clock, another data transfer channel occupies the transfer bus for one cycle of the transfer clock. The data transfer circuit according to claim 1, wherein the data transfer circuit is switched. 3. The data transfer circuit according to claim 1, wherein the data transfer channel is provided for a direct memory access operation of a computer system.