JPH0946216A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a semiconductor device with the smaller number of manufacture processes, to reduce cost, to realize high integration, to set leak current to be small and to obtain an appropriate output level. SOLUTION: The sources and the drains of pMOS transistors Q1 and Q2 are connected between a power supply source and ground in series. Positive logic or negative logic is applied on the gate of the pMOS transistor Q1 from an input (IN)-side, and logic obtained by inverting input (IN) is applied on the gate of the pMOS transistor Q2 from an inverse input (the inverse of IN)-side. The source and the drain of a pMOS transistor Q3 are interposed between the inverse input (the inverse of IN) and the gate of the pMOS transistor Q2. Then, a capacitor C1 is interposed between a space between the output- side of the pMOS transistor Q3 and the gate of the pMOS transistor Q2, and the connection part of the pMOS transistors Q1 and Q2. Thus, the output level from an output terminal part (OUT) is made appropriate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including MOS transistors of the same conductivity type.

[0002]

2. Description of the Related Art A conventional semiconductor device, for example, a thin film semiconductor device composed of a thin film transistor (TFT) is provided with an AND (logical product) circuit, a NAND
(Negative logical product) circuit, OR (logical sum) circuit, NOR
(Negative OR) circuit, EXOR (Exclusive OR) circuit, EXNOR (Negative Exclusive OR) circuit, or INV (Inverter: Negation) circuit and other logic circuits and various basic circuit elements Is possible. And
A device configured by combining these basic circuits includes, for example, an arithmetic device capable of performing all logical operations,
There is a liquid crystal driving device such as a liquid crystal display.

As described above, the conventional logic circuit using the semiconductor device and various basic circuit elements are usually pMOS.
A CMOS circuit in which a transistor and an nMOS transistor are combined is used. This CMOS circuit is
It is widely used because of its advantages such as low power consumption and proper output.

For example, FIG. 14 is a diagram showing a configuration of the CMOS inverter circuit 1. As shown in FIG.
The OS inverter circuit 1 uses two types of transistors, pMOS2 and nMOS3, as a pair. This CMO
In the S inverter circuit 1, when the IN (input) is “0”, the pMOS 2 is turned on and “1” is output from the power supply (Vdd).
(Output) When the input is "1", nMO
S3 is turned on and "0" is output from the ground. In this way, the CMOS inverter circuit 1 outputs an inverted version of the input.

Separately from this, pMOS or n
It is also possible to configure the inverter circuit using one of the MOS transistors. This inverter circuit includes a ratio type inverter circuit and a non-ratio type inverter circuit. Further, the ratio type inverter circuit includes a resistance load type, an E / E type, an E / D type and the like.

For example, FIG. 15 is a diagram showing the structure of the non-proportional inverter circuit 4, in which two pMOSs 5 are provided.
And pMOS6. This non-proportional inverter circuit 4 has the same conductivity type (here, p-type) MO
Since it is composed of S-transistors, the number of ion doping steps can be reduced as compared with the case of CMOS.

In the above-mentioned conventional example, an inverter circuit has been described as an example, but as another logic circuit, an AND
NAND circuit, OR / NOR circuit, EXOR / EXNO
CMOS and the like have been used also when configuring the R circuit and the like.

[0008]

However, in such a conventional semiconductor device, the CMO shown in FIG. 14 is used.
Since the S inverter circuit 1 is composed of two types of transistors, pMOS2 and nMOS3, it is necessary to make both pMOS and nMOS when manufacturing a CMOS inverter circuit, which increases the number of ion doping steps and the number of masks. However, there is a problem in that the manufacturing cost is increased because the number increases. Therefore, it is conceivable to use a ratioless inverter circuit that uses only one of the pMOS and nMOS transistors without using the CMOS.

However, this proportionless inverter circuit 4
As shown in FIG. 15, the gate of the PMOS5 is "0".
Is input, the PMOS 5 is turned on and the power supply outputs "1". Further, at this time, since "1" is input to the gate of the PMOS 6, the PMOS 6 is turned off and the current from the power supply does not flow to the ground side.

On the contrary, when "1" is input to the gate of the PMOS 5, the PMOS 5 is turned off, and "0" is input to the gate of the PMOS 6, so that the PMOS 6 is turned on and the ground potential is changed. "0" should be output. However, since the output "0" on the low side rises by the threshold voltage of the transistor, there is a problem that a sufficiently low potential such as the ground potential cannot be output.

Therefore, the present invention has been made in view of the above-mentioned problems, and by using transistors of the same conductivity type such as pMOS or nMOS, it can be formed by a small number of manufacturing steps and high integration can be achieved. It is an object of the present invention to provide a semiconductor device which is possible, has a small leak current, and can obtain an appropriate output level.

[0012]

According to another aspect of the present invention, there is provided a semiconductor device having first and second MOS transistors in which at least two sources or drains of MOS transistors of the same conductivity type are connected in series from a power source to a ground. And an input terminal for inputting a positive or negative gate signal to the gate of one of the MOS transistors, and an inverting input for inputting a gate signal of the opposite polarity to the input terminal to the gate of the other MOS transistor. The end and the first
An output end for outputting an output signal obtained by inverting the polarity of the input signal from the input end or the inverting input end from the connection between the MOS transistor and the second MOS transistor,
A semiconductor device comprising an inverter circuit including:
The above object is achieved by including a level correction circuit for correcting the output level output from the output end between at least one of the input end and the inverting input end of the inverter circuit and the gate.

Therefore, since the MOS transistors of the inverter circuit are of the same conductivity type and are composed of, for example, only pMOS transistors, an ion doping process for forming an inverter circuit on a substrate using a semiconductor process is performed. The number and the number of masks are smaller than in the case of CMOS transistors, and the manufacturing cost can be reduced. Of course, instead of the pMOS transistor,
It can also be configured with only nMOS transistors.

Further, since the inverter circuit is provided with the level correction circuit, a proper level can always be output from the output end of the inverter circuit. Therefore, even if a circuit incorporating this inverter circuit is constructed, malfunction or the like will occur. Can be obtained, and a highly reliable circuit can be obtained.

According to another aspect of the semiconductor device of the present invention, a logic circuit for executing a logical operation on a plurality of inputs by using a plurality of MOS transistors of the same conductivity type and a source or a drain of a MOS transistor of the same conductivity type as the logic circuit. Between at least two MOS transistors connected in series from the power supply to the ground, each gate of the two MOS transistors receives a logic output from the output section of the logic circuit, and between the two MOS transistors connected in series. An inverter circuit that outputs a logical operation result from the output end of the connection part, and an output level that is provided between the output part of the logic circuit and the gate of the inverter circuit and that is output from the output end of the inverter circuit. And a level correction circuit that corrects
By having the above, the above-mentioned object is achieved.

Therefore, the logic circuit for executing the logical operation is provided with an inverter circuit at its output stage to optimize the output level of the logic output, and a level correction circuit is provided at the gate portion of the inverter circuit to provide an inverter. By correcting the output level output from the circuit, an appropriate output level can be obtained. Therefore, even if a circuit that incorporates this logic circuit is configured, malfunction does not occur, and the circuit is highly reliable. be able to.

Further, since the MOS transistors constituting the above logic circuit are constituted by only pMOS transistors of the same conductivity type, for example, the number of ion doping steps and the number of masks can be reduced, and the manufacturing cost can be reduced. You can Of course, also in this case, instead of the pMOS transistor, only the nMOS transistor may be used.

According to another aspect of the logic circuit of the semiconductor device of the present invention,
You may make it include the logic circuit which performs a logical product. Therefore, in the logic circuit that executes the logical product, that is, in the AND circuit, the output level of the logical product is optimized by providing the inverter circuit in the output stage, and the level correction circuit is provided in the gate portion of the inverter circuit. By correcting the output level output from the inverter circuit, an appropriate output level of the logical product can be obtained. Therefore, even if a circuit incorporating this AND circuit is configured, malfunction does not occur and reliability is improved. Can be a high circuit.

According to another aspect of the logic circuit of the semiconductor device,
You may make it include the logic circuit which performs a logical sum. Therefore, in the logic circuit that executes the logical sum, that is, in the OR circuit, the output level of the logical sum is optimized by providing the inverter circuit at the output stage, and the level correction circuit is provided at the gate portion of the inverter circuit. By correcting the output level output from the inverter circuit,
Since an appropriate logical sum output level can be obtained, this O
Even if a circuit in which the R circuit is incorporated is configured, malfunction does not occur, and a highly reliable circuit can be obtained.

According to another aspect of the logic circuit of the semiconductor device of the present invention,
You may make it include the logic circuit which performs an exclusive OR. Therefore, in the logic circuit that executes the exclusive OR, that is, in the EXOR circuit, the output level of the exclusive OR is optimized by providing the inverter circuit in the output stage, and the level correction is performed on the gate portion of the inverter circuit. By providing a circuit and correcting the output level output from the inverter circuit, a proper exclusive OR output level can be obtained. Therefore, even if a circuit incorporating this EXOR circuit is configured, malfunction or the like may occur. It is possible to obtain a highly reliable circuit that does not generate.

In the semiconductor device according to any one of claims 1 to 5, for example, as described in claim 6, the level correction circuit includes a MOS transistor of the same conductivity type as the inverter circuit. A MOS transistor, which is composed of a capacitor and constitutes the level correction circuit, is connected between the gate and the input of at least one MOS transistor of the inverter circuit via a source and a drain to constitute the level correction circuit. Both ends of the capacitor are connected between the output side and the gate of the MOS transistor of the level correction circuit and the connection portion between the two MOS transistors connected in series in the inverter circuit, and the inverter circuit is connected. The fluctuation of the gate potential of the MOS transistor may be compensated.

Therefore, in the level correction circuit, the gate capacitance of the inverter circuit is increased by using the MOS transistor and the capacitor to form the inverter circuit.
An appropriate output level can be obtained from the inverter circuit by adopting the so-called bootstrap method that compensates for the variation of the gate potential of the S transistor.

Further, the level correction circuit uses, for example, a pMOS transistor of the same conductivity type as the logic circuit and the inverter circuit, and since all the MOS transistors can be unified to the same conductivity type, the ion doping is performed. The number of steps and the number of masks are reduced, and the manufacturing cost can be reduced. Of course, an nMOS transistor may be used instead of the pMOS transistor.

In the semiconductor device according to any one of claims 2 to 6, for example, as described in claim 7, two sets of the inverter circuit are provided for the logic circuit. Outputs from the two sets of inverter circuits are connected so that the connection positions to the gates of the MOS transistors of the two sets of inverter circuits are opposite to the two reverse polarity logic outputs output from the logic circuit. However, it may be configured to include the logical result of the logic circuit and its negation.

Therefore, each logic circuit is provided with an AND circuit, a NAND circuit, and an OR circuit only by adding one set of inverter circuits.
Circuit and NOR circuit, EXOR circuit and EXNOR circuit 2
It is possible to have two logic circuits together, and in that case as well, it is possible to configure with MOS transistors of the same conductivity type,
A proper output level can be obtained.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. 1 to 13
FIG. 4 is a diagram showing an embodiment of a semiconductor device of the present invention, in which only a pMOS transistor is used as a transistor of the same conductivity type used in the semiconductor device.

(First Embodiment) FIG. 1 is a diagram showing the configuration of a pMOS inverter circuit 11 according to the first embodiment, and FIG. 2 is a pMOS inverter circuit 11 of FIG.
FIG. 5 is a diagram showing symbols and their input / output signals. First,
The configuration will be described. PMOS inverter circuit 1 shown in FIG.
1 is composed of two inverter circuits 12 and 13.

The inverter circuit 12 connects the sources or drains of the pMOS transistors Q1 and Q2 in series from the power supply (Vdd) to the ground (GND),
Input end (IN) to the gate of pMOS transistor Q1
Input signal from the pMOS transistor Q2
It is connected so that the input signal from the inverting input terminal (-IN) is input to the gate of. The feature of the first embodiment is that a level correction circuit 14 is added to the gate side of the pMOS transistor Q2 to compensate the fluctuation of the gate potential and correct the output level.

Since the inverter circuit 12 is composed of only the pMOS transistor, the output level of the level correction circuit 14 is that of the transistor when the pMOS transistor Q2 is turned on to output the ground level "0". Since the voltage rises by the threshold voltage, a sufficiently low ground potential is output by correcting this. Specifically, as shown in FIG. 1, pM
The gate of the OS transistor Q2 and the inverting input terminal (| I
PMO with its gate grounded to N)
The bootstrap method is adopted in which the source and drain of the S-transistor Q3 are connected, and further, the capacitor C1 is connected between the output side of the pMOS transistor Q3 and the connecting portion of the pMOS transistors Q1 and Q2. ing.

As described above, the level correction circuit 14 has the pM
By using the OS transistor Q3 and the capacitor C1, the gate capacitance of the pMOS transistor Q2 is increased, and the gate potential for reliably turning on the pMOS transistor Q2 is held. However, the output level never rises and a sufficiently low ground potential can be output.

The inverter circuit 13 is composed of pMOS transistors Q4 and Q5 like the inverter circuit 12, and the level correction circuit 15 is composed of the pMOS transistor Q6 and the capacitor C2. The difference from the inverter circuit 12 is that the input end (I
N) and the inverting input end (-IN) are the inverter circuit 13
Are connected in reverse to the gates of the pMOS transistors Q4 and Q5. Therefore, the output of the inverter circuit 13 is the negative of the logic output from the inverter circuit 12. That is, the inverter circuit 12
The output end (OUT) of the inverter outputs an inverted signal of the signal input from the input end (IN), and the inverted output end (-OUT) of the inverter circuit 13 outputs the inverted input end. A signal obtained by inverting the polarity of the signal input from the section (IN) is output.

The pMOS inverter circuit 1 described with reference to FIG.
The symbol of 1 is as shown in FIG. 2, and its input end (I
N) the logical negation inputted from the output end (OUT) is output from the output end (OUT), and the logical negation inputted from the inverting input end (-IN) is output from the inverting output end (-OUT). .

Further, the pMOS according to the first embodiment
In the inverter circuit 11, the inverter circuits 12 and 13
Since the transistors used for the level correction circuits 14 and 15 are composed only of pMOS transistors, the number of ion doping steps and the number of masks are reduced when forming an inverter circuit on a substrate by using a semiconductor process. By simplifying, the manufacturing cost can be reduced.

The pMOS transistor used in this embodiment has, for example, a transistor size of L (channel length) = 4 μm, W (channel width) = 4 μm, a threshold voltage of −3 V, and a field effect mobility. 40 cm ² / V
S, gate electrode capacity 1.22 × 10 ^-14 F, S / D
A (source / drain) resistor having a resistance of 200Ω and a substrate voltage equal to the power source voltage (Vdd) is used. The capacitor used in the basic circuit has a capacitance of 0.2 pF.

The pMOS inverter circuit 1 described above is also used.
In No. 1, the pMOS transistor is used as the MOS transistor to be used, but the present invention is not limited to this.
Similar effects can be obtained even when the circuit is configured by using nMOS transistors instead of MOS transistors.

Next, the operation will be described. In the pMOS inverter circuit 11, for example, when a negative logic “0” is input to the input end (IN) and a positive logic “1” is input to the inverting input end (_IN), the pMOS inverter circuit 11 receives the pMOS
The transistor Q1 turns on, "1" is output (OUT) from the power supply Vdd, and the pMOS transistor Q2 turns off.

On the contrary, in the inverter circuit 13, the pMOS transistor Q4 is turned off and the pMOS transistor Q5 is turned on, and the ground level "0" is output as the inverted output (-OUT).

Further, the pMOS inverter circuit 11 is provided.
In, the input end (IN) and the inverting input end (-IN)
If the above logic is opposite to the above, "0" is output from the output end (OUT) side and "1" is output from the inverting output end (-OUT) side. As described above, in the pMOS inverter circuit 11 of the present embodiment, when both positive logic and negative logic are input as the input and the inverting input, the logic that negates them is output from the output end and the inverting output end. It

In the pMOS inverter circuit 11 of this embodiment, when the pMOS transistor Q2 of the inverter circuit 12 or the pMOS transistor Q5 of the inverter circuit 13 is turned on, the ground level is output as an output or an inverted output. At this time, in the present embodiment, as shown in FIG. 1, since the level correction circuits 14 and 15 are provided on the gate side of the pMOS transistors Q2 and Q5, when outputting a low level as an output or an inverted output, , It becomes possible to prevent the rise of the low level. Therefore, the pMOS inverter circuit 11 of the present embodiment can always output the proper Vdd level "1" and the ground level "0" from the output end or the inverting output end.

FIG. 2 is a symbolic representation of the pMOS inverter circuit 11 of FIG. 1 described above. A signal obtained by inverting the polarity of the signal input from the input terminal (IN) is output terminal (OUT). ), And a signal obtained by inverting the polarity of the signal input from the inverting input end (IN) is output from the inverting output end (-OUT).

(Second Embodiment) FIG. 3 is a diagram showing a configuration of an AND / NAND circuit 21 according to a second embodiment, and FIG. 4 is a symbol of the AND / NAND circuit 21 of FIG. It is a figure which shows and its input / output signal.

First, the configuration will be described. AND shown in FIG.
The NAND circuit 21 includes inverter circuits 22 and 23,
It is composed of level correction circuits 24 and 25 and a logic circuit 26.

The four pMOS transistors Q21 to Q24 forming the logic circuit 26 generate a logical product of the four inputs (a, ￣a, b, ￣b) and its negation using the pass transistor logic. To do. That is, when there are two inputs a and b, the inverse of that is the inverse a.
(_A) and inversion b (_b) are also input. Then, the pMOS transistors Q21 and Q22 are connected in series between the input end of a and the ground, and the pMOS transistor Q23 is connected between the input end of the inversion a and the power supply (Vdd). Q24 is connected in series. The gates of the pMOS transistors Q22 and Q24 are b
Is input to perform switching, and inversion b is input to the gates of the pMOS transistors Q21 and Q23 to perform switching. Then, according to the switching result of the above-mentioned four pMOS transistors, a signal of high level "1" or low level "0" is output from the connection portion of pMOS transistors Q21 and Q22 and the connection portion of pMOS transistors Q23 and Q24. Is output.

However, the logic circuit 26 is the above pMOS.
When only the transistors Q21 to Q24 are used, when the low level is output, the output level lost by the threshold voltage of the transistor is output. Therefore, in the AND / NAND circuit 21 of the present embodiment, the inverter circuits 22 and 23 are added to the output side of the logic circuit 26, and the output of the logic circuit 26 is applied to the gates of the inverter circuits 22 and 23. By switching the pMOS transistor, the power supply potential (Vdd) or the ground potential (GN
D) is output.

However, the above inverter circuits 22 and 23
Is composed of pMOS transistors only,
When the pMOS transistors Q27, 30 shown in FIG. 3 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 24, 2 are further added.
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The specific configuration of the level correction circuit 24 in the second embodiment is that between one output from the logic circuit 26 and the gate of the pMOS transistor Q27,
The source and drain of a pMOS transistor Q25 whose gate is grounded are connected to each other, and the output side of the pMOS transistor Q25 and the pMO transistor
The bootstrap method in which the capacitor C21 is connected between the S transistors Q26 and Q27 is adopted.

In this way, the level correction circuit 24 has the pM
The addition of the OS transistor Q25 and the capacitor C21 increases the gate capacitance of the pMOS transistor Q27 and holds the gate potential necessary for turning on the pMOS transistor Q27 with certainty. The output level does not increase by the value voltage, and the output can be corrected to a sufficiently low ground potential before output.

The level correction circuit 25, like the level correction circuit 24, uses the pMOS transistor Q28 and the capacitor C22 to increase the gate capacitance of the pMOS transistor Q30 and surely turn on the pMOS transistor Q30. Since the gate potential required for this is maintained, the output level does not rise by the threshold voltage, and the output can be corrected to a sufficiently low ground potential before output.

AND / NAND constructed as described above
The circuit 21 has a logical product (AND) from the inverter circuit 22 and a logical product (AND) from the inverter circuit 23 with respect to four inputs (a, ￣a, b, ￣b).
Is output. AND / NAND circuit 2 described in FIG.
The symbol of 1 is as shown in FIG. 4, and the AND output and the NAND output are output to the a input end and the b input end thereof.

Further, AND / NAN according to the present embodiment
The D circuit 21 uses inverters 22 and 23, level correction circuits 24 and 25 thereof, and transistors used in a logic circuit 26 including pass transistor logic as pMO.
Since only S transistors are used, the number of ion doping steps and the number of masks are reduced when the AND / NAND circuit is formed on the substrate using the semiconductor process, and the manufacturing process is simplified, thereby reducing the manufacturing cost. can do. In the AND / NAND circuit 21, a pMOS transistor is used to form the circuit, but an nMOS transistor may be used instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), the pMOS transistors Q21 and Q23 are turned off as shown in FIG. Then, since Q22 and Q24 are turned on, the pMOS transistors Q26 and Q30 of the inverter circuits 22 and 23 are turned off, but the pMOS transistors Q27 and Q29 are turned on and the AND output is "0" and the NAND output is "1". Become.

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the AND output is "0", The NAND output becomes "1". Also, the input a is "1" (the inverted a is "0").
When b is “0” (inversion b is “1”), the AND output is “0” and the NAND output is “1”.

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The AND output becomes "1" and the NAND output becomes "0". In this way, the AND / NAND circuit 21 of the present embodiment
Is output from the inverter circuits 22 and 23, respectively, as a logical product and a negative logical product with respect to the inputs of a and b.

Then, the AND / NAND of the present embodiment
The circuit 21 outputs the ground level as an AND output or a NAND output when the pMOS transistor Q27 or Q30 of the inverter circuits 22 and 23 is turned on. At this time, in the present embodiment, as shown in FIG. 3, since the level correction circuits 24 and 25 are provided on the gate side of the pMOS transistors Q27 and Q30, a low level is output as an AND output or a NAND output. Moreover, the rise of the low level can be prevented. Therefore, the AND / NAND circuit 21 according to the present embodiment can always output the appropriate Vdd level “1” and the ground level “0” as the AND output or the NAND output.

The AND / NA explained in FIG.
The ND circuit 21 is written as a symbol as shown in FIG. 4, and AND / NAND is applied to two inputs (a, b).
The logical product (AND) and the negative of the logical product (NAND) are output from the output side of the circuit 21.

(Third Embodiment) FIG. 5 is a diagram showing a configuration of an OR / NOR circuit 31 according to a third embodiment, and FIG. 6 is a symbol of the OR / NOR circuit 31 of FIG. It is a figure which shows and its input / output signal.

First, the structure will be described. OR shown in FIG.
The NOR circuit 31 is composed of inverter circuits 32 and 33, level correction circuits 34 and 35, and a logic circuit 36.

The four pMOS transistors Q31 to Q34 forming the logic circuit 36 generate a logical sum of the four inputs (a, ￣a, b, ￣b) and its negation using the pass transistor logic. To do. That is, when there are two inputs a and b, the inverse of that is the inverse a.
(_A) and inversion b (_b) are also input. Then, pMOS transistors Q31 and Q32 are connected in series between the input end of the inversion a and the ground, and a pMOS transistor Q33 is connected between the input end of a and the power supply (Vdd). Q34 is connected in series. Inversion b is input to the gates of the pMOS transistors Q32 and Q34 to perform switching, and
B is input to the gates of the transistors Q31 and Q33 to perform switching. And the above four MOS
Depending on the switching result of the transistor, pMOS
Connection between transistors Q31 and Q32 and pMOS
A high level "1" or low level "0" signal is output from the connection between the transistors Q33 and Q34.

However, the logic circuit 36 is the pMOS described above.
If only the transistors Q31 to Q34 are used, when the low level is output, the output level lost by the threshold voltage of the transistor is output. Therefore, in the OR / NOR circuit 31 of the present embodiment, the inverter circuits 32 and 33 are added to the output side of the logic circuit 36, and the logic circuit 3
By applying the output of No. 6 to the gates of the inverter circuits 32 and 33 and switching each pMOS transistor, the power supply potential (Vdd) or the ground potential (GN).
D) is output.

However, the above inverter circuits 32, 33
Is composed of pMOS transistors only,
When the pMOS transistors Q37 and 40 shown in FIG. 5 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 34, 3
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The concrete configuration of the level correction circuit 34 in the third embodiment is that a pMOS transistor whose gate is grounded is provided between one output from the logic circuit 36 and the gate of the pMOS transistor Q37. Q
35 is connected to the source and drain of the pMOS transistor Q35.
The bootstrap method in which the capacitor C31 is connected between the transistor Q36 and the connection portion between the transistors Q37 is adopted.

Therefore, in the level correction circuit 34, pMO
By using the S transistor Q35 and the capacitor C31, the gate capacitance of the pMOS transistor Q37 is increased and the gate potential for reliably turning on the pMOS transistor Q37 is held, so that the output level is equal to the threshold voltage. It is possible to correct and output the level to a sufficiently low ground potential.

In the level correction circuit 35, the gate capacitance of the pMOS transistor Q40 is increased to hold the gate potential for reliably turning on the pMOS transistor Q40, similarly to the level correction circuit 34, so that the output level is increased. It is possible to correct and output an appropriate level.

The OR / NOR circuit 31 configured as described above has four inputs (a, ￣a, b, ￣b),
The inverter circuit 32 outputs a logical sum (OR), and the inverter circuit 33 outputs a negative logical sum (NOR). The symbol of the OR / NOR circuit 31 described with reference to FIG. 5 is as shown in FIG. 6, and the OR output and NOR output are output to the a input end and the b input end of the symbol.

Further, in the OR / NOR circuit 31 according to the present embodiment, the transistors used in the inverter circuits 32 and 33, their level correction circuits 34 and 35, and the logic circuit 36 composed of pass transistor logic are pMOS transistors. Since it is configured only, when the inverter circuit is formed on the substrate using the semiconductor process, the number of ion doping processes and the number of masks are reduced, and the manufacturing process is simplified, so that the manufacturing cost can be reduced. . Although the OR / NOR circuit 31 is configured by using the pMOS transistor, it may be configured by using the nMOS transistor instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), the pMOS transistors Q32 and Q34 are turned off as shown in FIG. Then, since Q31 and Q33 are turned on, the pMOS transistors Q36 and Q40 of the inverter circuits 32 and 33 are turned off, but the pMOS transistors Q37 and Q39 are turned on and the OR output is "0",
The NOR output becomes "1".

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the OR output is "1", The NOR output becomes "0".
In addition, the input a is “1” (inversion a is “0”), and b
Is "0" (inversion b is "1"), the OR output is "1" and the NOR output is "0".

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The OR output becomes "1" and the NOR output becomes "0". As described above, the OR / NOR circuit 31 according to the present embodiment has a, b
Is output from the OR output end, and negative logical sums that negate it are output from the NOR output end, respectively.

The OR / NOR circuit 31 of the present embodiment outputs the ground level as an OR output or a NOR output when the pMOS transistor Q37 or Q40 of the inverter circuits 32 and 33 is turned on.
At this time, in the present embodiment, as shown in FIG. 5, the level correction circuits 34 and 35 cause the pMOS transistor Q3 to operate.
Since it is provided on the gate side of 7 and Q40, OR
When the low level is output as the output or NOR output, the rise of the low level can be prevented. Therefore,
The OR / NOR circuit 31 according to the present embodiment can always output a proper Vdd level “1” and a ground level “0” as an OR output or a NOR output.

Then, the OR / NOR explained in FIG.
When the circuit 31 is written with a symbol, it becomes as shown in FIG.
For the two inputs (a, b), the OR / NOR circuit 31
OR from the output side of the and the negation of the OR (N
OR) is output.

(Fourth Embodiment) FIG. 7 is a diagram showing a configuration of an EXOR / EXNOR circuit 41 according to a fourth embodiment, and FIG. 8 is a symbol of the EXOR / EXNOR circuit 41 of FIG. It is a figure which shows and its input / output signal.

First, the structure will be described. EXO shown in FIG.
The R / EXNOR circuit 41 includes inverter circuits 42 and 43.
And level correction circuits 44 and 45, and a logic circuit 46. 4 pMOSs forming the logic circuit 46
Transistors Q41-Q44 are pass transistors
Exclusive OR (EXOR) and its negation (EXNO) for four inputs (a, ￣a, b, ￣b) using logic.
R) and are generated. That is, the input is a, b
In the case of two, the inversion a (￣a) and the inversion b which are the negation.
(￣b) is also entered.

The input of the inverted b is input to the level correction circuit 44 of the next stage via the pMOS transistor Q41, and the input of b is the pMOS transistor Q42.
Is input to the level correction circuit 45 of the next stage via the
It is connected to the output side of the pMOS transistor Q42 via the OS transistor Q43, and from the input side of the pMOS transistor Q42 to the pMOS transistor Q42.
It is connected to the output side of the pMOS transistor Q41 via 44.

The above pMOS transistors Q41 and Q4
An inversion a is input to the gate of 2 to perform switching, and an a is input to the gates of the pMOS transistors Q43 and Q44 to perform switching, thereby forming an exclusive OR logic circuit 46. . Then, a high level "1" or a low level "0" signal is output to the level correction circuits 44 and 45 according to the switching result of the MOS transistor.

However, the logic circuit 46 is the pMOS described above.
If only the transistors Q41 to Q44 are used, when a low level is output, an output level lost by the threshold voltage of the transistor is output. Therefore, in the EXOR / EXNOR circuit 41 of the present embodiment, the inverter circuits 42 and 43 are added to the output side of the logic circuit 46,
The output of the logic circuit 46 is applied to the gates of the inverter circuits 42 and 43, and each pMOS transistor is switched to output the power supply potential (Vdd) or the ground potential (GND).

However, the above inverter circuits 32 and 33
Is composed of pMOS transistors only,
When the pMOS transistors Q47 and Q50 of FIG. 7 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 44, 4 are further added.
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The concrete configuration of the level correction circuit 44 in the fourth embodiment is that a pMOS transistor whose gate is grounded is provided between one output from the logic circuit 46 and the gate of the pMOS transistor Q47. Q
45 is connected to the source and drain thereof, and the output side of the pMOS transistor Q45 is connected to the pMOS transistor Q45.
The bootstrap method in which the capacitor C41 is connected between the transistor Q46 and the connection portion between the transistors Q47 is adopted.

Therefore, in the level correction circuit 44, pMO
By using the S transistor Q45 and the capacitor C41, the gate capacitance of the pMOS transistor Q47 is increased and the gate potential for reliably turning on the pMOS transistor Q47 is held, so that the output level is equal to the threshold voltage. It is possible to correct and output the level to a sufficiently low ground potential.

Further, in the level correction circuit 45, the gate capacitance of the pMOS transistor Q50 is increased and the gate potential for reliably turning on the pMOS transistor Q50 is held, as in the level correction circuit 44, so that the output level is increased. It is possible to correct and output an appropriate level.

EXOR / EXN constructed as described above
The OR circuit 41 outputs an exclusive OR (EX) from the inverter circuit 42 to the four inputs (a, ￣a, b, ￣b).
OR) is output from the inverter circuit 43 as a negative exclusive OR (EXNOR).

The symbols of the EXOR / EXNOR circuit 41 described with reference to FIG. 7 are as shown in FIG.
An EXOR output and an EXNOR output are output to the input end. Further, the EXOR / EX according to the present embodiment
The NOR circuit 41 uses p-type transistors for the inverter circuits 42 and 43, their level correction circuits 44 and 45, and a logic circuit 46 including pass transistor logic.
Since only MOS transistors are used, when forming an inverter circuit on a substrate using a semiconductor process, the number of ion doping processes and the number of masks are reduced, and the manufacturing process is simplified, thereby reducing the manufacturing cost. You can

The EXOR / EXNOR circuit 41 is used.
In the above, the circuit is configured using the pMOS transistor, but an nMOS transistor may be used instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), as shown in FIG. 7, the pMOS transistors Q41 and Q42 are turned off. Then, since Q43 and Q44 are turned on, the pMOS transistors Q36 and Q40 of the inverter circuits 42 and 43 are turned off, but the pMOS transistors Q47 and Q49 are turned on and the EXOR output is "0" and the EXNOR output is "1". Become.

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the EXOR output is "1", EXNOR output is "0"
Becomes When the input a is “1” (inversion a is “0”) and b is “0” (inversion b is “1”),
The EXOR output becomes "1" and the EXNOR output becomes "0".

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The EXOR output becomes "0" and the EXNOR output becomes "1". In this way, the EXOR / EXNOR of the present embodiment is
In the circuit 41, the exclusive OR for inputs a and b is EX.
It is output from the OR output end, and a negative exclusive OR that negates it is output from the EXNOR output end.

In addition, the EXOR / EXNO of the present embodiment
The R circuit 41 is a pMO of the inverter circuits 42 and 43.
S transistor Q47 or pMOS transistor Q
When 50 is turned on, the ground level is output as an OR output or a NOR output. At this time, in the present embodiment, as shown in FIG. 5, since the level correction circuits 44 and 45 are provided on the gate sides of the pMOS transistors Q47 and Q50, the EXOR output and EXNO output are obtained.
When the low level is output as the R output, the rise of the low level can be prevented. Therefore, the EXOR / EXNOR circuit 41 of the present embodiment always keeps the proper Vdd.
EXO the level "1" and the ground level "0"
It is output as R output or EXNOR output.

Then, the EXOR and EXN of FIG.
The OR circuit 41 is represented by a symbol as shown in FIG. 8. EXOR.EXN is given to two inputs (a, b).
The OR circuit 41 outputs an exclusive OR (EXOR) and a negation (EXNOR) of the exclusive OR.

As described above, in the first to fourth embodiments, the configurations of the four types of basic logic circuits in which the level correction circuit is added to the inverter circuit and the negation circuit thereof have been described. By combining these logic circuits, all 16 pool algebras can be calculated.

In the circuit configuration described in the above embodiment in which the level correction circuit is added to the inverter circuit, a basic circuit other than the logic circuit, for example, a latch circuit or a tri-state circuit can be configured. Therefore, in the following fifth embodiment, a configuration example of the latch circuit will be
In the sixth embodiment, a configuration example of the tri-state circuit will be described.

(Fifth Embodiment) FIG. 9 is a diagram showing a configuration of a latch circuit 51 according to a fifth embodiment. First, the configuration will be described. The latch circuit 51 shown in FIG. 9 is different from the configuration of the pMOS inverter circuit 11 according to the first embodiment described in FIG. 1 in that it has an input signal control unit 56 that controls an input signal from the input side and an output. And a feedback signal control section 57 for feeding back an output signal from the input side to the input side.

Therefore, the pMOS inverter circuit 1 of FIG.
As shown in FIG. 9, the structure of the part corresponding to 1 is pM
Q1 → Q56, Q2 → Q57, Q
3 → Q55, Q4 → Q59, Q5 → Q60, Q6 → Q5
8 respectively, in the capacitor C1 → C51, C
2 → C52, which corresponds to 2 sets of inverter circuits 5
2, 53 and their level correction circuits 54, 55 are configured.

Then, the two sets of inverter circuits 52,
An input signal control unit 56 for controlling an input signal is provided between each gate of the pMOS transistor constituting 53 and the input end (I) and the inverting input end (_I). The input signal control unit 56 is composed of pMOS transistors Q51 and Q52 which are switching elements, and the inverted clock signal (_clk) for switching is applied to the gates of the pMOS transistors Q51 and Q52. It is input from the input end (-L).

A feedback signal control unit 57 is provided between the output side and the input side of the inverter circuits 52 and 53, and is composed of a feedback loop and pMOS transistors Q53 and Q54.

That is, the output (--OUT) from the output terminal (--O) of the inverter circuit 52 is connected to the drain side of the pMOS transistor Q52 described above by a feedback loop through the pMOS transistor Q54 which is a switching element. , The inverter circuit 5
The output (OUT) from the output end (O) of 3 is the pMOS transistor Q described above by the feedback loop.
PMOS, which is a switching element, on the drain side of 51
It is connected through the transistor Q53.

Then, the above-mentioned pMOS transistor Q
A clock signal (clk) for controlling switching is applied to the control signal input terminal (L) at the gates of 53 and Q54.
It is configured to be input from. As described above, the latch circuit 51 shown in FIG. 9 is obtained by newly adding four pMOS transistors Q51 to Q54 to the inverter circuit shown in FIG. And the pMOS transistor Q
51 to Q54 are input terminals for the inversion control signal from the outside (-
L) and the control signal from the control signal input terminal (L) are used to switch between the through operation and the latch operation of the latch circuit 51.

Next, the operation will be described. In the latch circuit 51 shown in FIG. 9, the clock signal (clk) input to the control signal input end (L) is high “1”, and the inverted clock signal (_clk) at the inverted control signal input end (_L). ) Is low “0”, the clock signal (clk) input to the control signal input end (L) is low “0” and the inverted control signal input end (−L). When the inverted clock signal (_clk) of)) is high “1”, the latch state is set.

The above-mentioned through state means the input end (I).
The input signal (IN) from is output as it is as the output signal (OUT) of the output end (O), and the inverting input end (
Inverted input signal (-IN) from I) is output as it is as the inverted output signal (-OUT) of the inverted output end (-O). Further, the above-mentioned latched state means holding the output state before latching.

Specifically, as shown in FIG. 9, the clock signal (clk) is high "1", and the inverted clock signal (-
When clk) is low “0”, it is in the through state and p
The MOS transistors Q53 and Q54 are turned off, and the pMOS
The transistors Q51 and Q52 are turned on.

Therefore, the input signal (IN) is "0",
When the inverted input signal (_IN) is "1", the pMOS transistors Q57 and Q59 are turned off, and the pMOS transistors Q56 and Q60 are turned on, so that the through state is output as it is and "0" is output to the output signal (OUT). "But,
"1" is output to the inverted output signal (_OUT).

Next, the clock signal (clk) is low "0" and the inverted clock signal (-clk) is high "1".
In the case of, the pMOS transistor Q53 and Q54 of FIG. 9 are turned on and the pMOS transistor Q53 is turned on.
51 and Q52 are turned off. Therefore, "0" of the output signal (OUT) in the immediately preceding through state is pM regardless of the input signals of the input end (I) and the inverting input end (-I).
The pMOS transistors Q56 and Q60 are turned on via the OS transistor Q53, and the inverted output signal (--OU
"1" in T) is transmitted through the pMOS transistor Q54,
Since the pMOS transistors Q57 and Q59 are turned off, the previous output state is maintained, the output signal (IN) is "0", and the inverted input signal (-IN) "1" is output as it is.

As described above, the latch circuit shown in FIG.
The gates of the individual pMOS transistors Q51 to Q54 are switched between the through operation and the latch operation according to a control signal from the outside.

Further, the latch circuit 51 of the above-mentioned embodiment.
Is the p of the inverter circuits 52 and 53, as shown in FIG.
In the gate portions of the MOS transistors Q57 and Q60, p
MOS transistors Q55, Q58 and capacitor C5
Since the level correction circuits 54 and 55 including C1 and C52 are provided respectively, output level loss is eliminated, and direct current leakage current is eliminated, so that power consumption can be reduced.

Furthermore, the latch circuit 51 of the above-mentioned embodiment.
Are all p-type MOS transistors of the same conductivity type.
Since it is composed of MOS transistors, the number of ion doping steps and the number of masks can be reduced when forming on a substrate using a semiconductor process as compared with a circuit using a conventional CMOS, so that the manufacturing cost can be reduced.

In the latch circuit 51, the pMOS
Although the circuit is composed of transistors, the present invention is not limited to this, and an nMOS transistor may be used instead of the pMOS transistor.

(Sixth Embodiment) FIG. 10 is a diagram showing a configuration example of a tri-state circuit 61 for generating an alternating voltage. The tri-state circuit 61 is used, for example, when an alternating drive voltage is generated because the liquid crystal is deteriorated when a direct current voltage is applied to the liquid crystal when the liquid crystal drive device or the like drives the liquid crystal.

First, the structure will be described. As shown in FIG. 10, the pMOS transistors Q61 to Q68 include a logic circuit 66 that generates a predetermined logic based on four input signals of d, inversion d (-d), WF, and inversion WF (-WF). I am configuring. Then, the tri-state circuit 61 is
By inputting positive logic and negative logic to d and WF respectively, an alternating voltage generated by switching three kinds of power source voltages VH, VC and VL is output from the output D (provided that VH> VC > VL). Here, the pass transistor logic method is used as in the above-described embodiment.

Then, for example, when the tri-state circuit 61 is used in a liquid crystal driving device, d of the input signal is used.
Can be used to indicate whether or not write data is present, that is, whether or not the liquid crystal is driven, and WF indicates whether the liquid crystal drive voltage is positive or negative.

Next, inverter circuits 62 and 63 are formed on the output side of the logic circuit 66. For example, the inverter circuit 62 is connected from the power source (Vdd) to the ground (G
PMOS transistors Q71 and Q7
0 source or drain is connected in series,
The output from the logic circuit 66 is the pMOS transistor Q7.
1 and Q70 are input to the gate. In the present embodiment, a pMOS transistor Q69 whose gate is grounded is connected between the gate of the pMOS transistor Q70 of the inverter circuit 62 and a predetermined output end of the logic circuit 66, and the pMOS transistor Q6 is connected to the pMOS transistor Q6.
9 output side and the pMOS transistors Q71 and Q70
A level correction circuit 64 is configured by connecting a capacitor C61 between the connection part of the and.

Further, the inverter circuit 63 is similar to the above-described inverter circuit 62 in that the pMOS transistor Q7 is used.
4 and Q73, and a level correction circuit 65
Is composed of a pMOS transistor Q72 and a capacitor C62. In this way, the inverter circuits 62, 6
Since the gates of the pMOS transistors of No. 3 are provided with the level correction circuits 64 and 65, the gate capacitance of the pMOS transistors Q70 or Q73 is increased to perform switching reliably, and an appropriate low level "L" is obtained. A signal can be output.

Then, the tri-state circuit 61 according to the present embodiment applies the output signals from the above-mentioned inverter circuits 62 and 63 to the gates of the pMOS transistors Q75 and Q76, respectively, thereby switching the high-potential power supply. The voltage VH or the low-potential power supply voltage VL is selectively output from the output terminal D, and the intermediate-potential power supply voltage VC is supplied to the pMOS transistor Q77.
Are switched by the d input and output.

In the present embodiment, in addition to the above configuration, a capacitor C63 is further connected between the gate of the pMOS transistor Q75 and the ground, and
It is connected between the gate of the pMOS transistor Q76 and the ground via a capacitor C64. Therefore, since the gate capacitances of the pMOS transistors Q75 and Q76 connected to the power supply voltage of the high potential (VH) and the low potential (VL) increase, the pMOS transistor Q7
5 and Q76 can be surely switched, and the power supply voltages VH and VL at appropriate levels without voltage rise or voltage drop are output.

As described above, in the tri-state circuit 61 of this embodiment, the output level of the logic circuit 66 is optimized by providing the inverter circuits 62 and 63 on the output side of the logic circuit 66. In particular, the inverter circuit 62,
When 63 is composed of a pMOS transistor,
By providing the level correction circuits 64 and 65 including the pMOS transistor Q69 or Q72 and the capacitor C61 or C62 on the side of the ground side pMOS transistor Q70 or Q73, the output level is increased by the threshold voltage of the pMOS transistor. Can be prevented. Further, the tri-state circuit 61 according to the present embodiment switches the pMOS transistors Q75 and Q76 in which the outputs of the inverter circuits 62 and 63 are connected to the high potential (VH) and low potential (VL) power supply voltages. For selective output, capacitors C63 and C64 are provided on the gate side to increase the gate capacitance and output power supply voltages VH and VL at appropriate levels.

Next, the operation will be described. The tri-state circuit 61 shown in FIG. 10 inputs D to WF by inputting either positive logic or negative logic to each of d and WF.
Any one of H, VC and VL is selectively output. Actually, by changing the inputs d and WF, VH and V
An alternating signal composed of C and VL is generated.

First, when the input signals d and WF are "0", the pMOS transistors Q75 and Q76 are turned off and the pMOS transistor Q77 is turned on, so that the intermediate potential (VC) is output from D. In addition, d of the input signal
Is 0 and WF is 1, the intermediate potential (VC) is output from D similarly to the above. This is because when d is "0", the pMOS transistor Q61 of the logic circuit 66,
Since Q63, Q65, and Q67 are turned off, the pMOS transistor Q77 is turned on without being influenced by the input signal of WF, and Vc is output from D.

When the input signal d is "1", the switching transistor Q77 is turned off and the logic circuit 6
6 pMOS transistors Q62, Q64, Q66, Q
68 is turned off, and conversely, pMOS transistors Q61, Q63, Q65, Q67 are turned on. Therefore, the output voltage from D changes based on the input signal of WF.

Therefore, when WF is "0", pMOS
Since transistor Q76 turns on and Q75 turns off,
A low potential (VL) is output from D. When WF is "1", the pMOS transistor Q75 is turned on and Q76 is turned off, so that the high potential (VH) is output from D.

As described above, the tri-state circuit 61 of the present embodiment can be composed of only the pMOS transistor and the capacitor, so that the structure is simple and can be manufactured in a small number of steps, so that the cost can be reduced.

Further, the tri-state circuit 61 of the above-described embodiment uses the inverter circuits 62 and 63 and the level correction circuits 64 and 65 to change the output level of the logic circuit 66 constituted by the pMOS transistors Q61 to Q68. In addition to the correction, the capacitors C63 and C64 are provided to surely switch the pMOS transistors Q75 and Q76, so that the power supply voltage V of an appropriate level is obtained.
It is possible to selectively output H and VL. In particular, pM
In the case of the OS transistor, it is possible to solve the problem that the low-level output voltage VL does not fall sufficiently, and it is possible to always output the voltage level in which it surely drops to a predetermined potential. I can do it now.

In the tristate circuit 61,
The circuit was constructed using pMOS transistors.
An nMOS transistor may be used instead of the MOS transistor.

(Seventh Embodiment) FIG. 11 shows a TFT-LCD integrated with a drive circuit to which the semiconductor device of the present invention is applied.
It is a schematic block diagram of 71. This drive circuit integrated TFT-
The LCD 71 forms a TFT (Thin Film Transistor) serving as a switching element for each pixel on a glass substrate in a display area of an LCD (Liquid Crystal Display), and also forms a drain driver (data line driving circuit) and a gate driver (scanning). A liquid crystal drive circuit including a line drive circuit) is integrally formed on a glass substrate.

First, the structure will be described. As shown in FIG. 11, the drive circuit integrated TFT-LCD 71 includes a liquid crystal display panel (TFT-LCD) 73 in which a TFT is formed for each pixel in a display area on a glass substrate 72, and the liquid crystal display panel 73. A gate driver 74 that applies a scanning signal to the gate of each TFT to create a selected state and a non-selected state;
The TFT selected by the gate driver 74
And a drain driver 75 for driving a liquid crystal for each pixel by applying a display signal to the pixel.

The liquid crystal display panel 73, the gate driver 74, and the drain driver 75 described above are provided on the glass substrate 7.
2 is integrally formed. FIG. 12 is a partial circuit diagram in which the drain driver 75 shown in FIG. 11 is configured by the latch circuit having a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit, an AND / NAND circuit, and a tri-state circuit. is there. .

The drain driver 75 shown in FIG. 12 includes latch circuits 81, 82, 83 ..., AND / NAND circuits 91, 92 ..., Latch circuits 101, 102 ..., Latch circuits 111, 112 ,. State circuit 12
1, 122 ... And so on.

The latch circuits 81, 82 and 83 are connected to a horizontal synchronizing signal (XSC
L) and the inverted horizontal synchronizing signal (-XSCL) are 1 at the control signal input end (L) and the inverted control signal input end (-L).
Every other time, the signals are input in the opposite phase, and when "1" is entered in the control signal input end (L), the input signal is output through.
When "0" is entered, the previous input signal is latched.

As the input signal to the latch circuit 81, the XD clock and the inverted XD clock are input, and the output signal corresponding to the through state and the latch state is output from the output end (O) and the inverted output end (-O). And is input to the input ends of the AND / NAND circuit 91 and the latch circuit 82 at the next stage. Similarly, the output signal of the latch circuit 82 is input to the AND / NAND circuits 91 and 92 and the input end of the latch circuit 83 of the next stage.

Then, the AND / NAND circuit 91 inputs the output (OUT) of the latch circuit 81 and the inverted output (-OUT) of the latch circuit 82 to control the logical product and its negation of the latch circuit 101. Input to the signal input end (L) and the inverted control signal input end (-L). AND NA
Similarly, the ND circuit 92 also outputs the inverted output (−) of the latch circuit 82.
OUT) and the output (OUT) of the latch circuit 83 are input, and the logical product and the negation thereof are input to the control signal input end (L) and the inverted control signal input end (-L) of the latch circuit 102. It

The latch circuit 101 and the latch circuit 102 are
In accordance with the timing of the output signals from the AND / NAND circuits 91 and 92, the data for each pixel input from a data conversion circuit (not shown) is latched, and the latched data is respectively transferred to the latch circuit 111 of the next stage. 112
Output to The latch circuits 111 and 112 use the clock O
The data for each pixel input at the timing of P is latched, and the output is latched in each tri-state circuit 121.
And 122.

The tri-state circuits 121 and 122 combine the input signals from the above-mentioned latch circuits 111 and 112 with the AC signal WF to produce VH, VC and V.
By appropriately selecting the three types of power source voltages of L 3, an alternating display signal is generated. The alternating display signal output from the tri-state circuit 121 is
The alternating display signal output to the drain line D1 and output from the tri-state circuit 122 is output to the drain line D2.

Note that FIG. 12 only illustrates a part of the configuration of the drain driver 75 which supplies the drain lines for two lines. In practice, the above circuits are connected in the horizontal scanning direction according to the number of pixels. Are arranged. This allows
A display signal corresponding to the position of each drain line can be supplied.

As described above, the latch circuit, ANDN
Since the drain driver 75 composed of an AND circuit and a tri-state circuit can be composed of only a pMOS transistor and a capacitor, the conventional CMOS
Compared to the case of using transistors, the transistor structure is simpler and the number of manufacturing steps is reduced. If a pMOS transistor is also used for the pixel TFT transistor, a drive circuit integrated type is formed on the same plane of the glass substrate. TFT-LCD can be created at the same time,
There is an advantage that the cost can be reduced.

Further, the drain driver 75 according to the present embodiment has a small DC leak current, low power consumption, and an appropriate output level, especially a low level, as in the case of being composed of CMOS transistors. There is an advantage that the output can be suppressed to a sufficiently low level.

Next, FIG. 13 shows a gate driver 74 shown in FIG. 11, which is a latch circuit having a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit.
FIG. 7 is a partial circuit diagram formed of a NOR circuit and an inverter circuit. The gate driver 74 shown in FIG. 13 includes latch circuits 131, 132, 133, 134, ..., NOR circuits 141, 142, 143, 144, ..., Inverter circuits 151, 152, 153, 154, ..., Inverter circuits 161, 162. , 163, 164, ..., Inverter circuits 171, 172, 173, 174 ,.

Latch circuits 131, 132, 133, 13
4 ... is a vertical sync signal (YSCL) input from a controller (not shown) and an inverted vertical sync signal (YSCL).
L) is input to the control signal input end (L) and the inverted control signal input end (-L) every other phase in reverse phase, and "1" is input to the control signal input end (L). And the input signal is output through, and when "0" is input, the previous input signal is latched.

The YD clock is input as an input signal to the latch circuit 131, an output signal corresponding to the through state and the latch state is output from the output end (O) and the inverted output end (_O), and the NOR circuit is input. 141 and the input terminal of the latch circuit 132 at the next stage. Similarly, the output signal of the latch circuit 132 is input to the input ends of the NOR circuit 141, the NOR circuit 142, and the latch circuit 133 at the next stage.

The NOR circuit 141 is supplied with the output (OUT) of the latch circuit 131 and the inverted output (-OUT) of the latch circuit 132, and a negative logical sum is continuously given to the inverter circuits 151 to 161, 171. Is input and a gate signal is output to the gate line G1. By the same operation as described above, each inverter circuit 172, 17
Gate lines G2, G from the output ends of 3, 174
Gate signals are sequentially output to 3 and G4.

Note that FIG. 13 merely illustrates a part of the configuration of the gate driver 74 which supplies the gate lines for two lines, and the above-mentioned circuits are arranged according to the number of lines arranged in the vertical direction. Has been done. As a result, each gate line is line-scanned by a predetermined scanning method to bring each gate line into a selected state or a non-selected state.

As described above, the gate driver 74 composed of the latch circuit, the NOR circuit and the inverter circuit.
Can be composed of only a pMOS transistor and a capacitor as in the case of the drain driver 75, so that the transistor structure is simpler and the number of manufacturing steps is reduced as compared with the case of the conventional CMOS transistor. be able to. In particular, if a pMOS transistor is adopted as the TFT transistor of the pixel, the driving circuit integrated TFT-LCD can be formed on the same plane of the glass substrate, so that the cost can be reduced. Further, the gate driver 74 of the present embodiment has the advantages of low power consumption similar to that of CMOS and capable of suppressing an appropriate output level, particularly a low level output to a sufficiently low level.

As described above, four kinds of basic logic circuits are constructed by using MOS transistors (pMOS, nMOS) of the same conductivity type and capacitors, and by combining these, all kinds of logical operations are possible. Can be configured, and these circuits can be manufactured at low cost. Further, since the level correction circuit is always added, even if the MOS transistors of the same conductivity type are used, the output level does not decrease and an appropriate output level can be obtained.

Of course, not only a logic circuit is formed by using the MOS transistors (pMOS, nMOS) of the same conductivity type and a capacitor as described above, but a basic circuit such as a latch circuit or a tri-state circuit is constructed and used in combination. Thereby, the same effect as the above can be obtained.

[0140]

According to the semiconductor device of the first aspect, since the MOS transistors of the inverter circuit are of the same conductivity type, the number of ion doping steps and the mask when forming the inverter circuit on the substrate by using the semiconductor process. The number is
Compared with the case of the conventional CMOS transistor, the number is reduced, and the manufacturing cost can be reduced. Further, since the inverter circuit includes the level correction circuit, it is possible to always output an appropriate level from the output end of the inverter circuit.

According to the semiconductor device of claims 2 to 5,
An inverter circuit is provided at the output stage of each of the AND circuit, the OR circuit, and the EXOR circuit to optimize the output level of the logic output, and a level correction circuit is provided at the gate portion of the inverter circuit to output the output level from the inverter circuit. An appropriate output level can be obtained by correcting. Moreover, since the MOS transistors forming the AND circuit, the OR circuit, and the EXOR circuit are configured to have only the same conductivity type, the number of ion doping steps and the number of masks can be reduced, and the manufacturing cost can be reduced.

According to the semiconductor device described in claim 6, the level correction circuit of the semiconductor device described in any one of claims 1 to 5 comprises a MOS transistor and a capacitor to increase the gate capacitance of the inverter circuit. An appropriate output level can be obtained from the inverter circuit by adopting the so-called bootstrap method, which compensates for the variation of the gate potential of the MOS transistor that constitutes the inverter circuit. Further, since the level correction circuit uses the MOS transistor of the same conductivity type as the logic circuit and the inverter circuit, the number of ion doping steps and the number of masks are reduced, and the manufacturing cost can be reduced.

A semiconductor device according to a seventh aspect is the semiconductor device according to the second aspect.
The inverter circuit according to claim 6 has two logic circuits.
A pair of inverter circuits are provided for each of the MO of the two inverter circuits with respect to two logic outputs of opposite polarities output from the logic circuit.
Since the S transistors are connected so that their connection positions to the gate are opposite to each other, the outputs from the two sets of inverter circuits can output the logical result of the logic circuit and its negation. Of course, also in that case, the MOS transistors of the same conductivity type can be used and an appropriate output level can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a pMOS inverter circuit according to a first embodiment.

FIG. 2 is a diagram showing a symbol of the pMOS inverter circuit of FIG. 1 and its input / output signals.

FIG. 3 is a diagram showing a configuration of an AND / NAND circuit according to a second embodiment.

FIG. 4 is a diagram showing symbols of the AND / NAND circuit of FIG. 3 and its input / output signals.

FIG. 5 is a diagram showing a configuration of an OR / NOR circuit according to a third embodiment.

6 is a diagram showing symbols of the OR / NOR circuit of FIG. 5 and its input / output signals.

FIG. 7 shows EXOR / EXNOR according to a fourth embodiment.
The figure which shows the structure of a circuit.

8 is a diagram showing symbols of the EXOR / EXNOR circuit of FIG. 7 and input / output signals thereof.

FIG. 9 is a diagram showing a configuration of a latch circuit according to a fifth embodiment.

FIG. 10 is a diagram showing a configuration example of a tri-state circuit that generates an alternating voltage.

FIG. 11 is a schematic configuration diagram of a TFT-LCD integrated with a drive circuit to which the semiconductor device of the present invention is applied.

FIG. 12 is a circuit diagram showing an AND / NAND circuit in which the drain driver shown in FIG. 11 is provided with a logic circuit composed of pMOS transistors, an inverter circuit and a level correction circuit
The partial circuit diagram comprised by the circuit and the tri-state circuit.

13 is a partial circuit diagram in which the gate driver shown in FIG. 11 is configured by a latch circuit including a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit, a NOR circuit, and an inverter circuit.

FIG. 14 is a diagram showing a configuration of a CMOS inverter circuit.

FIG. 15 is a diagram showing a configuration of a ratioless inverter circuit.

[Explanation of symbols]

 11 pMOS inverter circuit 12, 13 inverter circuit 14, 15 level correction circuit 21 AND / NAND circuit 22, 23 inverter circuit 24, 25 level correction circuit 26 logic circuit 31 OR / NOR circuit 32, 33 inverter circuit 34, 35 level correction circuit 36 logic circuit 41 EXOR / EXNOR circuit 42, 43 inverter circuit 44, 45 level correction circuit 46 logic circuit

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[Procedure amendment]

[Submission date] April 5, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Semiconductor device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having the same conductivity type thin film transistor.

[0002]

2. Description of the Related Art A conventional semiconductor device, for example, a thin film semiconductor device composed of a thin film transistor (TFT) is provided with an AND (logical product) circuit, a NAND
(Negative logical product) circuit, OR (logical sum) circuit, NOR
(Negative OR) circuit, EXOR (Exclusive OR) circuit, EXNOR (Negative Exclusive OR) circuit, or INV (Inverter: Negation) circuit and other logic circuits and various basic circuit elements Is possible. And
A device configured by combining these basic circuits includes, for example, an arithmetic device capable of performing all logical operations,
There is a liquid crystal driving device such as a liquid crystal display.

As described above, the conventional logic circuit using the semiconductor device and various basic circuit elements are usually pMOS.
A CMOS circuit in which a transistor and an nMOS transistor are combined is used. This CMOS circuit is
It is widely used because of its advantages such as low power consumption and proper output.

For example, FIG. 14 is a diagram showing a configuration of the CMOS inverter circuit 1. As shown in FIG.
The OS inverter circuit 1 uses two types of transistors, pMOS2 and nMOS3, as a pair. This CMO
In the S inverter circuit 1, when the IN (input) is “0”, the pMOS 2 is turned on and “1” is output from the power supply (Vdd).
(Output) When the input is "1", nMO
S3 is turned on and "0" is output from the ground. In this way, the CMOS inverter circuit 1 outputs an inverted version of the input.

Separately from this, pMOS or n
It is also possible to configure the inverter circuit using one of the MOS transistors. This inverter circuit includes a ratio type inverter circuit and a non-ratio type inverter circuit. Further, the ratio type inverter circuit includes a resistance load type, an E / E type, an E / D type and the like.

For example, FIG. 15 is a diagram showing the structure of the non-proportional inverter circuit 4, in which two pMOSs 5 are provided.
And pMOS6. This non-proportional inverter circuit 4 has the same conductivity type (here, p-type) MO
Since it is composed of S-transistors, the number of ion doping steps can be reduced as compared with the case of CMOS.

In the above-mentioned conventional example, an inverter circuit has been described as an example, but as another logic circuit, an AND
NAND circuit, OR / NOR circuit, EXOR / EXNO
CMOS and the like have been used also when configuring the R circuit and the like.

[0008]

However, in such a conventional semiconductor device, the CMO shown in FIG. 14 is used.
Since the S inverter circuit 1 is composed of two types of transistors, pMOS2 and nMOS3, it is necessary to make both pMOS and nMOS when manufacturing a CMOS inverter circuit, which increases the number of ion doping steps and the number of masks. However, there is a problem in that the manufacturing cost is increased because the number increases. Therefore, it is conceivable to use a ratioless inverter circuit that uses only one of the pMOS and nMOS transistors without using the CMOS.

However, this proportionless inverter circuit 4
As shown in FIG. 15, the gate of the PMOS5 is "0".
Is input, the PMOS 5 is turned on and the power supply outputs "1". Further, at this time, since "1" is input to the gate of the PMOS 6, the PMOS 6 is turned off and the current from the power supply does not flow to the ground side.

On the contrary, when "1" is input to the gate of the PMOS 5, the PMOS 5 is turned off, and "0" is input to the gate of the PMOS 6, so that the PMOS 6 is turned on and the ground potential is changed. "0" should be output. However, since the output "0" on the low side rises by the threshold voltage of the transistor, there is a problem that a sufficiently low potential such as the ground potential cannot be output.

Therefore, the present invention has been made in view of the above-mentioned problems, and by using transistors of the same conductivity type such as pMOS or nMOS, it can be formed by a small number of manufacturing steps and high integration can be achieved. It is an object of the present invention to provide a semiconductor device which is possible, has a small leak current, and can obtain an appropriate output level.

[0012]

The semiconductor device of claim 1, wherein Means for Solving the Problems] at least towards the source or drain of the thin film transistors of the same conductivity type from the power supply to the ground 2
First and second thin film transistors connected to the individual series, an input end for inputting a positive or negative polarity gate signal to the gate of the one of the thin film transistor, the other
An inverting input end for inputting a gate signal of opposite polarity to the input end to the gates of the thin film transistor, the input end from the connecting portion of the first thin film <br/> transistor and a second thin film transistor or A semiconductor device comprising an inverter circuit including an output terminal that outputs an output signal that is obtained by inverting the polarity of an input signal from the inverting input terminal, wherein the input terminal and the inverting input terminal of the inverter circuit are The above object is achieved by providing a level correction circuit for correcting the output level output from the output end between at least one of the gate and the gate.

Accordingly, since the thin film transistors of the inverter circuit are of the same conductivity type and are composed of, for example, only pMOS transistors, the inverter circuit is formed on the substrate by using a semiconductor process. In this case, the number of ion doping steps and the number of masks are smaller than in the case of a CMOS transistor, and the manufacturing cost can be reduced. Of course, instead of the pMOS transistor, n
It is also possible to use only MOS transistors.

Further, since the inverter circuit is provided with the level correction circuit, a proper level can always be output from the output end of the inverter circuit. Therefore, even if a circuit incorporating this inverter circuit is constructed, malfunction or the like will occur. Can be obtained, and a highly reliable circuit can be obtained.

The semiconductor device according to claim 2 includes a logic circuit for performing a logical operation on a plurality of input using a plurality of thin film transistors of the same conductivity type, the source or drain of the thin film transistor of the same conductivity type as said logic circuit from the power supply toward the ground and connected to at least two series, the logic output from the output section of the logic circuit to the gates of the two thin film transistors are respectively input, between two thin film transistors connected in series An inverter circuit that outputs a logical operation result from the output end of the connection part, and an output level that is provided between the output part of the logic circuit and the gate of the inverter circuit and that is output from the output end of the inverter circuit. The above-mentioned object is achieved by including a level correction circuit that corrects.

Therefore, the logic circuit for executing the logical operation is provided with an inverter circuit at its output stage to optimize the output level of the logic output, and a level correction circuit is provided at the gate portion of the inverter circuit to provide an inverter. By correcting the output level output from the circuit, an appropriate output level can be obtained. Therefore, even if a circuit that incorporates this logic circuit is configured, malfunction does not occur, and the circuit is highly reliable. be able to.

Further, since the thin film transistor constituting the above logic circuit is constituted by only pMOS transistors of the same conductivity type, for example, the number of ion doping steps and the number of masks can be reduced, and the manufacturing process can be improved. The cost can be reduced. Of course, also in this case, instead of the pMOS transistor, only the nMOS transistor may be used.

According to another aspect of the logic circuit of the semiconductor device of the present invention,
You may make it include the logic circuit which performs a logical product. Therefore, in the logic circuit that executes the logical product, that is, in the AND circuit, the output level of the logical product is optimized by providing the inverter circuit in the output stage, and the level correction circuit is provided in the gate portion of the inverter circuit. By correcting the output level output from the inverter circuit, an appropriate output level of the logical product can be obtained. Therefore, even if a circuit incorporating this AND circuit is configured, malfunction does not occur and reliability is improved. Can be a high circuit.

According to another aspect of the logic circuit of the semiconductor device,
You may make it include the logic circuit which performs a logical sum. Therefore, in the logic circuit that executes the logical sum, that is, in the OR circuit, the output level of the logical sum is optimized by providing the inverter circuit at the output stage, and the level correction circuit is provided at the gate portion of the inverter circuit. By correcting the output level output from the inverter circuit,
Since an appropriate logical sum output level can be obtained, this O
Even if a circuit in which the R circuit is incorporated is configured, malfunction does not occur, and a highly reliable circuit can be obtained.

According to another aspect of the logic circuit of the semiconductor device of the present invention,
You may make it include the logic circuit which performs an exclusive OR. Therefore, in the logic circuit that executes the exclusive OR, that is, in the EXOR circuit, the output level of the exclusive OR is optimized by providing the inverter circuit in the output stage, and the level correction is performed on the gate portion of the inverter circuit. By providing a circuit and correcting the output level output from the inverter circuit, a proper exclusive OR output level can be obtained. Therefore, even if a circuit incorporating this EXOR circuit is configured, malfunction or the like may occur. It is possible to obtain a highly reliable circuit that does not generate.

[0021] The semiconductor device according to any one of claims 1 to 5, for example, as described in claim 6, wherein the level correction circuit includes a thin film transistor of the same conductivity type as the inverter circuit Composed of a capacitor,
Thin film transistors constituting the level correction circuit, which is connected via the source and drain between the gate of at least one of the thin film transistor of the inverter circuit and the input, both ends of the capacitor constituting the level correction circuit, level and between the output side and the gate of the thin film transistor of the correction circuit, connected in series with the inverter circuit 2
Is connected between the connection between the pieces of the thin film transistor,
It may be compensated for variations in the gate potential of the thin film transistor of the inverter circuit.

[0022] Thus, the level correction circuit, the gate capacitance of the inverter circuit is increased by using the thin film transistor and a capacitor, to compensate for variations in the gate potential of the thin film bets <br/> transistor constituting the inverter circuit, So-called,
By adopting the bootstrap method, an appropriate output level can be obtained from the inverter circuit.

Further, the level correction circuit uses, for example, a pMOS transistor of the same conductivity type as the logic circuit and the inverter circuit, and since all the MOS transistors can be unified to the same conductivity type, the ion doping is performed. The number of steps and the number of masks are reduced, and the manufacturing cost can be reduced. Of course, an nMOS transistor may be used instead of the pMOS transistor.

In the semiconductor device according to any one of claims 2 to 6, for example, as described in claim 7, two sets of the inverter circuit are provided for the logic circuit. The two sets of inverter circuits are connected so that the connection positions to the gates of the thin film transistors of the two sets of inverter circuits are exactly opposite to the two sets of the two sets of reverse polarity logic outputs. The output from the inverter circuit may be the logical result of the logic circuit and its negation.

Therefore, each logic circuit is provided with an AND circuit, a NAND circuit, and an OR circuit only by adding one set of inverter circuits.
Circuit and NOR circuit, EXOR circuit and EXNOR circuit 2
One of the can have combined logic circuit, even in which case, it is possible to a thin film transistor of the same conductivity type, it is possible to obtain an appropriate output level.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. 1 to 13
FIG. 3 is a diagram showing an embodiment of a semiconductor device of the present invention, in which only a pMOS transistor is used as a thin film transistor of the same conductivity type used in the semiconductor device.

(First Embodiment) FIG. 1 is a diagram showing the configuration of a pMOS inverter circuit 11 according to the first embodiment, and FIG. 2 is a pMOS inverter circuit 11 of FIG.
FIG. 5 is a diagram showing symbols and their input / output signals. First,
The configuration will be described. PMOS inverter circuit 1 shown in FIG.
1 is composed of two inverter circuits 12 and 13.

The inverter circuit 12 connects the sources or drains of the pMOS transistors Q1 and Q2 in series from the power supply (Vdd) to the ground (GND),
Input end (IN) to the gate of pMOS transistor Q1
Input signal from the pMOS transistor Q2
It is connected so that the input signal from the inverting input terminal (-IN) is input to the gate of. The feature of the first embodiment is that a level correction circuit 14 is added to the gate side of the pMOS transistor Q2 to compensate the fluctuation of the gate potential and correct the output level.

Since the inverter circuit 12 is composed of only the pMOS transistor, the output level of the level correction circuit 14 is that of the transistor when the pMOS transistor Q2 is turned on to output the ground level "0". Since the voltage rises by the threshold voltage, a sufficiently low ground potential is output by correcting this. Specifically, as shown in FIG. 1, pM
The gate of the OS transistor Q2 and the inverting input terminal (| I
PMO with its gate grounded to N)
The bootstrap method is adopted in which the source and drain of the S-transistor Q3 are connected, and further, the capacitor C1 is connected between the output side of the pMOS transistor Q3 and the connecting portion of the pMOS transistors Q1 and Q2. ing.

As described above, the level correction circuit 14 has the pM
By using the OS transistor Q3 and the capacitor C1, the gate capacitance of the pMOS transistor Q2 is increased, and the gate potential for reliably turning on the pMOS transistor Q2 is held. However, the output level never rises and a sufficiently low ground potential can be output.

The inverter circuit 13 is composed of pMOS transistors Q4 and Q5 like the inverter circuit 12, and the level correction circuit 15 is composed of the pMOS transistor Q6 and the capacitor C2. The difference from the inverter circuit 12 is that the input end (I
N) and the inverting input end (-IN) are the inverter circuit 13
Are connected in reverse to the gates of the pMOS transistors Q4 and Q5. Therefore, the output of the inverter circuit 13 is the negative of the logic output from the inverter circuit 12. That is, the inverter circuit 12
The output end (OUT) of the inverter outputs an inverted signal of the signal input from the input end (IN), and the inverted output end (-OUT) of the inverter circuit 13 outputs the inverted input end. A signal obtained by inverting the polarity of the signal input from the section (IN) is output.

The pMOS inverter circuit 1 described with reference to FIG.
The symbol of 1 is as shown in FIG. 2, and its input end (I
N) the logical negation inputted from the output end (OUT) is output from the output end (OUT), and the logical negation inputted from the inverting input end (-IN) is output from the inverting output end (-OUT). .

Further, the pMOS according to the first embodiment
In the inverter circuit 11, the inverter circuits 12 and 13
Since the transistors used for the level correction circuits 14 and 15 are composed only of pMOS transistors, a plurality of thin film transistors are formed on the substrate using a semiconductor process.
When forming an inverter circuit according to the present invention, the number of ion doping steps and the number of masks are reduced, and the manufacturing process is simplified, so that the manufacturing cost can be reduced.

The pMOS transistor used in this embodiment has, for example, a transistor size of L (channel length) = 4 μm, W (channel width) = 4 μm, a threshold voltage of −3 V, and a field effect mobility. 40 cm ² / V
S, gate electrode capacity 1.22 × 10 ^-14 F, S / D
A (source / drain) resistor having a resistance of 200Ω and a substrate voltage equal to the power source voltage (Vdd) is used. The capacitor used in the basic circuit has a capacitance of 0.2 pF.

The pMOS inverter circuit 1 described above is also used.
In No. 1, the pMOS transistor is used as the MOS transistor to be used, but the present invention is not limited to this.
Similar effects can be obtained even when the circuit is configured by using nMOS transistors instead of MOS transistors.

Next, the operation will be described. In the pMOS inverter circuit 11, for example, when a negative logic “0” is input to the input end (IN) and a positive logic “1” is input to the inverting input end (_IN), the pMOS inverter circuit 11 receives the pMOS
The transistor Q1 turns on, "1" is output (OUT) from the power supply Vdd, and the pMOS transistor Q2 turns off.

On the contrary, in the inverter circuit 13, the pMOS transistor Q4 is turned off and the pMOS transistor Q5 is turned on, and the ground level "0" is output as the inverted output (-OUT).

Further, the pMOS inverter circuit 11 is provided.
In, the input end (IN) and the inverting input end (-IN)
If the above logic is opposite to the above, "0" is output from the output end (OUT) side and "1" is output from the inverting output end (-OUT) side. As described above, in the pMOS inverter circuit 11 of the present embodiment, when both positive logic and negative logic are input as the input and the inverting input, the logic that negates them is output from the output end and the inverting output end. It

In the pMOS inverter circuit 11 of this embodiment, when the pMOS transistor Q2 of the inverter circuit 12 or the pMOS transistor Q5 of the inverter circuit 13 is turned on, the ground level is output as an output or an inverted output. At this time, in the present embodiment, as shown in FIG. 1, since the level correction circuits 14 and 15 are provided on the gate side of the pMOS transistors Q2 and Q5, when outputting a low level as an output or an inverted output, , It becomes possible to prevent the rise of the low level. Therefore, the pMOS inverter circuit 11 of the present embodiment can always output the proper Vdd level "1" and the ground level "0" from the output end or the inverting output end.

FIG. 2 is a symbolic representation of the pMOS inverter circuit 11 of FIG. 1 described above. A signal obtained by inverting the polarity of the signal input from the input terminal (IN) is output terminal (OUT). ), And a signal obtained by inverting the polarity of the signal input from the inverting input end (IN) is output from the inverting output end (-OUT).

(Second Embodiment) FIG. 3 is a diagram showing a configuration of an AND / NAND circuit 21 according to a second embodiment, and FIG. 4 is a symbol of the AND / NAND circuit 21 of FIG. It is a figure which shows and its input / output signal.

First, the configuration will be described. AND shown in FIG.
The NAND circuit 21 includes inverter circuits 22 and 23,
It is composed of level correction circuits 24 and 25 and a logic circuit 26.

The four pMOS transistors Q21 to Q24 forming the logic circuit 26 generate a logical product of the four inputs (a, ￣a, b, ￣b) and its negation using the pass transistor logic. To do. That is, when there are two inputs a and b, the inverse of that is the inverse a.
(_A) and inversion b (_b) are also input. Then, the pMOS transistors Q21 and Q22 are connected in series between the input end of a and the ground, and the pMOS transistor Q23 is connected between the input end of the inversion a and the power supply (Vdd). Q24 is connected in series. The gates of the pMOS transistors Q22 and Q24 are b
Is input to perform switching, and inversion b is input to the gates of the pMOS transistors Q21 and Q23 to perform switching. Then, according to the switching result of the above-mentioned four pMOS transistors, a signal of high level "1" or low level "0" is output from the connection portion of pMOS transistors Q21 and Q22 and the connection portion of pMOS transistors Q23 and Q24. Is output.

However, the logic circuit 26 is the above pMOS.
When only the transistors Q21 to Q24 are used, when the low level is output, the output level lost by the threshold voltage of the transistor is output. Therefore, in the AND / NAND circuit 21 of the present embodiment, the inverter circuits 22 and 23 are added to the output side of the logic circuit 26, and the output of the logic circuit 26 is applied to the gates of the inverter circuits 22 and 23. By switching the pMOS transistor, the power supply potential (Vdd) or the ground potential (GN
D) is output.

However, the above inverter circuits 22 and 23
Is composed of pMOS transistors only,
When the pMOS transistors Q27, 30 shown in FIG. 3 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 24, 2 are further added.
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The specific configuration of the level correction circuit 24 in the second embodiment is that between one output from the logic circuit 26 and the gate of the pMOS transistor Q27,
The source and drain of a pMOS transistor Q25 whose gate is grounded are connected to each other, and the output side of the pMOS transistor Q25 and the pMO transistor
The bootstrap method in which the capacitor C21 is connected between the S transistors Q26 and Q27 is adopted.

In this way, the level correction circuit 24 has the pM
The addition of the OS transistor Q25 and the capacitor C21 increases the gate capacitance of the pMOS transistor Q27 and holds the gate potential necessary for turning on the pMOS transistor Q27 with certainty. The output level does not increase by the value voltage, and the output can be corrected to a sufficiently low ground potential before output.

The level correction circuit 25, like the level correction circuit 24, uses the pMOS transistor Q28 and the capacitor C22 to increase the gate capacitance of the pMOS transistor Q30 and surely turn on the pMOS transistor Q30. Since the gate potential required for this is maintained, the output level does not rise by the threshold voltage, and the output can be corrected to a sufficiently low ground potential before output.

AND / NAND constructed as described above
The circuit 21 has a logical product (AND) from the inverter circuit 22 and a logical product (AND) from the inverter circuit 23 with respect to four inputs (a, ￣a, b, ￣b).
Is output. AND / NAND circuit 2 described in FIG.
The symbol of 1 is as shown in FIG. 4, and the AND output and the NAND output are output to the a input end and the b input end thereof.

Further, AND / NAN according to the present embodiment
The D circuit 21 uses inverters 22 and 23, level correction circuits 24 and 25 thereof, and transistors used in a logic circuit 26 including pass transistor logic as pMO.
Since only S transistors are used, the number of ion doping steps and the number of masks are reduced when the AND / NAND circuit is formed on the substrate using the semiconductor process, and the manufacturing process is simplified, thereby reducing the manufacturing cost. can do. In the AND / NAND circuit 21, a pMOS transistor is used to form the circuit, but an nMOS transistor may be used instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), the pMOS transistors Q21 and Q23 are turned off as shown in FIG. Then, since Q22 and Q24 are turned on, the pMOS transistors Q26 and Q30 of the inverter circuits 22 and 23 are turned off, but the pMOS transistors Q27 and Q29 are turned on and the AND output is "0" and the NAND output is "1". Become.

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the AND output is "0", The NAND output becomes "1". Also, the input a is "1" (the inverted a is "0").
When b is “0” (inversion b is “1”), the AND output is “0” and the NAND output is “1”.

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The AND output becomes "1" and the NAND output becomes "0". In this way, the AND / NAND circuit 21 of the present embodiment
Is output from the inverter circuits 22 and 23, respectively, as a logical product and a negative logical product with respect to the inputs of a and b.

Then, the AND / NAND of the present embodiment
The circuit 21 outputs the ground level as an AND output or a NAND output when the pMOS transistor Q27 or Q30 of the inverter circuits 22 and 23 is turned on. At this time, in the present embodiment, as shown in FIG. 3, since the level correction circuits 24 and 25 are provided on the gate side of the pMOS transistors Q27 and Q30, a low level is output as an AND output or a NAND output. Moreover, the rise of the low level can be prevented. Therefore, the AND / NAND circuit 21 according to the present embodiment can always output the appropriate Vdd level “1” and the ground level “0” as the AND output or the NAND output.

The AND / NA explained in FIG.
The ND circuit 21 is written as a symbol as shown in FIG. 4, and AND / NAND is applied to two inputs (a, b).
The logical product (AND) and the negative of the logical product (NAND) are output from the output side of the circuit 21.

(Third Embodiment) FIG. 5 is a diagram showing a configuration of an OR / NOR circuit 31 according to a third embodiment, and FIG. 6 is a symbol of the OR / NOR circuit 31 of FIG. It is a figure which shows and its input / output signal.

First, the structure will be described. OR shown in FIG.
The NOR circuit 31 is composed of inverter circuits 32 and 33, level correction circuits 34 and 35, and a logic circuit 36.

The four pMOS transistors Q31 to Q34 forming the logic circuit 36 generate a logical sum of the four inputs (a, ￣a, b, ￣b) and its negation using the pass transistor logic. To do. That is, when there are two inputs a and b, the inverse of that is the inverse a.
(_A) and inversion b (_b) are also input. Then, pMOS transistors Q31 and Q32 are connected in series between the input end of the inversion a and the ground, and a pMOS transistor Q33 is connected between the input end of a and the power supply (Vdd). Q34 is connected in series. Inversion b is input to the gates of the pMOS transistors Q32 and Q34 to perform switching, and
B is input to the gates of the transistors Q31 and Q33 to perform switching. And the above four MOS
Depending on the switching result of the transistor, pMOS
Connection between transistors Q31 and Q32 and pMOS
A high level "1" or low level "0" signal is output from the connection between the transistors Q33 and Q34.

However, the logic circuit 36 is the pMOS described above.
If only the transistors Q31 to Q34 are used, when the low level is output, the output level lost by the threshold voltage of the transistor is output. Therefore, in the OR / NOR circuit 31 of the present embodiment, the inverter circuits 32 and 33 are added to the output side of the logic circuit 36, and the logic circuit 3
By applying the output of No. 6 to the gates of the inverter circuits 32 and 33 and switching each pMOS transistor, the power supply potential (Vdd) or the ground potential (GN).
D) is output.

However, the above inverter circuits 32, 33
Is composed of pMOS transistors only,
When the pMOS transistors Q37 and 40 shown in FIG. 5 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 34, 3
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The concrete configuration of the level correction circuit 34 in the third embodiment is that a pMOS transistor whose gate is grounded is provided between one output from the logic circuit 36 and the gate of the pMOS transistor Q37. Q
35 is connected to the source and drain of the pMOS transistor Q35.
The bootstrap method in which the capacitor C31 is connected between the transistor Q36 and the connection portion between the transistors Q37 is adopted.

Therefore, in the level correction circuit 34, pMO
By using the S transistor Q35 and the capacitor C31, the gate capacitance of the pMOS transistor Q37 is increased and the gate potential for reliably turning on the pMOS transistor Q37 is held, so that the output level is equal to the threshold voltage. It is possible to correct and output the level to a sufficiently low ground potential.

In the level correction circuit 35, the gate capacitance of the pMOS transistor Q40 is increased to hold the gate potential for reliably turning on the pMOS transistor Q40, similarly to the level correction circuit 34, so that the output level is increased. It is possible to correct and output an appropriate level.

The OR / NOR circuit 31 configured as described above has four inputs (a, ￣a, b, ￣b),
The inverter circuit 32 outputs a logical sum (OR), and the inverter circuit 33 outputs a negative logical sum (NOR). The symbol of the OR / NOR circuit 31 described with reference to FIG. 5 is as shown in FIG. 6, and the OR output and NOR output are output to the a input end and the b input end of the symbol.

Further, in the OR / NOR circuit 31 according to the present embodiment, the transistors used in the inverter circuits 32 and 33, their level correction circuits 34 and 35, and the logic circuit 36 composed of pass transistor logic are pMOS transistors. Since it is configured only, when the inverter circuit is formed on the substrate using the semiconductor process, the number of ion doping processes and the number of masks are reduced, and the manufacturing process is simplified, so that the manufacturing cost can be reduced. . Although the OR / NOR circuit 31 is configured by using the pMOS transistor, it may be configured by using the nMOS transistor instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), the pMOS transistors Q32 and Q34 are turned off as shown in FIG. Then, since Q31 and Q33 are turned on, the pMOS transistors Q36 and Q40 of the inverter circuits 32 and 33 are turned off, but the pMOS transistors Q37 and Q39 are turned on and the OR output is "0",
The NOR output becomes "1".

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the OR output is "1", The NOR output becomes "0".
In addition, the input a is “1” (inversion a is “0”), and b
Is "0" (inversion b is "1"), the OR output is "1" and the NOR output is "0".

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The OR output becomes "1" and the NOR output becomes "0". As described above, the OR / NOR circuit 31 according to the present embodiment has a, b
Is output from the OR output end, and negative logical sums that negate it are output from the NOR output end, respectively.

The OR / NOR circuit 31 of the present embodiment outputs the ground level as an OR output or a NOR output when the pMOS transistor Q37 or Q40 of the inverter circuits 32 and 33 is turned on.
At this time, in the present embodiment, as shown in FIG. 5, the level correction circuits 34 and 35 cause the pMOS transistor Q3 to operate.
Since it is provided on the gate side of 7 and Q40, OR
When the low level is output as the output or NOR output, the rise of the low level can be prevented. Therefore,
The OR / NOR circuit 31 according to the present embodiment can always output a proper Vdd level “1” and a ground level “0” as an OR output or a NOR output.

Then, the OR / NOR explained in FIG.
When the circuit 31 is written with a symbol, it becomes as shown in FIG.
For the two inputs (a, b), the OR / NOR circuit 31
OR from the output side of the and the negation of the OR (N
OR) is output.

(Fourth Embodiment) FIG. 7 is a diagram showing a configuration of an EXOR / EXNOR circuit 41 according to a fourth embodiment, and FIG. 8 is a symbol of the EXOR / EXNOR circuit 41 of FIG. It is a figure which shows and its input / output signal.

First, the structure will be described. EXO shown in FIG.
The R / EXNOR circuit 41 includes inverter circuits 42 and 43.
And level correction circuits 44 and 45, and a logic circuit 46. 4 pMOSs forming the logic circuit 46
Transistors Q41-Q44 are pass transistors
Exclusive OR (EXOR) and its negation (EXNO) for four inputs (a, ￣a, b, ￣b) using logic.
R) and are generated. That is, the input is a, b
In the case of two, the inversion a (￣a) and the inversion b which are the negation.
(￣b) is also entered.

The input of the inverted b is input to the level correction circuit 44 of the next stage via the pMOS transistor Q41, and the input of b is the pMOS transistor Q42.
Is input to the level correction circuit 45 of the next stage via the
It is connected to the output side of the pMOS transistor Q42 via the OS transistor Q43, and from the input side of the pMOS transistor Q42 to the pMOS transistor Q42.
It is connected to the output side of the pMOS transistor Q41 via 44.

The above pMOS transistors Q41 and Q4
An inversion a is input to the gate of 2 to perform switching, and an a is input to the gates of the pMOS transistors Q43 and Q44 to perform switching, thereby forming an exclusive OR logic circuit 46. . Then, a high level "1" or a low level "0" signal is output to the level correction circuits 44 and 45 according to the switching result of the MOS transistor.

However, the logic circuit 46 is the pMOS described above.
If only the transistors Q41 to Q44 are used, when a low level is output, an output level lost by the threshold voltage of the transistor is output. Therefore, in the EXOR / EXNOR circuit 41 of the present embodiment, the inverter circuits 42 and 43 are added to the output side of the logic circuit 46,
The output of the logic circuit 46 is applied to the gates of the inverter circuits 42 and 43, and each pMOS transistor is switched to output the power supply potential (Vdd) or the ground potential (GND).

However, the above inverter circuits 32 and 33
Is composed of pMOS transistors only,
When the pMOS transistors Q47 and Q50 of FIG. 7 are turned on to output the ground level "0", the output level rises by the threshold voltage of the transistor. Therefore, in the present embodiment, the level correction circuits 44, 4 are further added.
5 is provided and the output level is corrected to output a sufficiently low ground potential.

The concrete configuration of the level correction circuit 44 in the fourth embodiment is that a pMOS transistor whose gate is grounded is provided between one output from the logic circuit 46 and the gate of the pMOS transistor Q47. Q
45 is connected to the source and drain thereof, and the output side of the pMOS transistor Q45 is connected to the pMOS transistor Q45.
The bootstrap method in which the capacitor C41 is connected between the transistor Q46 and the connection portion between the transistors Q47 is adopted.

Therefore, in the level correction circuit 44, pMO
By using the S transistor Q45 and the capacitor C41, the gate capacitance of the pMOS transistor Q47 is increased and the gate potential for reliably turning on the pMOS transistor Q47 is held, so that the output level is equal to the threshold voltage. It is possible to correct and output the level to a sufficiently low ground potential.

Further, in the level correction circuit 45, the gate capacitance of the pMOS transistor Q50 is increased and the gate potential for reliably turning on the pMOS transistor Q50 is held, as in the level correction circuit 44, so that the output level is increased. It is possible to correct and output an appropriate level.

EXOR / EXN constructed as described above
The OR circuit 41 outputs an exclusive OR (EX) from the inverter circuit 42 to the four inputs (a, ￣a, b, ￣b).
OR) is output from the inverter circuit 43 as a negative exclusive OR (EXNOR).

The symbols of the EXOR / EXNOR circuit 41 described with reference to FIG. 7 are as shown in FIG.
An EXOR output and an EXNOR output are output to the input end. Further, the EXOR / EX according to the present embodiment
The NOR circuit 41 uses p-type transistors for the inverter circuits 42 and 43, their level correction circuits 44 and 45, and a logic circuit 46 including pass transistor logic.
Since only MOS transistors are used, when forming an inverter circuit on a substrate using a semiconductor process, the number of ion doping processes and the number of masks are reduced, and the manufacturing process is simplified, thereby reducing the manufacturing cost. You can

The EXOR / EXNOR circuit 41 is used.
In the above, the circuit is configured using the pMOS transistor, but an nMOS transistor may be used instead of the pMOS transistor.

Next, the operation will be described. When the input a is "0" (inversion a is "1") and b is "0" (inversion b is "1"), as shown in FIG. 7, the pMOS transistors Q41 and Q42 are turned off. Then, since Q43 and Q44 are turned on, the pMOS transistors Q36 and Q40 of the inverter circuits 42 and 43 are turned off, but the pMOS transistors Q47 and Q49 are turned on and the EXOR output is "0" and the EXNOR output is "1". Become.

Similarly to the above, when the input a is "0" (inversion a is "1") and b is "1" (inversion b is "0"), the EXOR output is "1", EXNOR output is "0"
Becomes When the input a is “1” (inversion a is “0”) and b is “0” (inversion b is “1”),
The EXOR output becomes "1" and the EXNOR output becomes "0".

Further, when the input a is "1" (inversion a is "0") and b is "1" (inversion b is "0"),
The EXOR output becomes "0" and the EXNOR output becomes "1". In this way, the EXOR / EXNOR of the present embodiment is
In the circuit 41, the exclusive OR for inputs a and b is EX.
It is output from the OR output end, and a negative exclusive OR that negates it is output from the EXNOR output end.

In addition, the EXOR / EXNO of the present embodiment
The R circuit 41 is a pMO of the inverter circuits 42 and 43.
S transistor Q47 or pMOS transistor Q
When 50 is turned on, the ground level is output as an OR output or a NOR output. At this time, in the present embodiment, as shown in FIG. 5, since the level correction circuits 44 and 45 are provided on the gate sides of the pMOS transistors Q47 and Q50, the EXOR output and EXNO output are obtained.
When the low level is output as the R output, the rise of the low level can be prevented. Therefore, the EXOR / EXNOR circuit 41 of the present embodiment always keeps the proper Vdd.
EXO the level "1" and the ground level "0"
It is output as R output or EXNOR output.

Then, the EXOR and EXN of FIG.
The OR circuit 41 is represented by a symbol as shown in FIG. 8. EXOR.EXN is given to two inputs (a, b).
The OR circuit 41 outputs an exclusive OR (EXOR) and a negation (EXNOR) of the exclusive OR.

As described above, in the first to fourth embodiments, the configurations of the four types of basic logic circuits in which the level correction circuit is added to the inverter circuit and the negation circuit thereof have been described. By combining these logic circuits, all 16 pool algebras can be calculated.

In the circuit configuration described in the above embodiment in which the level correction circuit is added to the inverter circuit, a basic circuit other than the logic circuit, for example, a latch circuit or a tri-state circuit can be configured. Therefore, in the following fifth embodiment, a configuration example of the latch circuit will be
In the sixth embodiment, a configuration example of the tri-state circuit will be described.

(Fifth Embodiment) FIG. 9 is a diagram showing a configuration of a latch circuit 51 according to a fifth embodiment. First, the configuration will be described. The latch circuit 51 shown in FIG. 9 is different from the configuration of the pMOS inverter circuit 11 according to the first embodiment described in FIG. 1 in that it has an input signal control unit 56 that controls an input signal from the input side and an output. And a feedback signal control section 57 for feeding back an output signal from the input side to the input side.

Therefore, the pMOS inverter circuit 1 of FIG.
As shown in FIG. 9, the structure of the part corresponding to 1 is pM
Q1 → Q56, Q2 → Q57, Q
3 → Q55, Q4 → Q59, Q5 → Q60, Q6 → Q5
8 respectively, in the capacitor C1 → C51, C
2 → C52, which corresponds to 2 sets of inverter circuits 5
2, 53 and their level correction circuits 54, 55 are configured.

Then, the two sets of inverter circuits 52,
An input signal control unit 56 for controlling an input signal is provided between each gate of the pMOS transistor constituting 53 and the input end (I) and the inverting input end (_I). The input signal control unit 56 is composed of pMOS transistors Q51 and Q52 which are switching elements, and the inverted clock signal (_clk) for switching is applied to the gates of the pMOS transistors Q51 and Q52. It is input from the input end (-L).

A feedback signal control unit 57 is provided between the output side and the input side of the inverter circuits 52 and 53, and is composed of a feedback loop and pMOS transistors Q53 and Q54.

That is, the output (--OUT) from the output terminal (--O) of the inverter circuit 52 is connected to the drain side of the pMOS transistor Q52 described above by a feedback loop through the pMOS transistor Q54 which is a switching element. , The inverter circuit 5
The output (OUT) from the output end (O) of 3 is the pMOS transistor Q described above by the feedback loop.
PMOS, which is a switching element, on the drain side of 51
It is connected through the transistor Q53.

Then, the above-mentioned pMOS transistor Q
A clock signal (clk) for controlling switching is applied to the control signal input terminal (L) at the gates of 53 and Q54.
It is configured to be input from. As described above, the latch circuit 51 shown in FIG. 9 is obtained by newly adding four pMOS transistors Q51 to Q54 to the inverter circuit shown in FIG. And the pMOS transistor Q
51 to Q54 are input terminals for the inversion control signal from the outside (-
L) and the control signal from the control signal input terminal (L) are used to switch between the through operation and the latch operation of the latch circuit 51.

Next, the operation will be described. In the latch circuit 51 shown in FIG. 9, the clock signal (clk) input to the control signal input end (L) is high “1”, and the inverted clock signal (_clk) at the inverted control signal input end (_L). ) Is low “0”, the clock signal (clk) input to the control signal input end (L) is low “0” and the inverted control signal input end (−L). When the inverted clock signal (_clk) of)) is high “1”, the latch state is set.

The above-mentioned through state means the input end (I).
The input signal (IN) from is output as it is as the output signal (OUT) of the output end (O), and the inverting input end (
Inverted input signal (-IN) from I) is output as it is as the inverted output signal (-OUT) of the inverted output end (-O). Further, the above-mentioned latched state means holding the output state before latching.

Specifically, as shown in FIG. 9, the clock signal (clk) is high "1", and the inverted clock signal (-
When clk) is low “0”, it is in the through state and p
The MOS transistors Q53 and Q54 are turned off, and the pMOS
The transistors Q51 and Q52 are turned on.

Therefore, the input signal (IN) is "0",
When the inverted input signal (_IN) is "1", the pMOS transistors Q57 and Q59 are turned off, and the pMOS transistors Q56 and Q60 are turned on, so that the through state is output as it is and "0" is output to the output signal (OUT). "But,
"1" is output to the inverted output signal (_OUT).

Next, the clock signal (clk) is low "0" and the inverted clock signal (-clk) is high "1".
In the case of, the pMOS transistor Q53 and Q54 of FIG. 9 are turned on and the pMOS transistor Q53 is turned on.
51 and Q52 are turned off. Therefore, "0" of the output signal (OUT) in the immediately preceding through state is pM regardless of the input signals of the input end (I) and the inverting input end (-I).
The pMOS transistors Q56 and Q60 are turned on via the OS transistor Q53, and the inverted output signal (--OU
"1" in T) is transmitted through the pMOS transistor Q54,
Since the pMOS transistors Q57 and Q59 are turned off, the previous output state is maintained, the output signal (IN) is "0", and the inverted input signal (-IN) "1" is output as it is.

As described above, the latch circuit shown in FIG.
The gates of the individual pMOS transistors Q51 to Q54 are switched between the through operation and the latch operation according to a control signal from the outside.

Further, the latch circuit 51 of the above-mentioned embodiment.
Is the p of the inverter circuits 52 and 53, as shown in FIG.
In the gate portions of the MOS transistors Q57 and Q60, p
MOS transistors Q55, Q58 and capacitor C5
Since the level correction circuits 54 and 55 including C1 and C52 are provided respectively, output level loss is eliminated, and direct current leakage current is eliminated, so that power consumption can be reduced.

Furthermore, the latch circuit 51 of the above-mentioned embodiment.
Are all p-type MOS transistors of the same conductivity type.
Since it is composed of MOS transistors, the number of ion doping steps and the number of masks can be reduced when forming on a substrate using a semiconductor process as compared with a circuit using a conventional CMOS, so that the manufacturing cost can be reduced.

In the latch circuit 51, the pMOS
Although the circuit is composed of transistors, the present invention is not limited to this, and an nMOS transistor may be used instead of the pMOS transistor.

(Sixth Embodiment) FIG. 10 is a diagram showing a configuration example of a tri-state circuit 61 for generating an alternating voltage. The tri-state circuit 61 is used, for example, when an alternating drive voltage is generated because the liquid crystal is deteriorated when a direct current voltage is applied to the liquid crystal when the liquid crystal drive device or the like drives the liquid crystal.

First, the structure will be described. As shown in FIG. 10, the pMOS transistors Q61 to Q68 include a logic circuit 66 that generates a predetermined logic based on four input signals of d, inversion d (-d), WF, and inversion WF (-WF). I am configuring. Then, the tri-state circuit 61 is
By inputting positive logic and negative logic to d and WF respectively, an alternating voltage generated by switching three kinds of power source voltages VH, VC and VL is output from the output D (provided that VH> VC > VL). Here, the pass transistor logic method is used as in the above-described embodiment.

Then, for example, when the tri-state circuit 61 is used in a liquid crystal driving device, d of the input signal is used.
Can be used to indicate whether or not write data is present, that is, whether or not the liquid crystal is driven, and WF indicates whether the liquid crystal drive voltage is positive or negative.

Next, inverter circuits 62 and 63 are formed on the output side of the logic circuit 66. For example, the inverter circuit 62 is connected from the power source (Vdd) to the ground (G
PMOS transistors Q71 and Q7
0 source or drain is connected in series,
The output from the logic circuit 66 is the pMOS transistor Q7.
1 and Q70 are input to the gate. In the present embodiment, a pMOS transistor Q69 whose gate is grounded is connected between the gate of the pMOS transistor Q70 of the inverter circuit 62 and a predetermined output end of the logic circuit 66, and the pMOS transistor Q6 is connected to the pMOS transistor Q6.
9 output side and the pMOS transistors Q71 and Q70
A level correction circuit 64 is configured by connecting a capacitor C61 between the connection part of the and.

Further, the inverter circuit 63 is similar to the above-described inverter circuit 62 in that the pMOS transistor Q7 is used.
4 and Q73, and a level correction circuit 65
Is composed of a pMOS transistor Q72 and a capacitor C62. In this way, the inverter circuits 62, 6
Since the gates of the pMOS transistors of No. 3 are provided with the level correction circuits 64 and 65, the gate capacitance of the pMOS transistors Q70 or Q73 is increased to perform switching reliably, and an appropriate low level "L" is obtained. A signal can be output.

Then, the tri-state circuit 61 according to the present embodiment applies the output signals from the above-mentioned inverter circuits 62 and 63 to the gates of the pMOS transistors Q75 and Q76, respectively, thereby switching the high-potential power supply. The voltage VH or the low-potential power supply voltage VL is selectively output from the output terminal D, and the intermediate-potential power supply voltage VC is supplied to the pMOS transistor Q77.
Are switched by the d input and output.

In the present embodiment, in addition to the above configuration, a capacitor C63 is further connected between the gate of the pMOS transistor Q75 and the ground, and
It is connected between the gate of the pMOS transistor Q76 and the ground via a capacitor C64. Therefore, since the gate capacitances of the pMOS transistors Q75 and Q76 connected to the power supply voltage of the high potential (VH) and the low potential (VL) increase, the pMOS transistor Q7
5 and Q76 can be surely switched, and the power supply voltages VH and VL at appropriate levels without voltage rise or voltage drop are output.

As described above, in the tri-state circuit 61 of this embodiment, the output level of the logic circuit 66 is optimized by providing the inverter circuits 62 and 63 on the output side of the logic circuit 66. In particular, the inverter circuit 62,
When 63 is composed of a pMOS transistor,
By providing the level correction circuits 64 and 65 including the pMOS transistor Q69 or Q72 and the capacitor C61 or C62 on the side of the ground side pMOS transistor Q70 or Q73, the output level is increased by the threshold voltage of the pMOS transistor. Can be prevented. Further, the tri-state circuit 61 according to the present embodiment switches the pMOS transistors Q75 and Q76 in which the outputs of the inverter circuits 62 and 63 are connected to the high potential (VH) and low potential (VL) power supply voltages. For selective output, capacitors C63 and C64 are provided on the gate side to increase the gate capacitance and output power supply voltages VH and VL at appropriate levels.

Next, the operation will be described. The tri-state circuit 61 shown in FIG. 10 inputs D to WF by inputting either positive logic or negative logic to each of d and WF.
Any one of H, VC and VL is selectively output. Actually, by changing the inputs d and WF, VH and V
An alternating signal composed of C and VL is generated.

First, when the input signals d and WF are "0", the pMOS transistors Q75 and Q76 are turned off and the pMOS transistor Q77 is turned on, so that the intermediate potential (VC) is output from D. In addition, d of the input signal
Is 0 and WF is 1, the intermediate potential (VC) is output from D similarly to the above. This is because when d is "0", the pMOS transistor Q61 of the logic circuit 66,
Since Q63, Q65, and Q67 are turned off, the pMOS transistor Q77 is turned on without being influenced by the input signal of WF, and Vc is output from D.

When the input signal d is "1", the switching transistor Q77 is turned off and the logic circuit 6
6 pMOS transistors Q62, Q64, Q66, Q
68 is turned off, and conversely, pMOS transistors Q61, Q63, Q65, Q67 are turned on. Therefore, the output voltage from D changes based on the input signal of WF.

Therefore, when WF is "0", pMOS
Since transistor Q76 turns on and Q75 turns off,
A low potential (VL) is output from D. When WF is "1", the pMOS transistor Q75 is turned on and Q76 is turned off, so that the high potential (VH) is output from D.

As described above, the tri-state circuit 61 of the present embodiment can be composed of only the pMOS transistor and the capacitor, so that the structure is simple and can be manufactured in a small number of steps, so that the cost can be reduced.

Further, the tri-state circuit 61 of the above-described embodiment uses the inverter circuits 62 and 63 and the level correction circuits 64 and 65 to change the output level of the logic circuit 66 constituted by the pMOS transistors Q61 to Q68. In addition to the correction, the capacitors C63 and C64 are provided to surely switch the pMOS transistors Q75 and Q76, so that the power supply voltage V of an appropriate level is obtained.
It is possible to selectively output H and VL. In particular, pM
In the case of the OS transistor, it is possible to solve the problem that the low-level output voltage VL does not fall sufficiently, and it is possible to always output the voltage level in which it surely drops to a predetermined potential. I can do it now.

In the tristate circuit 61,
The circuit was constructed using pMOS transistors.
An nMOS transistor may be used instead of the MOS transistor.

(Seventh Embodiment) FIG. 11 shows a TFT-LCD integrated with a drive circuit to which the semiconductor device of the present invention is applied.
It is a schematic block diagram of 71. This drive circuit integrated TFT-
The LCD 71 forms a thin film transistor serving as a switching element for each pixel on a glass substrate in a display area of an LCD (Liquid Crystal Display), and includes a drain driver (data line driving circuit) and a gate driver (scanning line driving circuit). This liquid crystal drive circuit is integrally formed on a glass substrate.

First, the structure will be described. As shown in FIG. 11, the drive circuit integrated TFT-LCD 71 includes a liquid crystal display panel (TFT-LCD) 73 in which a TFT is formed for each pixel in a display area on a glass substrate 72, and the liquid crystal display panel 73. A gate driver 74 that applies a scanning signal to the gate of each TFT to create a selected state and a non-selected state;
The TFT selected by the gate driver 74
And a drain driver 75 for driving a liquid crystal for each pixel by applying a display signal to the pixel.

The liquid crystal display panel 73, the gate driver 74, and the drain driver 75 described above are provided on the glass substrate 7.
2 is integrally formed. FIG. 12 is a partial circuit diagram in which the drain driver 75 shown in FIG. 11 is configured by the latch circuit having a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit, an AND / NAND circuit, and a tri-state circuit. is there.

The drain driver 75 shown in FIG. 12 includes latch circuits 81, 82, 83 ..., AND / NAND circuits 91, 92 ..., Latch circuits 101, 102 ..., Latch circuits 111, 112 ,. State circuit 12
1, 122 ... And so on.

The latch circuits 81, 82 and 83 are connected to a horizontal synchronizing signal (XSC
L) and the inverted horizontal synchronizing signal (-XSCL) are 1 at the control signal input end (L) and the inverted control signal input end (-L).
Every other time, the signals are input in the opposite phase, and when "1" is entered in the control signal input end (L), the input signal is output through.
When "0" is entered, the previous input signal is latched.

As the input signal to the latch circuit 81, the XD clock and the inverted XD clock are input, and the output signal corresponding to the through state and the latch state is output from the output end (O) and the inverted output end (-O). And is input to the input ends of the AND / NAND circuit 91 and the latch circuit 82 at the next stage. Similarly, the output signal of the latch circuit 82 is input to the AND / NAND circuits 91 and 92 and the input end of the latch circuit 83 of the next stage.

Then, the AND / NAND circuit 91 inputs the output (OUT) of the latch circuit 81 and the inverted output (-OUT) of the latch circuit 82 to control the logical product and its negation of the latch circuit 101. Input to the signal input end (L) and the inverted control signal input end (-L). AND NA
Similarly, the ND circuit 92 also outputs the inverted output (−) of the latch circuit 82.
OUT) and the output (OUT) of the latch circuit 83 are input, and the logical product and the negation thereof are input to the control signal input end (L) and the inverted control signal input end (-L) of the latch circuit 102. It

The latch circuit 101 and the latch circuit 102 are
In accordance with the timing of the output signals from the AND / NAND circuits 91 and 92, the data for each pixel input from a data conversion circuit (not shown) is latched, and the latched data is respectively transferred to the latch circuit 111 of the next stage. 112
Output to The latch circuits 111 and 112 use the clock O
The data for each pixel input at the timing of P is latched, and the output is latched in each tri-state circuit 121.
And 122.

The tri-state circuits 121 and 122 combine the input signals from the above-mentioned latch circuits 111 and 112 with the AC signal WF to produce VH, VC and V.
By appropriately selecting the three types of power source voltages of L 3, an alternating display signal is generated. The alternating display signal output from the tri-state circuit 121 is
The alternating display signal output to the drain line D1 and output from the tri-state circuit 122 is output to the drain line D2.

Note that FIG. 12 only illustrates a part of the configuration of the drain driver 75 which supplies the drain lines for two lines. In practice, the above circuits are connected in the horizontal scanning direction according to the number of pixels. Are arranged. This allows
A display signal corresponding to the position of each drain line can be supplied.

As described above, the latch circuit, ANDN
Since the drain driver 75 composed of an AND circuit and a tri-state circuit can be composed of only a pMOS transistor and a capacitor, the conventional CMOS
Compared to the case of using transistors, the transistor structure is simpler and the number of manufacturing steps is reduced. If a pMOS transistor is also used for the pixel TFT transistor, a drive circuit integrated type is formed on the same plane of the glass substrate. TFT-LCD can be created at the same time,
There is an advantage that the cost can be reduced.

Further, the drain driver 75 according to the present embodiment has a small DC leak current, low power consumption, and an appropriate output level, especially a low level, as in the case of being composed of CMOS transistors. There is an advantage that the output can be suppressed to a sufficiently low level.

Next, FIG. 13 shows a gate driver 74 shown in FIG. 11, which is a latch circuit having a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit.
FIG. 7 is a partial circuit diagram formed of a NOR circuit and an inverter circuit. The gate driver 74 shown in FIG. 13 includes latch circuits 131, 132, 133, 134, ..., NOR circuits 141, 142, 143, 144, ..., Inverter circuits 151, 152, 153, 154, ..., Inverter circuits 161, 162. , 163, 164, ..., Inverter circuits 171, 172, 173, 174 ,.

Latch circuits 131, 132, 133, 13
4 ... is a vertical sync signal (YSCL) input from a controller (not shown) and an inverted vertical sync signal (YSCL).
L) is input to the control signal input end (L) and the inverted control signal input end (-L) every other phase in reverse phase, and "1" is input to the control signal input end (L). And the input signal is output through, and when "0" is input, the previous input signal is latched.

The YD clock is input as an input signal to the latch circuit 131, an output signal corresponding to the through state and the latch state is output from the output end (O) and the inverted output end (_O), and the NOR circuit is input. 141 and the input terminal of the latch circuit 132 at the next stage. Similarly, the output signal of the latch circuit 132 is input to the input ends of the NOR circuit 141, the NOR circuit 142, and the latch circuit 133 at the next stage.

The NOR circuit 141 is supplied with the output (OUT) of the latch circuit 131 and the inverted output (-OUT) of the latch circuit 132, and a negative logical sum is continuously given to the inverter circuits 151 to 161, 171. Is input and a gate signal is output to the gate line G1. By the same operation as described above, each inverter circuit 172, 17
Gate lines G2, G from the output ends of 3, 174
Gate signals are sequentially output to 3 and G4.

Note that FIG. 13 merely illustrates a part of the configuration of the gate driver 74 which supplies the gate lines for two lines, and the above-mentioned circuits are arranged according to the number of lines arranged in the vertical direction. Has been done. As a result, each gate line is line-scanned by a predetermined scanning method to bring each gate line into a selected state or a non-selected state.

As described above, the gate driver 74 composed of the latch circuit, the NOR circuit and the inverter circuit.
Can be composed of only a pMOS transistor and a capacitor as in the case of the drain driver 75, so that the transistor structure is simpler and the number of manufacturing steps is reduced as compared with the case of the conventional CMOS transistor. be able to. In particular, if a pMOS transistor is adopted as the TFT transistor of the pixel, the driving circuit integrated TFT-LCD can be formed on the same plane of the glass substrate, so that the cost can be reduced. Further, the gate driver 74 of the present embodiment has the advantages of low power consumption similar to that of CMOS and capable of suppressing an appropriate output level, particularly a low level output to a sufficiently low level.

As described above, four kinds of basic logic circuits are constructed by using MOS transistors (pMOS, nMOS) of the same conductivity type and capacitors, and by combining these, all kinds of logical operations are possible. Can be configured, and these circuits can be manufactured at low cost. Further, since the level correction circuit is always added, even if the MOS transistors of the same conductivity type are used, the output level does not decrease and an appropriate output level can be obtained.

Of course, not only a logic circuit is formed by using the MOS transistors (pMOS, nMOS) of the same conductivity type and a capacitor as described above, but a basic circuit such as a latch circuit or a tri-state circuit is constructed and used in combination. Thereby, the same effect as the above can be obtained.

[0140]

Effects of the Invention] According to the semiconductor device according to claim 1, the thin film transistor of the inverter circuit is formed of the same conductivity type, an ion doping step number and mask for forming the inverter circuit on a substrate using a semiconductor process The number is smaller than that of conventional CMOS transistors,
The manufacturing cost can be reduced. Further, since the inverter circuit includes the level correction circuit, it is possible to always output an appropriate level from the output end of the inverter circuit.

According to the semiconductor device of claims 2 to 5,
An inverter circuit is provided at the output stage of each of the AND circuit, the OR circuit, and the EXOR circuit to optimize the output level of the logic output, and a level correction circuit is provided at the gate portion of the inverter circuit to output the output level from the inverter circuit. An appropriate output level can be obtained by correcting. Further, the AND circuit, a thin film transistor constituting an OR circuit, an EXOR circuit, due to so as to consist only of the same conductivity type, it requires less ion doping step number and the number of masks it is possible to reduce the manufacturing cost.

[0142] According to the semiconductor device according to claim 6, the level correction circuit of a semiconductor device according to claims 1 to 5 is composed of a thin film transistor and the capacitor, by increasing the gate capacitance of the inverter circuit , to compensate for variations in the gate potential of the thin film transistors constituting the inverter circuit, so-called, by adopting a bootstrap method, the proper output level is obtained from the inverter circuit. Moreover, the level correction circuit, the use of the thin film transistor of the same conductivity type as the logic circuit and an inverter circuit, an ion doping step number and the mask number is reduced, thereby reducing the manufacturing cost.

A semiconductor device according to a seventh aspect is the semiconductor device according to the second aspect.
The inverter circuit according to claim 6 has two logic circuits.
A pair of thin-film transistors of the two sets of inverter circuits are connected so that their connection positions to the gates of the two sets of inverter circuits are opposite to each other. Therefore, the outputs from the two sets of inverter circuits can output the logical result of the logic circuit and its negation. Of course, also the case, it is possible to a thin film transistor of the same conductivity type, an appropriate output level is obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a pMOS inverter circuit according to a first embodiment.

FIG. 2 is a diagram showing a symbol of the pMOS inverter circuit of FIG. 1 and its input / output signals.

FIG. 3 is a diagram showing a configuration of an AND / NAND circuit according to a second embodiment.

FIG. 4 is a diagram showing symbols of the AND / NAND circuit of FIG. 3 and its input / output signals.

FIG. 5 is a diagram showing a configuration of an OR / NOR circuit according to a third embodiment.

6 is a diagram showing symbols of the OR / NOR circuit of FIG. 5 and its input / output signals.

FIG. 7 shows EXOR / EXNOR according to a fourth embodiment.
The figure which shows the structure of a circuit.

8 is a diagram showing symbols of the EXOR / EXNOR circuit of FIG. 7 and input / output signals thereof.

FIG. 9 is a diagram showing a configuration of a latch circuit according to a fifth embodiment.

FIG. 10 is a diagram showing a configuration example of a tri-state circuit that generates an alternating voltage.

FIG. 11 is a schematic configuration diagram of a TFT-LCD integrated with a drive circuit to which the semiconductor device of the present invention is applied.

FIG. 12 is a circuit diagram showing an AND / NAND circuit in which the drain driver shown in FIG. 11 is provided with a logic circuit composed of pMOS transistors, an inverter circuit and a level correction circuit
The partial circuit diagram comprised by the circuit and the tri-state circuit.

13 is a partial circuit diagram in which the gate driver shown in FIG. 11 is configured by a latch circuit including a logic circuit formed of pMOS transistors, an inverter circuit, and a level correction circuit, a NOR circuit, and an inverter circuit.

FIG. 14 is a diagram showing a configuration of a CMOS inverter circuit.

FIG. 15 is a diagram showing a configuration of a ratioless inverter circuit.

[Description of Reference Signs] 11 pMOS inverter circuit 12, 13 inverter circuit 14, 15 level correction circuit 21 AND / NAND circuit 22, 23 inverter circuit 24, 25 level correction circuit 26 logic circuit 31 OR / NOR circuit 32, 33 inverter circuit 34 , 35 level correction circuit 36 logic circuit 41 EXOR / EXNOR circuit 42, 43 inverter circuit 44, 45 level correction circuit 46 logic circuit

Claims (7)

[Claims] 1. A first and a second MOS transistor in which at least two sources or drains of the same conductivity type MOS transistor are connected in series from a power source to a ground, and a positive gate is provided to either one of the MOS transistors. Alternatively, an input end for inputting a negative polarity gate signal, an inverting input end for inputting a gate signal having a polarity opposite to that of the input end to the gate of the other MOS transistor, the first MOS transistor and the second MOS transistor. A semiconductor device comprising an inverter circuit comprising: an output terminal that outputs an output signal obtained by inverting the polarity of an input signal from the input terminal or the inverting input terminal from the connection portion of the MOS transistor, An output signal output from the output terminal is provided between at least one of the input terminal and the inverting input terminal of the inverter circuit and the gate. A semiconductor device characterized by comprising a level correction circuit for correcting the Le. 2. A logic circuit using a plurality of MOS transistors of the same conductivity type to execute a logical operation on a plurality of inputs, and a source or a drain of a MOS transistor of the same conductivity type as the logic circuit, at least from the power supply to the ground. Two MOS transistors are connected in series, and a logic output is respectively input from the output section of the logic circuit to each gate of the two MOS transistors, and an output end of a connection section between two MOS transistors connected in series. An inverter circuit that outputs a logical operation result from the logic circuit, and a level correction circuit that is provided between the output part of the logic circuit and the gate of the inverter circuit and corrects the output level output from the output end of the inverter circuit. A semiconductor device comprising: 3. The semiconductor device according to claim 2, wherein the logic circuit includes a logic circuit that executes a logical product. 4. The semiconductor device according to claim 2, wherein the logic circuit includes a logic circuit that executes a logical sum. 5. The semiconductor device according to claim 2, wherein the logic circuit includes a logic circuit that executes an exclusive OR. 6. The level correction circuit includes a MOS transistor and a capacitor of the same conductivity type as the inverter circuit, and the MOS transistor forming the level correction circuit includes:
At least one of the MOS transistors of the inverter circuit is connected via a source and a drain between the gate and the input, and both ends of a capacitor forming the level correction circuit have an output side and a gate of the MOS transistor of the level correction circuit. And a connection portion between two MOS transistors connected in series of the inverter circuit, and compensates for fluctuations in the gate potential of the MOS transistor of the inverter circuit. The semiconductor device according to any one of claims 1 to 5. 7. The inverter circuit is provided in two sets with respect to the logic circuit, and gates of respective MOS transistors of the two sets of inverter circuits are provided for two logic outputs of opposite polarities output from the logic circuit. 7. The output from the two sets of inverter circuits is composed of the logical result of the logic circuit and its negation. The semiconductor device according to any one of 1.