JPH0937057A - Method and device for erasing marker - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for erasing a marker capable of obtaining B picture output of no difference or small difference between the density of a marker removing part and that of a peripheral picture element. SOLUTION: Picture elements are successively supplied for a circuit for calculating a number of peripheral picture elements and an average density level 64 in a peripheral picture element level calculation circuit 6 from the three lines of (n) to n+2. The circuit 64 obtains the number ADD 1 of picture elements under the density of the marker and the total sum of the density of the picture elements under the density of the marker from the picture elements of 3×3 and divides the total sum of the density to calculate the background level DIV 1 of a watching picture element included in the picture elements of 3×3. A background level selection circuit 65 selects the background level DIV 1 when the number of objects ADD 1 is not less than a planned number of objects and selects the background level of the watching picture element just before. An output picture selection circuit 9 selects a background level OUT 1 when the watching picture element is the marker and replaces the marker with the background level OUT 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a marker erasing method and apparatus, and more particularly to a marker erasing method and apparatus capable of removing a marker written on a document without causing a sense of discomfort with surrounding pixels.

[0002]

2. Description of the Related Art Conventionally, a technique has been developed in which a marker provided on a document is removed by a marker pen having a predetermined density to obtain an image output without a marker. An example of a device for removing the marker is disclosed in Japanese Patent Laid-Open No. 4-5346. In this publication, as shown in FIG. 9, the background level signal 11 and the image input data 12 are used as input signals, and the marker detecting unit 1 is used.
There is disclosed a marker removing device including a multiplexer 14 which uses the detection signal of No. 3 as a selection signal. The multiplexer 14 selects the A terminal when the marker is detected by the marker detection unit 13, and selects the B terminal when the marker is not detected to be the image output 15. As a result,
It is possible to obtain the image output 15 in which the marker is removed from the image input data 12 and the portion where the marker is removed is replaced with the background level. Another example is disclosed in Japanese Patent Laid-Open No. 4-313744. This publication discloses that a density histogram of the entire page of a document is obtained and the density having the maximum value is adopted as the background level.

[0003]

According to the prior art disclosed in the above-mentioned first publication, there is a problem that no consideration is given to a method for specifically obtaining the background level. Further, according to the prior art disclosed in the above-mentioned second publication, the background level obtained by this technology does not correspond to the background level of the area where the marker is drawn on the document. Not exclusively. For example, as shown in FIG. 10 (a), a one-page original includes a light background such as the area 20a and a light background such as the area 20b.
There is a white background such as the area 20c, and when the background level is obtained from the density histogram of the entire page of the original document, if the background level of the area 20a is reached, the area 20b in which the marker 20d is drawn and The background level of 20c is different from the obtained background level.

In such a case, if the marker-removed portion of the image output after the marker 20d is removed is replaced with the background level of the area 20a, the marker-removed portion of the image output is as shown by 20e in FIG. , Regions 20b and 20c
However, there is a problem that the image output becomes unnatural because the density is different from the background. An object of the present invention is to eliminate the above-mentioned problems of the prior art, and to provide a marker erasing method and apparatus capable of obtaining an image output in which there is no difference or a small difference between the density of a marker removed portion and the density of peripheral pixels. To provide.

[0005]

In order to achieve the above object, the present invention provides a marker erasing method for erasing a marker from a multi-valued image input signal, wherein n × m pixels ( n and m are both positive integers, at least one of which is an integer of 2 or more) is sequentially cut out, and one pixel at a predetermined position of the n × n pixels is set as a target pixel, and the density of the peripheral pixels of the target pixel is the marker density. The background level of the target pixel is obtained from the sum of the number of pixels smaller than the lower limit value and the density of the pixel, and the background level is obtained when the number of pixels smaller than the lower limit value of the marker density is a predetermined number or more. If the level is selected and the background level of the pixel of interest immediately before is selected when the number is smaller than the predetermined number, the marker erase position is set to the selected background level. The first feature is that the replacement is performed. In addition, a marker signal is detected from the image input signal during the pre-scan, a marker signal is thickened during the main scan to specify a region where the marker should be erased, and whether or not the pixel of interest is on the marker. When it is on the marker, when the target pixel is included in the area to be erased, the target pixel is replaced with the selected background level, and when not included, the target pixel is output. The second feature lies in the fact that

Further, a means for sequentially cutting out n × m pixels from the image input signal and a target pixel are excluded (n × m−1).
Means for comparing whether or not the density of each of the pixels is smaller than the lower limit value of the marker density, and the number of pixels of which the density of the (n × m−1) pixels is smaller than the lower limit value of the marker density. And a density of the density and dividing the sum of the density by the number to obtain a background level, and a density of the (n × n−1) pixels from a lower limit value of the marker density. Means for determining whether the number of small pixels is larger or smaller than a predetermined number, and the means for determining when the density is smaller than the lower limit value of the marker density and the number of pixels is larger than the predetermined number. A third feature is that a means for selecting a background level and selecting the background level of the immediately preceding pixel of interest when the level is small is provided.

According to the first feature, the target pixel in the n × m pixels is a point on the marker if there are a predetermined number or more of pixels at the background level or higher around the target pixel. At this time, the surrounding background level is substituted, and conversely, when the number of pixels equal to or higher than the background level is smaller than the predetermined number, the background level of the immediately preceding target pixel is substituted. Therefore, the density of the pixel after the marker is removed is replaced with the background level in the vicinity of the marker, and it becomes possible to obtain an output image from which the marker is removed without a feeling of strangeness. According to the second feature, even if a mechanical shift occurs between the prescan and the copy scan, the shift can be absorbed and the marker can be surely removed. When the target pixel has the same density as the marker and the target pixel is included in the area where the marker should be erased, the target pixel is replaced with the background level, but the target pixel is included. Not replaced at background level when not. Therefore, the problem that effective image information having the same density as the marker is replaced with the background level is eliminated.

According to the third feature, by comparing whether or not the density of each of the (n × m−1) pixels excluding the pixel of interest is smaller than the lower limit value of the marker density,
It is possible to obtain the number of pixels having a density smaller than the lower limit value of the marker density out of the (n × m−1) pixels. Further, the background level can be obtained by calculating the sum of the densities of pixels whose density is smaller than the lower limit of the marker density and dividing the sum of the densities by the number. Then, it is determined whether the density of the (n × m−1) pixels whose density is smaller than the lower limit value of the marker density is larger or smaller than a predetermined number, and the density is the lower limit of the marker density. When the number of pixels smaller than the value is larger than the predetermined number, the background level obtained by the means is selected, and when the number is smaller, the background level of the pixel of interest immediately before is selected. As a result, it is possible to obtain an image output in which there is no difference or a small difference between the density of the marker-removed portion and the density of the peripheral pixels.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the outline of the overall configuration of an embodiment of the present invention. In the figure, a marker recognition circuit 1 discriminates three areas on the marker (area where the marker is drawn), inside the marker (area surrounded by the marker) and outside the marker from the image data of the pre-scanned document. To do. The page memory 2 is a memory for accumulating the recognition result of the marker recognition circuit 1 for one page of the original document, grasps the original document as two-dimensional coordinates, and stores the recognition result of the area corresponding to each coordinate. FIG. 5A is a conceptual diagram of data stored in the page memory 2, and 5a is data representing the marker upper area. The page memory control circuit 3 of FIG. 1 controls writing and reading of data to the page memory 2 and control of an address. The marker erase signal generation circuit 4 takes the logical sum of the data written in the page memory 2 and the data read in advance, and extends the result in the main scanning and sub scanning directions to thicken the marker signal. Operation to generate a marker erase signal.

Next, the first delay circuit 5a is composed of, for example, two line buffers, temporarily stores the image data of two lines, and parallelizes the data of one pixel for each three lines. To the peripheral pixel level calculation circuit 6. The number of line buffers is not limited to two. The second delay circuit 5b is composed of, for example, one line buffer, and has the background level signal OUT1 output from the peripheral pixel level calculation circuit 6.
Is delayed by one line. The peripheral pixel level calculation circuit 6
Calculates the peripheral pixel level, that is, the background level for one target pixel among 3 × 3 pixels, and outputs it as OUT1. The input image level recognition circuit 7 determines whether or not the pixel of interest is a pixel on the marker. The timing signal generation circuit 8 outputs an L (line) START signal (see FIG. 8) indicating the beginning of each line. The output image selection circuit 9 selects the background level signal OUT1 based on the marker erasing signal when the target pixel is a pixel on the marker, and selects and outputs the target pixel when the target pixel is not the pixel on the marker. To do. The output image selection circuit 9 outputs image data in which the marker is removed and the background-level image is replaced in the marker removed portion.

FIG. 2 is a block diagram showing a specific example of the delay circuits 5a and 5b, the peripheral pixel level calculation circuit 6, the input image level recognition circuit 7 and the output image selection circuit 9 of FIG. The first delay circuit 5a has line buffers 61 and 62 for delaying the input image data and outputs image data for 3 lines (n, n + 1, n + 2 lines). The second delay circuit 5b outputs the background level signal OUT1 output from the peripheral pixel level calculation circuit 6.
Is composed of a line buffer 63 for delaying by one line.

The peripheral pixel level calculation circuit 6 is composed of a peripheral pixel number / average density level calculation circuit 64 and a background level selection circuit 65. The peripheral pixel number / average density level calculation circuit 64 outputs the number of background pixels ADD1 around the pixel of interest and the average density level DIV1 of the background pixels. Further, the background level selection circuit 65 selects the average density level DIV1 when the number of background pixels ADD1 is larger than a predetermined number, and when the background pixel number ADD1 is smaller than the average density level DIV1, selects the background level for the pixel of interest in the previous line or one pixel before. Select and output. Details of the peripheral pixel number / average density level calculation circuit 64 will be described later with reference to FIG. 3, and details of the background level selection circuit 65 will be described later with reference to FIG.

The input pixel level recognition circuit 7 is composed of comparators 101 and 102 which form a window comparator and an AND circuit 103, and the pixel of interest output from the peripheral pixel number / average density level calculation circuit 64. S9
It is determined whether or not is a pixel on the marker. The output image selection circuit 9 has an AND circuit 104 that receives the output S103 from the input pixel level recognition circuit 7 and the marker erase signal from the marker erase signal generation circuit 4, the target pixel S9, and the peripheral pixel level calculation. With the background level OUT1 from the circuit 6 as an input, the AND circuit 1
Multiplexer 105 having output signal 04 as selection signal
It is composed of

Next, the structure and operation of a specific example of the peripheral pixel number / average density level calculation circuit 64 will be described with reference to FIG. The circuit shown in the figure operates in synchronization with a clock (not shown). A of comparators 81, 82 and 83
The terminal has a threshold value Thmin which is the lower limit value of the marker density.
To enter. 3 output from the first delay circuit 5a
Each pixel of the line data is temporarily flip-flop (hereinafter abbreviated as FF) 8 in synchronization with the first clock.
4, 85 and 86, then the comparator 8
Input to the B terminals of 1, 82 and 83. The first comparator 81 compares the pixel on the n-th line with the threshold value Thmin, outputs a signal of 1 if A ≧ B, and outputs a signal of 0 if A <B. Second and third comparators 82 and 8
3 also operates in the same manner. When the second clock is input, the FFs 813, 814 and 815 latch the output signals of the comparators 81, 82 and 83, respectively, and the pixels latched by the FFs 84, 85 and 86 are fed to the FF 87, Shifted to 88 and 89. Further, the FFs 84, 85 and 86 include
The second pixel of each of the three lines of data is latched and then compared with the threshold Thmin by the comparators 81, 82 and 83.

When the third clock is input, FF8
16 and 817 latch the data latched in the FFs 813 and 814, respectively, and the FFs 813, 814 and 815 respectively compare the comparators 81, 82 and 83.
Is latched. The pixels latched in the FFs 87, 88 and 89 are respectively FF81.
0, 811, and 812, the FF 84,
The pixel latched by 85 and 86 is the FF8.
Shifted to 7, 88 and 89. Also, the FF8
The third pixel of the data of the three lines is latched at 4, 85, and 86, respectively, and then compared with the threshold value Thmin by the comparators 81, 82, and 83. Hereinafter, when the fourth, fifth, ... Clocks are input, the same operation as described above is repeated. Further, in synchronization with the clock, the FF 812 outputs the target pixels S9 one by one to the input pixel level recognition circuit 7.

The first adder circuit 826, the second adder circuit 827, and the divider circuit 828 operate in synchronization with the clocks. The first adder circuit 826 determines the threshold Th for eight pixels around the target pixel S9.
Calculate how many pixels have density less than min. Therefore, the number of peripheral pixels having a density smaller than the marker density, that is, the number ADD1 of pixels at the background level is output from the first addition circuit 826. On the other hand, the second adder circuit 827 has eight pixels around the target pixel S9,
The densities of pixels having a density equal to or lower than the threshold Thmin are added. The result of this addition is ADD2. Division circuit 828
Calculates ADD2 / ADD1. The ADD2 / AD
The calculation result of D1 is the threshold value Thmin of the target pixel S9.
The average level DIV1 of the peripheral pixels having the following densities is obtained. Note that, in the above example, 3 × 3 pixels are sequentially cut out from the image input signal, but the present invention is not limited to this, and n × m pixels (n and m are both positive integers, at least one of which is 2 or more). May be sequentially cut out.

Next, the structure and operation of a specific example of the background level selection circuit 65 will be described with reference to FIG. The circuit shown in the figure operates in synchronization with a clock (not shown). For the multiplexer 91, for example, the time for three pixels from the beginning of the line is at H level, and after that, L
The line head signal LSTART of the level is input as a selection signal. The output signal OUT1 of the background level selection circuit 65 is input to the A terminal, and the signal S61 one line before the output signal OUT1 is input to the B terminal.
Then, the multiplexer 91 selects the B terminal when the line head signal LSTART is at the H level, and selects the A terminal when it is at the L level. That is, 3 from the beginning of the line
The signal S61 of one line before is selected until the pixel, and then the immediately previous output signal OUT1 is selected. The FF 93 delays the output signal S91 of the multiplexer 91 by one clock and outputs it to the A terminal of the multiplexer 96 in synchronization with the clock. Further, the FF94 is the average level DIV.
1 is delayed by 1 clock and is output to the B terminal of the multiplexer 96 in synchronization with the clock.

The comparator 92 compares the peripheral pixel number ADD1 having a density smaller than the marker density with a predetermined reference pixel number count value, for example, 4, and if A ≧ B,
For example, the signal S94 of H level is output. The FF 95 delays the signal S95 by one clock and outputs it to the S terminal of the multiplexer 96 in synchronization with the clock. From the Z terminal of the multiplexer 96, the signal of the A terminal is selected when the signal S95 is at the L level, and the signal of the B terminal is selected when the signal S95 is at the H level. Therefore, the multiplexer 9
From the Z terminal 6 of FIG. 6, when the pixel number ADD1 having a density equal to or lower than the threshold value Thmin is smaller than the reference pixel number count value, the number of background pixels is small. On the contrary, when ADD1 is larger than the reference pixel number count value, the number of pixels serving as the background is large, so the background level obtained from the peripheral pixels of the target pixel is output as OUT1.

Next, the operation of the present embodiment will be described. First, a document with a marker is prescanned. The image data obtained by the pre-scan is input to the marker recognition circuit 1 of FIG. 1 and is discriminated into three areas, that is, above the marker, inside the marker, and outside the marker. The result of this determination is stored in the page memory 2. FIG. 5A shows the page memory 2
5a is a conceptual diagram of the data stored in FIG. 5, and 5a indicates a marker signal.

Next, when the prescan is completed, a copy scan for performing a predetermined editing function based on the marker recognition data is started. In the copy scan, the original is read again. At this time, the marker recognition circuit 1 does not operate, and the page memory control circuit 3 reads the data from the page memory 2 and sends it to the marker erase signal generation circuit 4. The page memory control circuit 3 sends the preread data of the page memory 2 and the normal read data to the marker erase signal generation circuit 4. Here, the prefetch data means the data shown in FIG.
5b, the above-marker signal 5a is pre-read by 1 bit in the main and sub-scanning directions, and as a result, the above-marker signal 5a is one pixel in the diagonally upper left 45 ° direction. The image is shifted by a minute. The marker erasure signal generation circuit 4 includes the marker signal 5a and the preread data 5b.
And are logically ORed, and then the result of the logical OR is thickened upward or downward or both directions and left or right or both directions. FIG. 5 (c) is a thickened version of the OR-processed data of FIG. 5 (b).

The reason for performing the above processing is that the marker recognition is performed by the prescan and the marker erasing is performed by the copy scan, so that a mechanical shift always occurs during the two scans of the prescan and the copy scan. If this deviation is large, it may not be possible to delete the marker on the original when erasing the marker.Therefore, in order to absorb the deviation, a thicker marker deletion signal is generated and the marker should be deleted using this signal. I have to.

Next, the operation of the main part of this embodiment during the copy scan will be described. Now, it is assumed that there is image data as shown in FIG. The numbers in the figure show an example of the density of each pixel, and the density of the marker is 128.
Therefore, the area on the marker is the shaded area in FIG. Also, n lines of image data, n
It is assumed that the +1 line and the n + 2 line are as illustrated. The threshold value Thmin in FIG. 3 is assumed to be Thmin = 128.

Now, suppose that at clock T1, the leading three pixels of the n, n + 1 and n + 2 lines shown in FIG. 7A are latched by the FFs 84, 85 and 86 of FIG. The output ADD1 of the first addition circuit 826 becomes ADD1 = 8, and the output DID of the division circuit 828 is
1 becomes DIV1 = 3. In addition, in the present embodiment, FIG.
As is clear from the target pixel S9, the last pixel of the 3 × 3 pixels is set as the target pixel. In the case of FIG. 7A, the pixel X having the density of 8 of the last pixel of 3 × 3 pixels is the target pixel. Further, it is assumed that the data of the margin on the left side of the head of the line is image data of zero density. Next, at the clock T2 advanced by one clock, n, which is shown in FIG.
The top three pixels of the n + 1 and n + 2 lines are shifted to the FFs 87, 88 and 89 in FIG. 3, and the second pixel from the top is latched to the FFs 84, 85 and 86. At this time, ADD1 = 7 and DIV1 = 5.

At the clock T3, nine pieces of image data as shown in FIG. 3C are converted into FFs 84 to 89 and 810 to FF8 in FIG.
12 will be latched, ADD1 = 5, DIV
1 = 11. At clock T4, as shown in FIG. 3D, nine pixels shifted right by one pixel are shown in FIG.
Will be latched by FFs 84 to 89 and 810 to 812, and ADD1 = 3 and DIV1 = 16. At clock T5, as shown in FIG.
The nine pixels shifted to the right of the pixel are FFs 84 to 8 in FIG.
9, 810 to 812 will be latched and ADD
1 = 3 and DIV1 = 16. Hereinafter, the same operation is performed, but the description is omitted.

Next, the operation of the background level selection circuit 65 of FIG. 4 will be described with reference to the timing chart of FIG. The timing signal generating circuit 8 has a clock T
Timing signals LSTART are output from 1 to T3 at H level and after clock T4 at L level. Then, the output signal S91 of the multiplexer 91 is the clocks T1 to T1.
During the period of 3, the background level of the peripheral pixels of the corresponding pixel on the previous line is set, and after the clock T4, the background level of the peripheral pixels of the immediately preceding target pixel is set. DIV of FIG.
1 and ADD1 are the values obtained in FIG.

On the other hand, the comparator 92 compares the ADD1 input to the A terminal with the reference pixel number count value, for example, 4 and, if A ≧ B, the H level signal, and if A <B, the L level signal. Outputs S94. The multiplexer 96 outputs the signal S
A terminal A or B is selected by a signal S95 obtained by delaying 94 by one clock. That is, when the signal S95 is at the H level, the B terminal is selected, and the signal S93, that is, the background level of the peripheral pixel of the target pixel is selected. The A terminal is selected. Select the background level of the pixel. That is, if four or more of the eight peripheral pixels of the target pixel are less than or equal to the lower limit density of the marker, the background level is obtained from the peripheral pixels of the target pixel, and conversely, if less than four,
The background level one line before the target pixel or immediately before the target pixel is obtained. Therefore, the output signal OUT1 of the multiplexer 96 is as shown in FIG.

Next, the input image level recognition circuit 7 of FIG. 2 judges whether the target pixel S9 is between the marker upper limit threshold and the marker lower limit threshold or is outside these values. Then, the result is output to the output image selection circuit 9 as the signal S103. Further, the target pixel S9 is input to the A terminal of the multiplexer 105 of the output image selection circuit 9. S of the multiplexer 105 of the output image selection circuit 9
An (H) level signal S103 indicating that the pixel of interest is on the marker is input from the input image level recognition circuit 7 to the (selection) terminal.
Is input, a marker erase signal is input through the AND circuit 104. When the marker deletion signal is input, the multiplexer 105 selects the B terminal and outputs the background level OUT1 output from the peripheral pixel level calculation circuit 6 as the image data output VDOUT.
On the other hand, the input image level recognition circuit 7 outputs an L level signal S10 indicating that the pixel of interest is inside or outside the marker.
When 3 is input, the multiplexer 105 selects the A terminal and outputs the pixel of interest as the image data output VDOUT.

As described above, according to the present embodiment, the background replaced with the position where the marker is removed from the original is created from the peripheral pixels of the marker, so that the density of the marker removed portion of the image output is generated. It is possible to reduce the difference between the densities of the peripheral pixels and the peripheral pixels, and it is possible to obtain an image output without a sense of discomfort. It should be noted that although the above embodiment has been described with a hardware configuration, the present invention is not limited to this, and it goes without saying that it can be implemented by software processing.

[0029]

According to the first aspect of the present invention, the pixel after the marker is removed can be replaced with the background level around the pixel. Therefore, the density of the marker removed portion and the density of the peripheral pixel can be It is possible to obtain an image output with no difference or a small difference. Also because of this,
High-quality marker removal processing can be performed. Claim 2
According to the invention, even if a mechanical shift occurs between the prescan and the copy scan, the shift can be absorbed and the marker can be surely removed. Further, even if the image data includes information having the same density as the marker, the image data is not erroneously detected as a marker and is not removed, so that highly reliable marker removal processing can be performed. According to the invention of claim 3, in addition to the effect possessed by the invention of claim 1, it can be realized with a simple and inexpensive structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the present embodiment.

FIG. 3 is a block diagram showing a configuration of a specific example of a peripheral pixel number / average density level calculation circuit of FIG.

4 is a block diagram showing a configuration of a specific example of the background level selection circuit of FIG.

FIG. 5 is a diagram showing an outline of marker recognition, marker prefetching processing, and marker thickening processing.

FIG. 6 is a diagram showing an example of image data used to describe the operation of the present embodiment.

FIG. 7 is a diagram showing image data used to explain the operation of the peripheral pixel number / average density level calculation circuit of FIG. 3;

8 is a timing chart of signals of a main part of the background level selection circuit of FIG.

FIG. 9 is a block diagram showing an example of a conventional marker removing device.

FIG. 10 is a diagram showing an image output removed by a conventional marker removing device.

[Explanation of symbols]

1 ... Marker recognition circuit, 2 ... Page memory, 3 ... Page memory control circuit, 4 ... Marker erase signal generation circuit, 5a, 5
b ... delay circuit, 6 ... peripheral pixel level calculation circuit, 7 ... input image level recognition circuit, 8 ... timing signal generation circuit, 9
Output image selection circuit, 64 peripheral pixel number / average density level calculation circuit, 65 background level selection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Suzuki 3-7-1, Iwatsuki City, Saitama Prefecture Fuji-Zerox Co., Ltd. (72) Inventor Atsushi Ouchi 3-7-1, Iwatsuki City, Saitama Prefecture Fuji Xerox Co., Ltd. (72) Inventor Koichi Okamura 3-7-1 Fuchu, Iwatsuki City, Saitama Prefecture Fuji Xerox Co., Ltd.

Claims (3)

[Claims] 1. A marker erasing method for erasing a marker from a multi-valued image input signal, wherein n × m pixels (n and m are both positive integers and at least one is an integer of 2 or more) from the image input signal. ) Are sequentially cut out, and one pixel at the predetermined position of the n × m pixels is set as a pixel of interest, and from the sum of the number of pixels whose density is smaller than the lower limit value of the marker density and the density of the pixel, The background level of the pixel of interest is calculated, and if the number of pixels smaller than the lower limit value of the marker density is equal to or more than a predetermined number, the background level is selected. A marker erasing method characterized in that a marker erasing position is replaced with the selected background level by selecting a level. 2. The marker erasing method according to claim 1, wherein a marker signal is detected from an image input signal during a pre-scan, and the marker signal is thickened during a main scan to identify a region where the marker is to be erased. At the same time, it is determined whether or not the pixel of interest is on the marker, and when it is on the marker,
Replacing the pixel of interest with the selected background level when the pixel of interest is included in the region to be erased,
A marker erasing method which outputs the pixel of interest when it is not included. 3. A marker erasing device adapted to erase a marker from a multi-valued image input signal, wherein n × m pixels (n and m are both positive integers and at least one is an integer of 2 or more) from the image input signal. ) Is sequentially cut out, and a means for comparing whether or not the density of each of the (n × m−1) pixels excluding the pixel of interest is smaller than the lower limit value of the marker density, and (n × m−1) ) Means for obtaining the background level by obtaining the number of pixels and the sum of the densities of the pixels whose densities are smaller than the lower limit value of the marker densities, and obtaining the background level by dividing the sum of the densities by the number. Xm-1) means for determining whether the number of pixels whose density is smaller than the lower limit value of the marker density is larger or smaller than a predetermined number, and the density is smaller than the lower limit value of the marker density. If the number of pixels is The marker erasing device further comprises means for selecting the background level obtained by the means when the number is larger than the selected number and selecting the background level of the immediately preceding target pixel when the number is smaller.