JP2777189B2 - Stereoscopic shadow processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional shadow addition processing device in an image processing device.

2. Description of the Related Art In a conventional image processing apparatus, when a character image is input, as a type of image processing, a predetermined direction of the character image,
For example, it is sometimes desired to output an image that gives a three-dimensional effect by adding a shadow in the lower right direction of 45 °.

Here, there is no conventionally known processing device for adding such a stereoscopic shadow, but it is easily conceivable to configure as shown in FIG.

First, an image area determination block 1 is provided which processes input image data to determine the presence or absence of an image, and outputs H when there is an image, and outputs L level when there is no image. Output from the image area determination block 1 (image determination signal)
Line buffers that delay each by one scan line
2a to 2d are provided. In addition, these line buffers
D flip-flops 3a to 3d are provided to delay the image determination signals output from 2a to 2d by one pixel. Here, one D flip-flop 3a is provided for the line buffer 2a, but two D flip-flops 3b ₁ and 3b ₂ are provided for the line buffer 2b, and 3 D flip-flops are provided for the line buffer 2c. One of the D flip-flop 3c ₁ ~3c ₃ is provided,
Four D flip-flops for line buffer 2d
3d _{1-3d 4} is provided. Therefore, the D flip-flop 3a
The output is delayed one scan line, one pixel data from the output of the D flip-flop 3b ₂ is 2 scanning lines, 2
This is data delayed by the number of pixels, and the D flip-flop 3c
The output from the ₃ is the data delayed third scanning lines, 3 pixels, output from the D flip-flop 3d ₄ 4 scan lines,
This is data delayed by four pixels. These D flip-flops 3a, the output from 3b _2, 3c _3, 3d ₄ is input to the NOR gate 4. The output of the NOR gate 4 is input to the NOR gate 5 together with the output from the image area determination block 1. Then, a selector 6 is provided which receives the image data and the shadow data from the shadow data generating means (not shown) and selects and outputs one of the image data and the shadow data according to the output of the NOR gate 5.

The example shown in FIG. 10 is an example in which the length of the shadow to be generated is equivalent to four pixels, and an image exists in any one of the four pixels in the direction of 45 ° in the upper left of the current pixel (that is, the NOR gate 4 has the image). Only when the output is at L level and there is no image at the current pixel (that is, when the output of the image area determination block 1 is at L level), the pixel is determined as a shadow area pixel, and the selector 6 selects and outputs shadow data. Will be.

Problems to be Solved by the Invention However, when a three-dimensional shadow adding apparatus is configured by the method shown in FIG. 10, a line buffer or a D flip-flop is used according to the length of a shadow to be generated (corresponding to four pixels in the example shown in FIG. 10). It is not easy to increase the length of the shadow because it is necessary to increase or decrease the delay means such as a shadow. For example, if the read pixel density is
If the shadow length is 16 mm = 256 pixels at 16 pixels / mm, a line buffer of at least 256 bits is required. Therefore, in the case of the system shown in FIG. 10, it is difficult to inexpensively realize a device capable of increasing the length of the shadow to be generated. In addition, reliability increases as the number of components increases.

Means for Solving the Problems Basically, a shadow area specifying means for specifying a shadow area based on image data input from the image data generating means, a shadow data generating means for generating shadow data, And image data selecting means for selectively outputting to the image data receiving means based on the specified result of the shadow area specifying means. A shadow length data generating means for generating a set value; an image area determining means for determining the presence or absence of an image based on the image data; and a shadow length for delaying data representing the length of the remaining shadow in the main scanning direction and the sub scanning direction. A data delay unit, a shadow length data counting unit that counts data representing the length of the remaining shadow, and a residual shadow counted by the shadow length data counting unit that is delayed by the shadow length data delay unit. Either the data representing the length or the shadow length data generated by the shadow length data generating means is selected based on the determination result of the image area determining means, and the data representing the remaining shadow length for the set value is updated. And a shadow area determining means for determining a shadow area based on the image data and data representing the length of the residual shadow that has been updated.

Further, the image area determining means is configured to determine the presence or absence of an image based on a plurality of image data input from the image data generating means. A data number selection unit for selecting the number of data, wherein the presence or absence of an image is determined based on the image data input from the image data generation unit in accordance with the number of image data selected by the data number selection unit. Configured.

In the case where a shadow is added to an image input from the image data generating means, a shadow area to which the shadow is to be added is specified by the shadow area specifying means, and shadow data indicating what density shadow is to be added. Is generated by the shadow data generating means,
Controlling the image data selecting means according to the result of specifying the shadow area,
If it is a shadow area, the image data is output to the image data receiving means as image data, and if it is not a shadow area, the input image data is output to the image data receiving means as it is.

By the way, when a shadow is added to an image, the shadow is generally obliquely downward with respect to the image. This can be expressed by being decomposed in the main scanning direction and the sub-scanning direction. That is, if an image exists,
This is because if the length of the shadow is taken in the sub-scanning direction, and this is delayed by ± several pixels in the main scanning direction for each sub-scanning, a pixel region in an oblique direction is obtained.

Based on such a premise, first, data representing the length of a shadow to be generated is an arbitrary set value generated by the shadow length data generating means. Then, the presence or absence of an image is determined by the image area determination means based on the input image data. Data representing the length of the remaining shadow is updated by the shadow length data updating means in accordance with the image resulting from this determination. Here, if it is the first time, the data representing the length of the remaining shadow matches the set value. This is moved to the shadow area by delaying it in the main / sub scanning direction by the shadow length data delay means. Such processing is similarly performed for the next sub-scanning line. At this time, the setting value is updated as data representing the length of the remaining shadow for the pixel where the image exists following the previous sub-scanning line. For a pixel having no image on the scanning line, a value obtained by subtracting the length of one pixel from the initially set value is updated as data representing the length of the remaining shadow. Then, delay processing is also performed on the remaining shadow length data. In parallel with such processing, data representing the length of the remaining shadow is counted by the shadow length data counting means, and is used to determine whether there is no data representing the length of the remaining shadow. In this manner, based on the image data, when the update process including the delay process and the count process of the data representing the length of the remaining shadow is performed, the result is a shadow region candidate,
Finally, the shadow area can be specified by excluding the actual image portion based on the image data by the shadow area determination means.

In other words, by focusing on data representing the length of the remaining shadow with respect to the set value of the length of the shadow to be generated, and updating, delaying, and counting this according to the image data, the shadow to be generated as image data is obtained. Irrespective of the length, only the image data of the current pixel of interest need be determined. Therefore, there is no need to delay-hold image data for a plurality of sub-scanning lines over the length of a shadow to be generated as in the related art, and a long shadow can be added to a small-capacity memory.

Further, if the image area determination means determines the presence or absence of an image based on a plurality of image data input from the image data generation means, shadows may be applied to characters, figures, etc. having a small line width, and noise pixels. Can not be added. In particular, the image processing apparatus further includes a data number selection unit for selecting the number of image data for determining the presence / absence of an image. If the presence or absence of an image is determined, the user can select the line width of the image to which the three-dimensional shadow is added, so that the legibility of characters having a small line width can be maintained.

Embodiment A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a basic block diagram configuration of a stereoscopic shadow adding apparatus according to the present embodiment. First, an image area determining means 12 and an image data selecting means 13 to which an image data signal 11 output from a raster image signal input means = image data generating means (not shown) are provided. The image area determining means 12 processes the image data signal to determine the presence or absence of an image for each pixel, and outputs the determination result as an image area signal 14. A shadow length data selecting means 15 and a shadow area determining means 16 to which the image area signal 14 is input are provided.

The shadow length data selecting means 15 constitutes shadow length data updating means 17 for updating data representing the length of the remaining shadow, and data representing the length of the shadow updated according to the image area signal 14. Is output as a shadow length residual value signal 18. More specifically, the shadow length data selection unit 15 selects the shadow length setting value signal 20 output from the shadow length data generation unit 19 when the image area signal 14 indicates the image “present”, and In this case, the shadow length residual value signal 22 output from the shadow length data counting means 21 is selected, and the shadow length residual value signal 18 is updated. Here, the shadow length setting value signal 20 output by the shadow length data generating means 19 means "a setting value of a shadow length to be generated".

The shadow length residual value signal output by the shadow length data selection means 15
18 is input to the shadow length data delay means 23. The shadow length data delay unit 23 delays the shadow length residual value signal 18 output by the shadow length data selection unit 15 by a time corresponding to one scanning line ± several pixels, and generates a delayed shadow length residual value signal 24. Output. Here, the reason why the delay time has a width of ± several pixels is that the required delay time varies depending on the direction of the shadow to be generated. The delayed shadow length residual value signal 24 is input to the shadow area determination means 16 together with the shadow length data counting means 21.

The shadow length data counting means 21 outputs the same data when the length of the residual shadow indicated by the delayed shadow length residual value signal 24 is “0” (that is, when the length of the residual shadow is “0”). Is output as a shadow length residual value signal 22, and when the data representing the length of the residual shadow, which is indicated by the delayed shadow length residual value signal 24, is not "0", the shadow length residual value signal is output. A predetermined length is subtracted from the length of the remaining shadow indicated by 24, and data indicating the length of the subtracted remaining shadow is output as a shadow length residual value signal 22.

The shadow area determination means 16 processes the image area signal 14 and the delayed shadow length residual value signal 24, determines whether each pixel is a shadow area, and outputs the result as a shadow area signal 25. is there. More specifically, if the image area signal 14 indicates an image “absent” and the data representing the length of the remaining shadow implied by the shadow length residual value signal 24 is not “0”, the pixel of interest is Is determined to be a shadow area. This shadow area signal 25
Is input to the image data selection means 13.

The image data selecting means 13 outputs the image data signal 11 or the shadow data signal (image data to be generated for a portion determined to be a shadow area) 27 output from the shadow data generating means 26 according to the shadow area signal 25. Either one is selected and output as an image data signal 28 to a raster image signal output means = image data receiving means (not shown) or the like. That is, the image data selection means 13 selects and outputs the shadow data signal 27 when the shadow area signal 25 means “shadow area”, and selects and outputs the image data signal 11 when the shadow area signal 25 means “non-shadow area”. I do.

In this manner, the shadow area identification is performed by the image area determination means 12, the shadow area determination means 16, the shadow length data update means 17, the shadow length data generation means 19, the shadow length data counting means 21, and the shadow length data delay means 23. Means 29 are configured.

According to such a configuration, it is not necessary to delay the image area determination results for a plurality of scanning lines as shown in FIG. 10, and the residual length corresponding to the image data for the shadow length data representing the set shadow length is eliminated. The update, the delay and the counting of the data representing the length of the shadow can be performed, and a long shadow can be added to a small-capacity memory.

In FIG. 1, the delayed shadow length residual value signal 24 output from the shadow length data delay unit 23 is used as the shadow length data counting unit.
The shadow length data signal output from the shadow length data selection unit 15 is input to the shadow length data selection unit 15. The shadow length data signal output from the shadow length data counting means is input to the shadow length data delay means, and the shadow length data signal output from the shadow length data delay means is selected. You may comprise so that a means may input. That is, the direction is opposite to the flow shown in FIG.

Next, a specific example of this embodiment will be described with reference to FIGS.

First, in the operation control of this embodiment, the frame synchronization signal synchronized with the frame of the input / output image data signal
▼, scanning line synchronizing signal synchronized with scanning line ▲ ▼
And a pixel synchronization signal CLOCK synchronized with the pixel.

An 8-bit image data signal IM1 output from an image input device (not shown) is input to an input terminal D of a flip-flop 31. Then, in synchronization with the pixel synchronization signal CLOCK input to the CLK terminal, the Q
An 8-bit image data signal IM2 is output from the terminal.
This image data signal IM2 is input to the input terminal P of the comparator 32 (corresponding to the image area determining means 12) and the input terminal B of the selector 33 (corresponding to the image data selecting means 13).

The comparator 32 is an image data signal input to the P terminal
IM2 is compared with the 8-bit threshold signal TH input to the Q terminal, and the result is It is output as an image area signal IA. Here, the value of the threshold signal TH input to the Q terminal is a threshold for determining the presence or absence of an image in each pixel of the image data signal IM2,
A value corresponding to the density of the document can be selected by a threshold setting switch 34 on an operation unit (not shown). Therefore, the image area signal IA output from the comparator 32 indicates the result of determining whether or not there is an image. In the present embodiment, if the image area signal IA is at the L level, the image is “present”, and if it is at the H level, the image is “absent”. The image area signal IA is connected to the select terminal / B of the selector 35 and a two-input NAND gate.
36 is entered.

The selector 35 corresponds to the shadow length data selection means 15, and selects the 8-bit shadow length setting value signal S4 input to the A terminal when the input of the select terminal / B is at the L level, that is, when the image is "present". When the input of the select terminal / B is at the H level, that is, when the image is "absent", the 8-bit shadow length residual value signal SR1 input to the B terminal is selected, and the 8-bit shadow length residual value is input from the Y terminal. Output as signal SR2. Here, A of selector 35
The value of the shadow length setting value signal SS input to the terminal represents data representing the length of the shadow to be generated, and is set to 0 by the shadow length setting switch 37 (corresponding to the shadow length data generating means 19) of the operation unit.
It can be set to any length from (no shadow) to 255 dots. The shadow length residual value signal SR2 is input to the input terminal Di of the line buffer 38.

The line buffer 38 operates in synchronization with the scanning line synchronizing signal ▲ input to the ▲ terminal and the pixel synchronizing signal CLOCK input to the CLK terminal, and outputs the shadow length residual value signal SR2 input to the Di terminal to one. The signal is delayed by the scanning line and output from the Do terminal as an 8-bit shadow length residual value signal SR3.
As such a line buffer 38, for example, μPD4250
A high-speed line memory 5C (manufactured by NEC Corporation) may be used. The shadow length residual value signal from this line buffer 38
SR3 is input to the D terminal of the flip-flop 39.

This flip-flop 39, together with the line buffer 38, corresponds to the shadow length data delay means 23,
It operates in synchronization with the pixel synchronization signal CLOCK input to the K terminal, and further outputs the remaining shadow length signal SR3 input to the D terminal by 1
Pixel delayed, 8-bit shadow length residual value signal SR from Q terminal
Output as 4. This shadow length residual value signal SR4 is input to the A terminal of the adder 40 and each input terminal of the 8-input OR gate 41.

The adder 40 receives the shadow length residual value signal SR4 input to the A terminal.
And an 8-bit fixed value signal DEC (here, 255) input to the B terminal, and the result is output from the Σ terminal to 8
It is output as a bit shadow length residual value signal SR5. at the same time,
The adder 40 outputs the carry signal CY from the CO terminal.
Each bit of the shadow length residual value signal SR5 output from the adder 40 is input to each gate input terminal of a group of eight 2-input AND gates 42. On the other hand, the other input terminal of each AND gate of the AND gate group 42 has a carry signal CY output from the adder 40.
Is entered. The output signal of each AND gate is a shadow length residual value signal SR1 for the B terminal of the selector 35.

Accordingly, the adder 40 performs an equivalent process by subtracting 1 from the value of the delayed shadow length residual value signal SR4, and the result is AN
It is output from the D gate group 42 and the adder 4
0 and the AND gate group 42 correspond to the shadow length data counting means 21.
When the value of the shadow length residual value signal SR4 is 0 (that is, the data indicating the residual length of the shadow is 0), the carry signal CY output from the adder 40 is at the L level. The value of the shadow length residual value signal SR1 output from the group 42 is also 0 (that is, the data indicating the residual length of the shadow is 0), and no substantial subtraction processing is performed.

On the other hand, the shadow length residual value signal SR4 delayed by 8 bits
The OR processing result of the OR gate 41 to which each of the bits is input is output as a shadow candidate signal SC. This shadow candidate signal SC is at H level unless the value of the shadow length residual value signal SR4 is 0 (that is, the data indicating the residual length of the shadow is 0). The shadow candidate signal SC is input to the NAND gate 36, and corresponds to the shadow area determination means 16 together with the NAND gate 36.

An image area signal IA is input to the NAND gate 36, and when the image area signal IA is at the H level and the shadow candidate signal SC is at the H level, the level becomes L level. That is, this is the case where the image is “absent” and the shadow area is a candidate. In other words, the output signal of the NAND gate 36 indicates whether or not it is the shadow area of the pixel of interest currently being processed, and if it is at the L level, it indicates the shadow area. Therefore, hereinafter, the output signal of the NAND gate 36 is referred to as a shadow area signal SA. This shadow area signal SA
Is input to the select terminal / B of the selector 33.

When the input of the select terminal / B is at the L level, that is, in the shadow area, the selector 33 selects the 8-bit shadow data signal SD input to the A terminal, and the input of the select terminal / B is at the H level, ie, If it is not a shadow area, the image data signal IM2 input to the B terminal is selected, and an 8-bit image data signal IM3 is input from the Y terminal to an image output device (not shown).
Is output to Here, the value of the shadow data signal SD input to the A terminal represents the density of the shadow to be generated, and a shadow density setting switch 43 of the operation unit (corresponding to the shadow data generating means 26)
Can be set to an arbitrary density from 0 (white) to 255 (black).

Also, a two-input AND gate 4 which receives a frame synchronization signal ▲ ▼ and a scanning line synchronization signal ▲ ▼ as inputs.
4 outputs the clear signal ▲ ▼ to the ▲ ▼ terminals of the flip-flops 31 and 39, clears the flip-flops 31 and 39 at the head of the image signal line and the line buffer 38 at the head of the frame of the image signal.
Used for clearing.

FIG. 3 shows a timing relationship among the frame synchronization signal ▼, the scanning line synchronization signal ▼, and the image data signal IM1. As shown in this figure, in the operation of this embodiment, before the valid image data signal IM1 is input, first, the frame synchronization signal ▼ becomes L level. In this case, according to the configuration of FIG. 2, the clear signal ▲ also goes to L level,
1,39 are cleared. Thereby, the image data signal IM2
Becomes 0, the image area signal IA is set to the threshold setting switch 34.
H level regardless of the setting of. Therefore, the selector
35 selects the shadow length residual value signal SR1 and outputs it to the line buffer 38. On the other hand, the clear signal ▲ ▼ also changes the shadow length residual value signal SR4 to 0, so that the carry signal CY becomes L level, and the shadow length residual value signal SR1 output from the AND gate group 42.
Becomes 0. Therefore, 0 is written to the line buffer 38 while the frame synchronization signal ▼ is at the L level.

On the other hand, the frame synchronization signal
Is, as shown in FIG.
The period changes in synchronization with the falling of ▼, and the scanning line synchronizing signal ▲
The line buffer is longer than one cycle of ▼
38 is filled with 0 and cleared. When the frame synchronization signal 信号 changes from the L level to the H level, as shown in FIG. 3, the image data signal of the first line starts to be input.
The image data signals of the next line are sequentially input in synchronization with ▼.

The processing operation of an input image as shown in FIG. 4 (a) will be described with reference to the timing chart of FIG. explain. Here, for the sake of simplicity, it is assumed that the value of each pixel of the image shown in FIG. 4A is 0 for a white portion and 255 for a black portion (image portion). The frame indicates the area of each pixel when the image is sampled in the main and sub scanning directions. The main scanning direction and the sub-scanning direction are the directions shown.

FIG. 5 shows an apparatus having the structure shown in FIG.
The scanning line synchronization signal ▲ when the image shown in
▼, pixel synchronization signal CLOCK, image data signals IM1, IM2
And the relationship between the shadow length residual value signals SR4 and SR2.

First, in this embodiment, as shown in FIG. 5, the scanning line synchronizing signal ▼ changes in synchronization with the fall of the pixel synchronizing signal CLOCK. It is one cycle or more of the synchronization signal CLOCK. Referring to FIG. 5, the frame synchronization signal ▲
When ▼ changes to the H level in synchronization with the falling of the scanning line synchronization signal ▼ (FIG. 3), the image data of the first line of the input image appears in the image data signal IM1. Here, the image data signal IM1 includes the scanning line synchronization signal ▲
The image data D1 of the first pixel in each line appears in synchronization with the change of ▼ to the L level, but the image data D2 of the second pixel appears in the scanning line synchronization signal ▲.
It is a timing synchronized with the first rising of the pixel synchronization signal CLOCK after the rising of ▼. The image data of the third and subsequent pixels appear sequentially in synchronization with the rising edge of the pixel synchronization signal CLOCK.

Here, in the case of the input image of FIG. 4 (a), since there is no image on the first line, the image data signal IM1 on the first line
Are all 0. The value of the image data signal IM2 is a value obtained by delaying the image data signal IM1 by one clock of the pixel synchronization signal CLOCK. Also, the scanning line synchronization signal ▲
While ▼ is at L level, clear signal ▲ as described above
Since ▼ is also at the L level, the value of the image data signal IM2 is 0 during this time. On the other hand, the values of the shadow length residual value signal SR4 of the first line output from the flip-flop 39 are all 0 since the line buffer 38 is cleared by the frame synchronization signal ▼. Further, since the values of the image data signal IM2 on the first line are all 0, the image area signal IA from the comparator 32 is output.
Remains at the H level, and 1
The residual shadow length signal SR2 of the line is 0.

In the case of FIG. 4 (a), since there is no image on the second line,
The second line is not shown in the figure, but the image data signals IM1 and IM2 and the shadow length residual value signal SR are similar to the first line.
4, The values of SR2 are all 0.

Next, the value of the image data signal IM2 of the third line becomes 255 in synchronization with the rising of the fourth pixel synchronization signal CLOCK after the rising of the scanning line synchronization signal ▲ ▼, and becomes the value of the thirteenth pixel synchronization signal CLOCK. It becomes 0 again in synchronization with the rise. That is, the value of the image data signal IM2 on the third line is from the rising of the fourth pixel synchronization signal CLOCK to the rising of the thirteenth pixel synchronization signal CLOCK after the rising of the scanning line synchronization signal ▲ ▼. Between, it is 255. Hereinafter, such a state is abbreviated as, for example, "the value of the image data signal IM2 becomes 255 in a period of 4 to 13 clocks".

On the other hand, the value of the shadow length residual value signal SR4 of the third line output from the flip-flop 39 remains 0.

Here, assuming that the value of the threshold signal TH is set to 128, the image area signal IA from the comparator 32 becomes 4
It goes low during the period of ~ 13 clocks and goes high during the other periods. Accordingly, the value of the shadow length residual value signal SR2 of the third line output by the selector 35 during the period of 4 to 13 clocks is the value SS set by the shadow length setting switch 37, and becomes 0 in other periods. FIG. 5 shows a case where the shadow length set value signal SS by the dilation setting switch 37 is 2. That is, this is a case where the length of the shadow to be generated is two dots.

Next, the processing of the fourth line will be described. The value of the image data signal IM2 on the fourth line becomes 255 during the period of 4 to 14 clocks, and becomes 0 during the other periods. On the other hand, the shadow length residual value signal SR4 of the fourth line output from the flip-flop 39
Is a value obtained by delaying the shadow length residual value signal SR2 of the third line by one clock of the pixel synchronization signal CLOCK. That is, 5-1
It becomes 2 in the period of 4 clocks, and becomes 0 in other periods. The value of the shadow length residual value signal SR2 on the fourth line is 4
The value set by the shadow length setting switch 37 becomes 2 during a period of up to 14 clocks, and becomes 0 in other periods.

The value of the image data signal IM2 on the fifth line is 4 to
It becomes 255 in the period of 7 clocks and the period of 11 to 15 clocks, and becomes 0 in other periods. On the other hand, the value of the shadow length residual value signal SR4 on the fifth line output from the flip-flop 39 is the same as the pixel synchronization signal C
A value delayed by one clock of LOCK, that is, 2 during a period of 5 to 15 clocks, and 0 during other periods. Accordingly, the value of the shadow length residual value signal SR2 of the fifth line becomes L level during the period of the image area signal IA of 4 to 7 clocks and the period of 11 to 15 clocks.
The value set in is = 2. On the other hand, the remaining period is a value obtained by performing a subtraction process on the shadow length residual value signal SR4. That is,
It becomes 1 during the period of 7 to 11 clocks, and becomes 0 during the other periods.

The value of the image data signal IM2 on the sixth line becomes 255 in the period of 4 to 7 clocks and 12 to 15 clocks, and becomes 0 in other periods. On the other hand, the value of the shadow length residual value signal SR4 on the sixth line output from the flip-flop 39 is
A value obtained by delaying the shadow length residual value signal SR2 of the fifth line by one clock of the pixel synchronization signal CLOCK, that is, 2 during the period of 5 to 8 clocks and 12 to 16 clocks, and 1 during the period of 8 to 12 clocks And becomes 0 in other periods. Therefore, the value of the shadow length residual value signal SR2 on the sixth line is 2 during the period of 4 to 7 clocks and the period of 12 to 15 clocks. On the other hand, since the remaining period is a value obtained by performing subtraction processing on the shadow length residual value signal SR4, the period of 7 to 8 clocks and the period of 15 to 16
It becomes 1 during the clock period, and becomes 0 during other periods.

Next, the value of the image data signal IM2 on the seventh line is 4 to
It becomes 255 in the period of 7 clocks and the period of 12 to 15 clocks, and becomes 0 in other periods. On the other hand, the value of the shadow length residual value signal SR4 on the seventh line output from the flip-flop 39 becomes 2 during the period of 5 to 8 clocks and the period of 13 to 16 clocks, and becomes 8 to 9 clocks and 16 to 17 clocks. It becomes 1 in the period, and becomes 0 in other periods. Accordingly, the value of the shadow length residual value signal SR2 on the seventh line becomes 2 during the period of 4 to 7 clocks and the period of 12 to 15 clocks. On the other hand, during the other periods, the shadow length residual value signal SR4 is a value obtained by performing a subtraction process, and thus becomes 1 during the period of 7 to 8 clocks and 15 to 16 clocks, and becomes 0 during the other periods. Become.

The value of the image data signal IM2 on the eighth line is 4 to
It becomes 255 in the period of 7 clocks and the period of 11 to 14 clocks, and becomes 0 in other periods. On the other hand, the value of the shadow length residual value signal SR4 of the eighth line output from the flip-flop 39 becomes 2 during the period of 5 to 8 clocks and the period of 13 to 15 clocks, and becomes 8 to 9 clocks and 16 to 17 clocks. It becomes 1 in the period, and becomes 0 in other periods. Accordingly, the value of the shadow length residual value signal SR2 on the eighth line is 2 during the period of 4 to 7 clocks and the period of 11 to 14 clocks. On the other hand, during the other periods, the shadow length residual value signal SR4 becomes a value obtained by performing a subtraction process, so that it becomes 1 during the period of 7 to 8 clocks and 14 to 16 clocks, and becomes 0 during the other periods. Become.

On the other hand, in the shadow area signal SA from the NAND gate 36, the value of the shadow length residual value signal SR4 is not 0, and the image area signal IA is H
In the case of the level, it indicates that it is determined to be the L level, that is, the shadow area. Here, in the case of FIG. 5, since the image area signal IA becomes H level when the value of the image data signal IM2 is 0, it is determined that the image area signal IA is a shadow area because the shadow length residual This is a case where the value of the value signal SR4 is not 0 and the value of the image data signal IM2 is 0. In FIG.
This condition is satisfied during the period of 7 to 11 clocks on the fifth line, the period of 7 to 12 clocks on the sixth line, the period of 15 to 16 clocks, the period of 7 to 9 clocks on the seventh line, 15 to
The period is 17 clocks, the period of 7 to 9 clocks on the eighth line, and the period of 15 to 17 clocks. Therefore, in these periods, the shadow data signal SD is selected, and in other periods, the image data signal IM2 is selected and output by the selector 33. Here, it is assumed that the shadow data signal SD is set to 128 by the shadow density setting switch 43.

In the above example, the processing up to the eighth line of the input image in FIG. 4A is described, but the same processing is performed for the ninth and subsequent lines.

FIG. 4B shows the result of applying the above-described processing to all the images shown in FIG. In FIG. 4 (b), the shaded area indicates the shaded area, and the pixel value is 128. Pixels in the white part are 0,
The number of pixels in the black part (image part) is 255, and FIG.
Remains. As shown in the shadowing result, a three-dimensional shadow having a length of 2 dots set by the shadow length setting switch 37 in the direction of 45 ° to the lower right in the drawing at the density set by the shadow density setting switch 43 It can be added.

In the case of the configuration shown in FIG.
And the flip-flop 39 delays the time by one scan line plus one pixel, so that a shadow is added in the direction of 45 ° at the lower right. However, the order of the line buffer 38 and the flip-flop 39 is changed. By connecting flip-flops in multiple stages, a time delay of one scanning line ± several pixels can be obtained, and a shadow directed in a direction other than the lower right 45 ° direction can be obtained. Further, the delay time may be variable so that the direction of the shadow to be added can be selected.

In FIG. 2, since the input image signal is multi-valued data, a comparator 32 and a threshold setting switch 34 for determining the presence or absence of an image are required. If the data is binary data from the beginning, the comparator 32 and the threshold setting switch 34 become unnecessary. Also,
When the input image signal is binary data, the number of bits of the selector 33 is reduced, so that it is more advantageous that the shadow data signal SD is also binary data. The shadow data signal in this case
SD is not a fixed value by the shadow density setting switch 43 as shown in FIG. 2, but a signal having a periodicity which can be obtained by counting the pixel synchronization signal CLOCK, the scanning line synchronization signal ▲ ▼, etc. Good.

Although the configuration example in FIG. 2 assumes a case where a three-dimensional shadow is added to a monocolor image, the three-dimensional shadow addition processing device according to the present invention is also applicable to a case where a three-dimensional shadow is added to a full-color image. Applicable.

In the case of FIG. 2, the 8-bit shadow length residual value signal is 1
A shadow up to 255 dots in length can be generated simply by delaying the scanning line by one pixel, so the addition of a long stereoscopic shadow can be realized at low cost using a small-capacity memory. it can.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to the drawings.

In general, when a three-dimensional shadow is added to a character or graphic image with a small line width, the original image is hidden by the added shadow and becomes difficult to read. Here, in the case of the above embodiment, since the presence or absence of an image is determined based on only the image data of one pixel of interest, a shadow is added even for a thin character image with a width of one dot, for example. . Further, in the case where noise (generally in the form of dots) is included in the input image data, a three-dimensional shadow is added to such a noise image, and the noise is enlarged. As a result, the output image becomes more dirty. That is, the three-dimensional shadow addition processing apparatus of the present embodiment is, for example, a digital copier including a scanner 46 having a document table 45, an image processing unit 47, and a printer unit 48 as schematically shown in FIG. When a document set on the document table 45 is read by the scanner 46 and is output as image data, dirt or the like in the document may be mixed as a noise image. The above problem may occur. Such a noise image can be removed by a noise removal process before being input to the image area determination means, but it is not preferable because thin lines and the like in the character image are also erased at the same time.

Thus, in the present embodiment, the configuration of the image area determination unit 12 is devised so that the presence or absence of an image is determined based on not only one image data but also a plurality of image data.
For example, a three-dimensional shadow is not added to a thin line image or the like.

First, FIG. 7 shows a timing control circuit 50, not shown in FIG. 2, etc., an image data generating means 51, and an image data receiving means 52. Timing control circuit 50
Is the frame synchronization signal ▲, as in the previous embodiment.
▼, a line synchronization signal ▲ ▼ and a pixel synchronization signal CLOCK are output as shown in FIG. 8 to control the operation timing of the circuit shown in FIG. Image data generating means 51
Outputs a raster-type image data signal IM1 in synchronization with the signal as shown in FIG. In the present embodiment, the image data signal IM1 is 8 bits and has 256 gradations (dark: 255 to light: 0). This image data signal IM1
Is input to the image area determination means 12 together with the selector 33.

The image area determination means 12 of the present embodiment includes a main scanning direction image presence / absence detection circuit 54 and a sub-scanning direction image presence / absence detection circuit 55 together with a comparator 53.

The comparator 53 includes a signal IM2 of the upper 4 bits in the image data signal IM1 and a threshold setting switch 5 for selecting a density level.
This is to compare with the 4-bit density level signal output from 6. The threshold setting switch 56 allows the operator to make 4 bits = 16 settings according to the density of the image to be processed. Therefore, from the comparator 53, when the value indicated by the image data signal IM1 is equal to or larger than 16, 32,..., 240, 256 according to the setting of the threshold setting switch 56, that is, when there is a possibility that there is an image, the H level is set. Otherwise, an L-level signal is output. Further, since the image data signal IM1 does not exceed 256, the output of the comparator 53 in this case is always at the L level.

The main scanning direction image presence / absence detection circuit 54 includes a D flip-flop 57, an OR gate 58, and an AND gate 59. The D flip-flop 57 receives the pixel synchronization signal CLOCK input to the CLK terminal.
, The signal input to the D terminal is delayed by the time corresponding to one pixel and output from the Q terminal. Therefore, when the signal output from the comparator 53 goes to the H level for two or three pixels in the main scanning direction continuously, it is determined that “there is a possibility that an image exists”, and the H level is output from the AND gate 59. Is output. On the other hand, if the signal input from the comparator 53 has a width of one pixel or less in the main scanning direction, it is treated as “no image”.

The sub-scanning direction image presence / absence detecting circuit 55 includes a FIFO memory 60, an OR gate 61, and a NAND gate 62. The FIFO memory 56 operates in synchronization with the line synchronization signal 信号 input to the に terminal and the pixel synchronization signal CLOCK input to the CLK terminal, and delays the signal input to the Di terminal by the time corresponding to one scanning line. Output from the Do terminal. Therefore, when a signal output from the AND gate 59 from the comparator 53 via the main scanning direction image presence / absence detection circuit 54 becomes H level continuously for two or three pixels in the sub-scanning direction, it is determined that “image is present”. Judge, NAND gate
From 62, an L-level image area signal IA is output. on the other hand,
When the signal input from the comparator 53 has a width of one pixel or less in the main scanning direction, it is determined that there is no image, and the image area signal IA becomes H level.

The image area signal IA determined based on the plurality of image data signals IM1 is used, and the subsequent processing is performed in the same manner as in the above-described embodiment. Therefore, even if a character or graphic image having a width of one pixel is input or a noise image having a width of about one pixel is input, it is not determined that there is an image. A three-dimensional shadow is added only to a character image or the like. Therefore, it is possible to prevent a character or the like having a small line width from being difficult to read due to a shadow or to enlarge a noise image by a shadow. For example, as shown in FIG. 9A, when a character image having a width of 2 to 3 pixels and a thin frame-shaped image having a width of 1 pixel are mixed, according to the shadow adding process of this embodiment, As shown in FIG. 3B, a shadow is added only to a character image having a large line width, and no shadow is added to a frame-shaped image having a small line width.

By the way, the readability of a shaded character is related to the balance between the thickness of the character and the length of the shadow to be added. In this regard, according to the above-described embodiment, the length of the shadow to be added can be selected by the shadow length setting switch 37. However, if the length of the shadow to be added is set to be long along with the thick character image, the relatively thin character image Readability tends to decrease relatively.

In this regard, in this embodiment, the image area determination means 12 includes a pixel number selection switch 63 serving as data number selection means, and this pixel number selection switch 63 is connected to the OR gates 58 and 61.
The number-of-pixels selection switch 63 can be switched by the operator according to the line width of the image to be processed. Can be selected. Specifically, when the number-of-pixels selection switch 63 is set to the OFF state, the OR gates 58 and 61 are always set to H level.
Since the level is output, if the output of the comparator 53 or the AND gate 59 continuously goes to the H level for two pixels, it is treated as "image present". If the number-of-pixels selection switch 63 is set to the ON state, it will not be treated as "image present" unless it goes high for three consecutive pixels.

Therefore, according to the present embodiment, the operator can select the line width of the image to which the three-dimensional shadow is to be added, and can add the three-dimensional shadow without impairing the readability of an image such as a character having a small line width. Can be.

In FIG. 7, the configuration and operation of the other parts are the same as those in FIG. However, the shadow length setting switch of this embodiment
In 37, the length of the shadow to be generated is 0, 16, 32, ..., 240 pixels
There are 16 ways. The shadow density setting switch 43 of this embodiment operates in conjunction with the threshold setting switch 62, and can take the values of 8, 16,..., 120. That is, the shadow data signal SD is configured to have a value that is half the threshold value set by the threshold setting switch 62. Therefore, a clear difference occurs between the value of the image part and the value of the shadow part to be added, and a three-dimensional shadow can be added without deteriorating the readability of the image.

In the present embodiment, the line width of the image to which a shadow is added is mainly
Although only two or three consecutive pixels in the sub-scanning direction have been described as an example, generally, the present invention can be applied to an even larger pixel width by changing the circuit configuration of the image area determining unit 12.

Advantageous Effects of the Invention Since the present invention is configured as described above, the remaining shadow length is set based on the setting value of the shadow length by the shadow length data generating means and the image data of the current pixel of interest. It is sufficient to update, delay, and count data to indicate whether or not it is a shadow area. Even when a long shadow is generated, update, delay, and count the remaining shadow length by that much. This can be dealt with by performing the processing, so that it is not necessary to delay-hold the image area determination result of the image data itself for a plurality of sub-scanning lines as in the related art, and a small-capacity memory is sufficient. The image area determination means determines whether or not an image is present based on a plurality of pieces of image data, and provides a process of whether or not to add a shadow.
It does not add shadows to graphic images or noise images, does not impair the readability of the images or enlarges the noise images, and has a data number selection means. For example, the line width of a character or the like to which a three-dimensional shadow is added can be selected by the operator, and a balanced three-dimensional image and shadow can be added.

[Brief description of the drawings]

1 to 5 show a first embodiment of the present invention. FIG. 1 is a conceptual block diagram, FIG. 2 is a block diagram showing a concrete example, FIG. 3 is a timing chart, 4th
FIG. 5 is an explanatory diagram showing an example of an image before and after image processing, FIG. 5 is a timing chart, FIGS. 6 to 9 show a second embodiment of the present invention, and FIG. FIG. 7 is a block diagram, FIG. 8 is a timing chart, FIG. 9 is an explanatory diagram showing an image example before and after image processing, FIG.
FIG. 1 is a block diagram showing a conventional example. 11 ... input image data, 13 ... image data selection means, 16
... shadow area determination means, 17 ... shadow length data updating means, 19 ...
... Shadow length data generating means, 21 ... Shadow length data counting means, 23
…… Shadow length data delay means, 26 …… Shadow data generation means, 27
... shadow data, 29 shadow area specifying means, 33 image data selecting means, 35 shadow length data updating means, 36, 41 shadow area determining means, 37 shadow length data generating means, 38 , 39 ……
Shadow length data delay means, 40, 42 ... shadow length data counting means, 4
3 ... shadow data generating means, 51 ... image data generating means, 5
2 ... Image data receiving means, 63 ... Data number selecting means

Claims (3)

(57) [Claims] 1. A shadow length data generating means for generating a set value of a length of a shadow to be generated, an image area determining means for determining the presence or absence of an image based on image data input from the image data generating means, Shadow length data delay means for delaying data representing the length of the shadow in the main scanning direction and sub-scanning direction, and shadow length data counting means for counting data representing the remaining shadow length;
Either data representing the length of the remaining shadow delayed by the shadow length data delaying means and counted by the shadow length data counting means or shadow length data generated by the shadow length data generating means is used as the image. Shadow length data updating means for selecting data based on the determination result of the area determining means and updating data representing the length of the remaining shadow with respect to the set value; and A shadow area determining means for determining a shadow area based on the data to be represented; a shadow data generating means for generating shadow data; and specifying one of the image data and the shadow data to the shadow area determining means. A three-dimensional shadow addition processing device comprising: image data selection means for selectively outputting to an image data receiving means based on a result specified by the means. 2. The three-dimensional shadow addition processing device according to claim 1, wherein said image area determining means determines the presence or absence of an image based on a plurality of image data input from the image data generating means. 3. An image area determining means having a data number selecting means for selecting the number of image data for determining the presence or absence of an image, and generating image data according to the number of image data selected by the data number selecting means. 3. The three-dimensional shadow addition processing device according to claim 2, wherein the presence or absence of an image is determined based on image data input from the means.