JPH09284178A - Intermittent operation delayed locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid loss of synchronization caused by fading for a long time and to reduce the power consumption in the case of configuration of a synchronization circuit for the direct spread spectrum communication system. SOLUTION: A desired wave power discrimination means 212 is provided to an output terminal, a sliding correlation device (SC) 204 takes correlation between a signal delaying an output of a reception section 201 by a time ΔTc and a spread code of a receiver outputted from a spread code generator 211 to detect a level of a synchronized desired wave. When the level is lower than a prescribed level, the operation of a delay circuit 203, SCs 205, 206, level detectors 207, 208 and an adder 209 is stopped to bring the operation of a phase locked loop PLL 210 into a flywheel operation and when the level is higher than the prescribed level, the operation stop is released to activate the PLL 210 normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple access system (DS-CDMA: Direct Sequence Code Divisio).
The present invention relates to improvement of a delay locked loop (DLL: Delay Locked Loop) used for synchronization of spread codes in a direct spread spectrum communication system with n multiple access.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing an example of a conventional delay locked loop. In the figure, 101 is a receiver (RX), 102 and 103 are delay circuits (ΔTc), 10
4, 105 and 106 are sliding correlators (SC),
107 and 108 are level detection circuits, 109 is an adder, 1
Reference numeral 10 is a phase locked loop (PLL), and 111 is a spreading code generator. FIG. 3 is a diagram showing an output example of the sliding correlator SC. The reception signal down-converted to the base band by the reception unit (RX) 101 is delayed by the delay circuit (Δ
Tc) 102 and a sliding correlator (SC) 106. The delay circuit 102 delays the received signal by the time ΔTc.
(However, ΔTc <Tc, Tc is one chip time, and the chip represents one bit of the spread code), and outputs it to another delay circuit 103 and a sliding correlator 104.

On the other hand, if the spreading code phase in the input signal from the receiving unit 101 and the spreading code phase of the receiver from the spreading code generator 111 are synchronized, the SC 106 of FIG. The correlation output is as shown by the arrow. FIG. 3 (a),
The broken lines in (b) and (c) show the autocorrelation function of the spreading code. Since SC has only one multiplier and one integrator, it can take only one point of the autocorrelation function during one symbol time. Therefore, the arrow shown in the figure indicates the SC output.
Here, in FIG. 3A, the phase difference ΔTc between the spreading code phase of the input signal and the spreading code phase of the receiver is + Tc / 2 (where the spreading code phase of the receiver is Tc / 2 rather than the spreading code phase of the input signal).
It is the case of the state of progressing). The output level of SC is
Since the maximum peak occurs only when the spread code phases match, the maximum peak point cannot be obtained in the case of phase error (a).

FIG. 3 corresponds to the conventional circuit of FIG.
The output of SC106 is (a), the output of SC104 is (b), and the output of SC105 is (c). In general, the autocorrelation function (dashed line) of the spread code is symmetrical about the maximum peak point, so that the absolute values (sizes) of the arrows in (a) and (c) are equal. However, since the input signal has a phase fluctuation due to information and a phase fluctuation due to a transmission path fluctuation, in order to remove the influence of rotation due to those phase fluctuations, a positive level (on the vector plane) is detected in the level detection circuits 107 and 108. (Corresponding to the magnitude of the vector).

The adder 109 calculates the difference between these levels, and as a result, outputs one point on the S-shaped curve as shown in FIG. In FIG. 4, the horizontal axis represents the phase shift (difference) and the vertical axis represents the level difference. If there is no deviation between the receiver spread code phase and the input signal spread code phase, the output of the adder 109 becomes 0, and if phase skipping occurs, a negative level difference is obtained. The PLL 110 adjusts the phase of the clock that determines the spread code phase of the receiver based on the result of averaging the level differences obtained from the adder 109.

For example, if the averaging level difference is a positive value (the input spreading code phase leads the receiver spreading code phase), the clock period is shortened and the averaging level difference is negative (the input spreading code phase). Is delayed from the received spread code phase), the clock period is lengthened. This operation is repeated many times and the clock whose phase has been adjusted is output to the spread code generator 111.

The spread code generator 111 outputs the same spread code to the three SCs 104 to 106 in synchronization with the input clock. By this operation, the spread code of the input signal is synchronized with the phase, and the output of the SC 104 can be used to judge the received signal. The above operation is generally performed by DLL (De
It is a known technique called lay locked loop).

[0008]

However, in a fading environment generally occurring in communication lines such as mobile communication, the input signal may drop significantly for a long period of time. In such a case, the reception S / N (Signal power to signal) Noise
power ratio: Received signal power to noise power ratio) deteriorates significantly and is governed by noise power, so it becomes impossible to obtain the correct level difference, resulting in loss of synchronization. . In addition, although power saving is required for portable devices, no consideration has been made in terms of power saving in the related art.

An object of the present invention is to provide an intermittent operation type delay lock loop which alleviates the problem of loss of phase synchronization due to a drop in received signal power over a long period of time, which is a problem of the prior art, and enables power saving. To do.

[0010]

SUMMARY OF THE INVENTION An intermittent operation type delay lock loop according to the present invention comprises a receiver for down converting a received signal from a radio frequency band to an intermediate frequency band or a base band, and an output signal of the receiver for a ΔTc time. (However, ΔTc
<Tc, Tc is a time length of 1 bit of the spread code), a first delay circuit for delaying the output signal of the first delay circuit by ΔTc, and an output of the receiving section. A signal, the output of the first delay circuit, and the second delay circuit.
The first, second, and third sliding correlators for correlating the outputs of the delay circuits with the spreading codes of the receiver, and the levels of the output signals of the first and third sliding correlators. First and second level detection circuits for respectively detecting, an adder for detecting a level difference between outputs of the first and second level detection circuits, a phase error signal output from the adder and flywheel control Flywheel control by inputting a signal and adjusting the phase of the output clock by adding or removing pulses to the clock so as to eliminate the phase error between the spread code phase of the received signal and the spread code phase of the receiver. When a signal is input, a phase-locked loop that ignores the input phase error and keeps outputting the clock immediately before the flywheel control signal is input, Of a spread code generator which continues to output the spread code of the receiver in synchronization with the clock signal from the synchronization loop and the output of the second sliding correlator, and calculates the average level in the received signal. Output a logical value L when the desired wave signal level is low, and output a logical value H when the desired wave signal level is high, and output the second delay circuit, the first and third sliding correlators, and the first delay correlator. Further, the second level detection circuit and the adder are provided with desired wave level determination means for controlling switching between a low power consumption mode including stop of operation and a normal operation mode.

[0011]

2 is a block diagram showing a first embodiment of the present invention. In the figure, reference numeral 201 is a receiving unit that down-converts a received signal from a carrier frequency band to an intermediate frequency band or a base band. 202,2
Reference numeral 03 denotes a delay circuit that delays the received signal by ΔTc time and can be configured by a shift register or the like. Reference numeral 204 denotes a sliding correlator (SC: Sliding) that correlates the output signal of the delay circuit 202 that delays the received signal by ΔTc (Tc: spreading code 1 bit) and the spreading code of the receiver output from the spreading code generator 211. Correlator). If the signal input sequence is x (k), c (k) is the spreading code sequence, and N is the spreading code length, the correlation output R (k) is given by the following equation.

[0012]

[Equation 1]

The SC outputs one point of this R (k). Therefore, if the received signal and the spreading code of the receiver are synchronized, the output of SC204 is R
(0). Reference numeral 205 denotes an SC that correlates the output signal of the delay circuit 203, which is obtained by delaying the received signal by Tc, with the spread code of the receiver. Using equation (1) above and the assumptions, the output of SC 205 is R (-ΔTc). 20
Reference numeral 6 is an SC that correlates the received signal output from the RX 201 with the receiver spreading code without intentional delay. Using equation (1) above and the assumptions, the output of SC 206 is R (+ ΔTc).

Reference numerals 207 and 208 denote SC205 and SC205, respectively.
A level detection circuit for detecting the output level of 206.
Generally, a square circuit is used as the level detection circuit, but an absolute value detection circuit or the like can be used instead. Reference numeral 209 denotes each of the level detection circuits 207 and 20.
8 is an adder for calculating the level difference obtained by 8.

Reference numeral 210 adjusts the phase of the clock that determines the spread code phase of the receiver from the level difference obtained by the adder 209, and when a fly-hole control signal is input, the control is performed regardless of the input signal. Continues to output the clock at the timing immediately before the signal is input (called the flywheel effect) Phase locked loop (PLL: Phase LockedLo)
op). A spread code generator 211 generates a spread code for the receiver in synchronization with an input clock.

Reference numeral 212 is an important part of the present invention, and SC2
04 output power averaged and received desired wave level (power)
Is measured, and if the desired reception wave level falls below the set threshold value, the delay circuit 203, SC 205,
206, level detection circuits 207 and 208, adder 209
To the power save mode, and outputs a control signal that causes the PLL 210 to flywheel operation. When the desired reception wave level is greater than the threshold value, a control signal that ends the power save mode is output. It is a desired wave level determination means that outputs a signal that outputs the signal and that stops the flywheel of the PLL 210.

The operation of the present invention will be described below with reference to FIG. If the desired reception wave level is higher than the set threshold value, the same operation as the known DLL is maintained. Hereinafter, the operation of the configuration of the present invention when the desired reception wave level drops and until the drop state is recovered will be described.

Now, the entire system of FIG. 2 performs DLL operation, and SC
It is assumed that the output 204 is in the state of obtaining the maximum peak point as shown in FIG. In FIG. 5, the average level of the desired reception wave (determined by the desired wave level determination means 212) is plotted on the vertical axis
It is a characteristic example figure which made the horizontal axis the elapsed time. If the transmission line fluctuation is in the state shown in FIG. 5, the threshold value is not exceeded until the 9th symbol time, so the control signal for prompting the transition to the power save mode is not output, but the 10th symbol time is not output. In, the average level value of the desired reception wave is below the threshold value. At this time, the desired wave level determination means 212 determines that each block (delay circuit 203, S) having the power saving mode.
The C205 and 206, the level detection circuits 207 and 208, and the adder 209) are controlled so as to be in the power saving mode, and the flywheel operation is specified in the PLL 210. Here, the power (battery) saving mode means that the power supply is cut off, but it may be a partial cutoff of the power supply depending on the equipment used and the purpose, or the transition to low power operation of each block. May be specified.

When the battery saving mode is activated by the control signal from the desired wave level determination means 212,
The input signal from the adder 209 of the PLL 210 is cut off. However, since the PLL 210 has the flywheel effect as described above, even if the input signal is cut off,
Continues to output the clock in the phase before it was cut off. Therefore, the spreading code generator 211 continues to output the spreading code in the spreading code phase before the input of the PLL 210 is blocked, and the SC
204 continues to correlate with the received input signal. During this time,
Code clock source of transmitter (eg TCXO: Temp
The original DLL operation of tracking the phase of the code clock source of the receiver to the reature Compensated Crystal Oscillator cannot be performed, but generally the relative phase shift of the clock that fluctuates during the fall time of the received power due to transmission line fluctuation is small. .

For example, the spreading rate is 10M.
1 ppm (1 ppm: 10) that can be easily realized as the relative accuracy of the code clock source of the transmitter and the receiver of cps (cps: Chips Per Second, the number of chips per second)
Assuming that the error of one clock occurs in 0,000 clocks) and the level decrease time due to fading is 10 msec, the phase shift generated during that time can be obtained by the following equation.

[0021]

[Equation 2] 10 × 10 ⁶ [cps] × 0.01 [sec] × 10 ^-6 =
0.1 [chip]

That is, even if the desired wave greatly drops due to fading, the error of the relative clock that fluctuates within that time is about 0.1 chip, and it is not necessary to strictly operate the DLL.

When the received signal drops significantly,
Signal power to noise power ratio (S / N)
Since the e power ratio is deteriorated, the output of the adder 209 is dominated by noise power, resulting in loss of synchronization. However, in the present invention, when the received signal drops significantly, , To stop the DLL operation,
The loss of sync problem is resolved.

Next, the restoration of the DLL operation will be described.
When the average level of the desired wave to be received by the desired wave level determination means 212 exceeds the threshold value (13th symbol time in FIG. 5), the desired wave level determination means 212 controls each block to end the power save mode. Further, since the flywheel operation end signal is output to the PLL 210, the DLL operation is restored.

FIG. 6 is a block diagram showing a second embodiment of the present invention. In the figure, reference numeral 601 denotes a receiving unit that down-converts a received signal from a carrier frequency band to an intermediate frequency band or a base band. Reference numeral 602 denotes a sliding correlator (SC) that correlates the received signal with the spreading code of the receiver obtained by delaying the output of the spreading code generator 611 by ΔTc (Tc: spreading code 1 bit).
It is. If the signal input sequence is x (k), c (k) is the spreading code sequence, and N is the spreading code length, the correlation output R (k)
Is given by

[0026]

(Equation 3)

The SC 602 outputs one point of this correlation output R (k). Therefore, if the received signal and the spread code of the receiver are synchronized, the output of SC602 is R (0). Reference numeral 603 is an SC that correlates the received signal with the receiver spreading code that does not intentionally delay the output of the spreading code generator 611. Using equation (2) and the assumption above, the output of SC603 is R (-ΔTc). Reference numeral 604 denotes an SC that correlates the received signal and the signal obtained by delaying the output of the spread code generator 611 by Tc and the spread code of the receiver. Using equation (2) and the assumption above, the output of SC 604 is R (+ ΔTc). 60
Reference numerals 5 and 606 each denote a delay circuit that delays the spread code of the receiver by ΔTc time and can be configured by a shift register or the like.

Reference numerals 607 and 608 denote SC603 and SC603, respectively.
A level detection circuit for detecting the output level of 604.
Generally, a square circuit is used as the level detection circuit, but an absolute value detection circuit or the like can be used instead. Reference numeral 609 denotes respective level detection circuits 607 and 60.
8 is an adder for calculating the level difference obtained by 8.

Reference numeral 610 adjusts the phase of the clock that determines the spread code phase of the receiver from the level difference obtained by the adder 209, and when the fly-hole control signal is input, the control is performed regardless of the input signal. It is a PLL (Phase Locked Loop) that keeps sending out a clock (= flywheel) immediately before a signal is input. A spread code generator 611 generates a spread code for the receiver in synchronization with an input clock.

612, the output of the SC 602 is power averaged to measure the desired reception wave level, and when the desired reception wave level falls below the set threshold value, the delay circuit 6 is provided.
06, SC603, 604, level detection circuit 607, 6
08, the adder 609 is controlled to shift to the power save mode, and the control signal for causing the flywheel operation of the PLL 610 is output, and when the desired reception wave level takes a value larger than the threshold value, the power save mode is set. Is a desired wave level determination means for outputting a control signal for terminating the operation of the PLL 610 and outputting a signal for stopping the flywheeling of the PLL 610.

The operation of the second embodiment of the present invention described above is as follows:
Since the delay relationship between the received signal and the receiver spreading code in the second embodiment is the same as the delay relationship in the second embodiment, the operation is the same as in the first embodiment.

FIG. 7 is a block diagram showing a third embodiment of the present invention. This third embodiment corresponds to the first embodiment shown in FIG.
Instead of the desired wave power determination means 212 of the embodiment of
A C circuit 702 and a comparator 703 are provided. In the figure, reference numeral 701 is a receiving unit that down-converts a received signal from a carrier frequency band to an intermediate frequency band or a base band. Reference numeral 702 denotes an automatic gain control circuit (AG which corrects the amplitude of the received signal to a voltage necessary for signal processing).
C: Automatic Gain Control). 703 is AG
This is a comparator that compares the reception average signal power (reception field strength signal: RSSI) obtained from C702 with a preset threshold value and outputs the comparison result. 704, 705
Is a delay circuit that delays the received signal by ΔTc (Tc: 1 bit of spreading code). 706 receives the received signal by ΔT
c (Tc spreading code 1 bit) Sliding correlator (SC: Correlation between delayed signal and spreading code of receiver)
Sliding Correlator). 707 indicates the received signal as T
c Correlation between the delayed signal and the spreading code of the receiver S
C. Reference numeral 708 is an SC that correlates the received signal with the received spread code without intentional delay. 709,710
Is a level detection circuit that powers the outputs of the SCs 707 and 708, respectively. Reference numeral 711 is an adder for subtracting the levels obtained by the respective level detection circuits 709 and 710.

712 adjusts the phase of the clock that determines the spread code phase of the receiver from the level difference obtained by the adder 711, and when the flywheel control signal is input, the control signal is applied regardless of the input signal. Is a PLL (Phase Locked Loop) that keeps sending out a clock (= flywheel) at a timing immediately before inputting. 713
Is a spreading code generator that generates a spreading code for the receiver in accordance with an input clock.

The operation of the third embodiment of the present invention will be described below with reference to FIG. Since the basic operation is the same as the operation of the first embodiment described above, the AGC 702 provided in place of the desired wave level determination means 212 shown in FIG.
The comparator 703 will be described. In general,
The receiver uses an AGC (Automatic Gain C) so that the received signal level satisfies the level required for signal processing in the subsequent stage.
ontrol: Automatic gain control) function is provided. AGC
Is the total received signal power (RSSI: Received Sig)
The received input signal level is adjusted so that the nal strength indicator) becomes a preset power level. Therefore, since the received signal power averaged by the AGC 702 can be detected, this value is compared with the threshold value by the comparator 703. At this time, since the received signal power also includes noise and interference power, it is necessary to set the threshold level higher than the threshold in the first embodiment. This threshold is set to a different value depending on the system to which the present invention is applied.

The third embodiment differs from the first embodiment in that the DLL operation control is performed using the total received power. This causes a problem that it is more susceptible to noise and interference power than the case where control is performed using a desired wave level having the best S / N. For example, a plurality of mobile stations from the same base station Spread spectrum signal (downlink)
Then, since a constant ratio between the total received power and the desired wave level is held, by multiplying the threshold value by the ratio, it is possible to obtain an effect equivalent to the judgment of the desired wave level.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention. In this embodiment, the AGC 802 is used instead of the desired wave power determination means 612 of the second embodiment shown in FIG.
And a comparator 803. In the figure, RX801, SC804-805, ΔTc807,
808, level detectors 809 and 810, an adder 811,
The PLL 812 and the spread code generator 813 correspond to the same part in FIG. The operations of the AGC 802 and the comparator 803 are the same as the operations of the AGC 702 and the comparator 703 in the third embodiment shown in FIG.

[0037]

【The invention's effect】

(1) Effect of the invention according to the first embodiment The intermittent operation type DLL of the present invention is directed to the loss of synchronization that occurs when the received signal drops significantly and the S / N becomes poor in a fading environment. It is valid. Further, since the DLL operation is not performed during the time when the signal power is greatly reduced, the power consumption can be greatly reduced. Therefore, a remarkable effect can be obtained for the portable mobile terminal. (2) Effect of the invention according to the second embodiment In the second embodiment of the present invention, the spread code of the receiver is delayed instead of delaying the input signal. If not, the number of delay elements can be reduced. As a result, the same effect as that of the first embodiment can be obtained, and further, the circuit scale can be reduced. (3) Effects of the Invention by the Third and Fourth Embodiments The third and fourth embodiments of the present invention require the desired wave level determination means provided in the first and second embodiments. Therefore, the circuit scale and the control algorithm can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a conventional technique.

FIG. 2 is a block diagram of a configuration example showing a first embodiment of the present invention.

FIG. 3 is an example of SC output.

FIG. 4 is an S-curve example diagram.

FIG. 5 is a diagram showing an example of a desired wave average level over time.

FIG. 6 is a configuration block diagram showing a second embodiment of the present invention.

FIG. 7 is a configuration block diagram showing a third embodiment of the present invention.

FIG. 8 is a configuration block diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

101 receiver (RX) 102, 103 delay circuit 104, 105, 106 sliding correlator (S
C) 107, 108 Level detection circuit 109 Adder (subtractor) 110 PLL 111 Spread code generator 201 Receiver (RX) 202, 203 Delay circuit 204, 205, 206 Sliding correlator (S
C) 207, 208 Level detection circuit 209 Adder (subtractor) 210 PLL 211 Spread code generator 212 Desired wave level determination means 601 Receiver (RX) 602, 603, 604 Sliding correlator (S
C) 605, 606 delay circuit 607, 608 level detection circuit 609 adder 610 PLL 611 spreading code generator 612 desired wave level determination means 701 receiver (RX) 702 AGC 703 comparator 704, 705 delay circuit 706, 707, 708 sliding Correlator (S
C) 709,710 level detection circuit 711 adder 712 PLL 713 spreading code generator 801 reception unit (RX) 802 AGC 803 comparator 804, 805, 806 sliding correlator (SC) 807, 808 delay circuit 809, 810 level detection circuit 811 adder 812 PLL 813 spreading code generator

Claims (3)

[Claims] 1. A receiver for down-converting a received signal from a radio frequency band to an intermediate frequency band or a base band, and an output signal of the receiver for a ΔTc time (where ΔTc <T.
c and Tc are delay times of 1 bit of the spread code), a first delay circuit for delaying the output signal of the first delay circuit by ΔTc, and an output signal of the receiving section. And first, second, and third sliding correlators that correlate the output of the first delay circuit and the output of the second delay circuit with the spreading code of the receiver, respectively. First and second level detection circuits that detect the levels of the output signals of the first and third sliding correlators, respectively, and an adder that detects the level difference between the outputs of the first and second level detection circuits The phase error signal output from the adder and the flywheel control signal are input, and pulses are added or removed from the clock so as to eliminate the phase error between the spread code phase of the received signal and the spread code phase of the receiver. Or A phase-locked loop that adjusts the phase of the output clock and, when the flywheel control signal is input, ignores the input phase error and continues to output the clock while holding the phase immediately before the flywheel control signal is input. A spread code generator which receives the clock from the phase locked loop as input and continues to output the spread code of the receiver in synchronization with the clock signal; and calculates an average level of the output of the second sliding correlator. , A logical value L is output when the desired wave signal level in the received signal is low, and a logical value H is output when the desired wave signal level is high, and the second delay circuit, the first and third sliding correlations And a desired wave level determination means for controlling switching between the low power consumption mode including the operation stop and the normal operation mode for the first, second and second level detection circuits and the adder. Intermittent operation delay-locked loop, characterized in that there was e. 2. The output signal of the receiving section is used as one input of each of the three sliding correlators, and the first and second delay circuits are cascade-connected to the output side of the spreading code generator and sequentially. 2. The intermittent delay lock loop of claim 1 configured to delay the receiver spreading code to the other input of each of the three sliding correlators. 3. An automatic gain control circuit inserted and connected between the receiving section and the first delay circuit instead of the desired wave level determination means, and a received electric field strength obtained from the automatic gain control circuit. A comparator for comparing the signal with a predetermined threshold value to determine and output the received signal level is provided, and the output of the comparator is used as the control signal output from the desired wave level determining means. The intermittent operation type delay lock loop according to claim 1 or 2, characterized in that: