JPH09284132A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the phase locked loop(PLL) circuit to generate transmission and reception local signals and to select the frequency at a high speed when the PLL circuit is used for a time division multile access(TDMA) system digital mobile communication equipment having an antenna changeover diversity function. SOLUTION: This circuit is provided with a reference signal generator 1, a 1st frequency divider 2 frequency-dividing a reference signal, a voltage controlled oscillator(VCO) 3, a 2nd frequency divider 4 frequency-dividing the oscillated signal of the VCO 3, a phase comparator 5 comparing output signals of the 1st and 2nd frequency dividers 2-4 to provide a phase difference signal, and two-system of loop filters 8, 9 receiving the phase difference signal to provide an output of a control voltage to the VCO 3. In the case of switching state of the oscillated frequency, the 1st loop filter 8 with more excellent frequency convergence performance is selected in the 2-system of the loop filters and after the frequency is made stable, the 2nd loop filter 9 with excellent low noise performance is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit used in a synthesizer device, and more particularly to a TDMA having an antenna switching diversity function.
It is suitable for application to a (time division multiple access) type digital mobile communication device.

[0002]

2. Description of the Related Art Conventionally, in a TDMA type mobile phone,
Due to the frequency configuration, the relationship between the transmission / reception bandwidth and the demodulation frequency,
In some cases, the reception local signal and the transmission local signal cannot be shared. For this reason, it is necessary to separately generate the local signal for transmission and the local signal for reception, so that a configuration is adopted in which dedicated PLL circuits are provided for each.

[0003]

Therefore, the conventional TD
In the MA type mobile phone, it is necessary to provide dedicated PLL circuits for transmission and reception, respectively, and there is a disadvantage that miniaturization is difficult because the circuit scale becomes large.

The present invention has been made in order to solve such a conventional problem, and it is possible to generate local signals for transmission and reception by one PLL circuit and perform frequency switching at high speed. An object of the present invention is to provide a PLL circuit that can be used.

[0005]

According to the present invention, a reference signal generator for generating a reference signal, a first frequency divider for dividing the reference signal, and voltage control in which the oscillation frequency changes according to a control voltage. A phase comparison that compares the phases of the output signals of the oscillator and the second frequency divider that divides the oscillation signal of the voltage controlled oscillator with the output signals of the first and second frequency dividers, and outputs the phase difference signal of both signals. And a loop filter for inputting a phase difference signal and outputting it as a control voltage to the voltage controlled oscillator, and switching the division ratio of the second frequency divider when switching the oscillation frequency,
The first frequency divider is configured to switch the frequency division ratio.

According to the present invention, it is possible to obtain a PLL circuit capable of generating local signals for transmission and reception by one PLL circuit and switching the frequency at high speed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is such that a reference signal generator for generating a reference signal, a first frequency divider for dividing the reference signal, and an oscillation frequency by a control voltage. The voltage-controlled oscillator that changes and the second frequency divider that divides the oscillation signal of the voltage-controlled oscillator are compared with the phases of the output signals of the first and second frequency dividers, and the phase difference signal of both signals is calculated. A phase comparator for outputting and a loop filter for inputting a phase difference signal and outputting as a control voltage to a voltage controlled oscillator are provided,
When the oscillation frequency is switched, the frequency division ratio of the second frequency divider is switched, and the frequency division ratio of the first frequency divider is also switched. The oscillation frequency can be switched at high speed by increasing the frequency of the comparison signal.

According to a second aspect of the present invention, a reference signal generator for generating a reference signal, a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, and a frequency divider for dividing the oscillation signal of the voltage controlled oscillator. , A phase comparator for comparing the phases of the reference signal and the output signal of the frequency divider to output a phase difference signal between the two signals, and two loops for inputting the phase difference signal and outputting as a control voltage to the voltage controlled oscillator And a frequency division ratio of the frequency divider when switching the oscillation frequency, a first loop filter having excellent frequency convergence characteristics is selected from the two loop filters, and after frequency stabilization, the first loop filter is selected.
It is configured to select the second loop filter having excellent low noise characteristics from the loop filters of the system,
By selecting the first loop filter when switching the frequency and selecting the second loop filter after stabilizing the frequency, it is possible to achieve both high-speed switching of the oscillation frequency and low noise characteristics.

According to a third aspect of the invention, in the invention of the second aspect, selection of two loop filters is performed by switching control of a loop filter switch provided between the phase comparator and the loop filter. When the frequency is switched, the loop filter switch is controlled to select the first loop filter, and after the frequency is stabilized, the loop filter switch is controlled to select the second loop filter. By doing so, both high-speed switching of the oscillation frequency and low noise characteristics can be realized.

According to a fourth aspect of the invention, in the second aspect of the invention, the selection of the two loop filters is performed by a switching timing signal generated based on a frequency switching signal instructing switching of the oscillation frequency. The first loop filter is selected at the time of frequency switching, and the second loop filter is selected after the frequency is stabilized, so that high-speed switching of the oscillation frequency and low noise characteristics can be realized at the same time. it can.

An embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention. This PLL circuit includes a reference signal generator 1 that oscillates a reference signal having a reference frequency, a first frequency divider 2 that divides the reference signal and outputs the result as a comparison signal, and a frequency that corresponds to the control voltage. A VCO (voltage controlled oscillator) 3 that oscillates a signal, a second frequency divider 4 that divides the signal oscillated by the VCO 3, and an output signal of the second frequency divider 4 and a comparison signal are compared. It has a phase comparator 5 that outputs both error components.

Further, a charge pump 6 for converting an error component of the phase comparator 5 output as a digital amount into an analog amount, and an output of the charge pump 6 is one of two loop filters described later. A loop filter switching unit 7 for outputting to the first loop filter, a first loop filter 8 and a second loop filter 9, one of which is selected by the loop filter switching unit 7, and the output of the selected loop filter 8 or 9 It is configured to control the oscillation frequency of the VCO 3.

The first loop filter 8 is a circuit configured so that the frequency convergence time has the highest priority in order to achieve high-speed switching of the oscillation frequency, and the second loop filter 9 is used for ensuring the performance. The S / N ratio is a circuit configured with the highest priority.

In this configuration, when the oscillation frequency is switched, the loop filter switching signal RS is used to control the switching of the loop filter switching device 7, and the first loop filter 8 for speeding up the frequency convergence time is selected. The frequency switching signal FS switches the frequency division ratio of the first frequency divider 2 and the second frequency divider 4 to control the VCO 3. The frequency division ratio of the first frequency divider 2 is switched in order to increase the frequency of the comparison signal and achieve high-speed switching of the oscillation frequency.

When the oscillation frequency becomes stable, the loop filter switching signal RS is used to switch the loop filter switching circuit 7 again, and this time, the second loop filter 9 having a low noise characteristic is selected to secure the performance.

If this PLL circuit is used to generate local signals for transmission and reception of a TDMA digital mobile phone, the oscillation frequency of the local signal can be switched according to the transmission slot or the reception slot of the own station of TDMA. .

FIG. 2A shows the slot structure of the own station of a PDC (Personal Digital Cellular) type full rate digital mobile phone (FIG. 2A). The idle slot S1 is followed by a transmission slot S2 and a level monitor for diversity. It is connected to S3 and the reception slot S4.

FIG. 6B is a time chart showing the oscillation frequency of the local signal in the PLL circuit of the present invention corresponding to the slot structure shown in FIG. As is clear from this figure, good diversity characteristics cannot be obtained unless the local signal is switched from transmitting to receiving during the diversity level monitor S3, and it is necessary to switch the oscillation frequency at high speed.

(Second Embodiment) FIG. 3 is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention. In the figure, the same components as those of the PLL circuit shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the loop filter switch 7 is deleted from the configuration shown in FIG. 1, and the output of the charge pump 6 is directly output to the first and second loop filters 8 and 9. ing. Charge pump 6
Which of the two loop filters should output the output of is controlled by counting the frequency switching signal FS by the newly provided timing counter 10. The other structure is the same as the structure shown in FIG.

In this configuration, the timing counter 10 calculates the switching timing of the two loop filters based on the frequency switching signal FS, controls the charge pump 6 based on the calculation result, and outputs the output of the first loop filter. 8 or the second loop filter 9 outputs. According to the second embodiment configured in this way, the loop filter switch 7 is not necessary, so that the control load can be reduced by simplifying the control method.

[0023]

As described above, according to the present invention, the oscillating frequency can be switched at high speed. Therefore, when the present invention is used in a TDMA digital mobile communication device having an antenna switching diversity function, it can be used in accordance with the transmission / reception slot. The frequency of the local signal can be switched at high speed, and the excellent effect of achieving both good diversity characteristics and miniaturization can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention.

2A is a diagram showing a slot configuration of a PDC full-rate digital mobile phone, and FIG. 2B is a time chart showing an oscillation frequency of a local signal corresponding to the slot configuration.

FIG. 3 is a block diagram of a PLL circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Reference Signal Generator 2 First Divider 3 Voltage Controlled Oscillator (VCO) 4 Second Divider 5 Phase Comparator 6 Charge Pump 7 Loop Filter Switcher 8 First Loop Filter 9 Second Loop Filter 10 Timing counter

Claims (4)

[Claims] 1. A reference signal generator that generates a reference signal, a first frequency divider that divides the reference signal, a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, and an oscillation of the voltage controlled oscillator. A second frequency divider that divides the frequency of the signal; a phase comparator that compares the phases of the output signals of the first and second frequency dividers and outputs a phase difference signal of both signals; And a loop filter that outputs the control voltage to the voltage controlled oscillator as the control voltage. When the oscillation frequency is switched, the frequency division ratio of the second frequency divider is switched, and the first frequency divider is used. A PLL circuit configured to switch the frequency division ratio of the. 2. A reference signal generator which generates a reference signal, a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, a frequency divider which divides an oscillation signal of the voltage controlled oscillator, the reference signal and the A phase comparator that compares the phases of the output signals of the frequency dividers and outputs a phase difference signal between the two signals, and a loop filter of two systems that inputs the phase difference signals and outputs the phase difference signals as the control voltage to the voltage controlled oscillator And switching the frequency division ratio of the frequency divider when switching the oscillation frequency, and selecting the first loop filter having excellent frequency convergence characteristics from the loop filters of the two systems, and after frequency stabilization. A PLL circuit configured to select a second loop filter having excellent low noise characteristics from the two loop filters. 3. The PLL circuit according to claim 2, wherein the selection of two loop filters is performed by switching control of a loop filter switch provided between the phase comparator and the loop filter. 4. A PLL circuit, wherein selection of two loop filters is performed by a switching timing signal generated based on a frequency switching signal instructing switching of an oscillation frequency.