JPH0758636A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To quickly and stably switch the frequency with a certain comparsion frequency independently of the channel width by providing a direct digital synthesizer which generates a comparison signal having a corresponding frequency based on the output of a voltage controlled oscillator and phase data set from the outside. CONSTITUTION:An output frequency fv of a direct digital synthesizer DDS 40 is given by fv=fo.PHI/2N. When PHI<2N is selected, the DDS 40 functions as a variable frequency divider which has a frequency division number fo/fv=2N/PHI corresponding to the set value of phase data PHI. Consequently, fo=2N.fR/PHI is true at the time of phase lock with respect to a PLL loop; but when phase data PHI is controlled by PHI=PHIo-i.DELTAPHI (i=0, 1, 2...), the output frequency fo of a voltage controlled oscillator 5 is changed by fo=2N.fR/(PHIo-i.DELTAPHI). Then, PHIis selected as a large value and DELTAPHI is selected as a very small value to arbitrarily reduce the channel step width of the output frequency fo.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer using a PLL system. For example, in digital mobile communication, there is a demand for accommodating more channels in a limited frequency band.
Further, in a zone-divided mobile network, a channel during a call is instantly (1-2 m
It is necessary to switch to s). Therefore, it is desired to provide a frequency synthesizer for a wireless device used in such a mobile communication network, which can switch channels to a desired channel at high speed and accurately with a small channel step width.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional basic frequency synthesizer, in which 1 is a reference oscillator (R
O), 2 is a digital phase comparator (DPD), 3 is a charge pump (CP), 4 is a low-pass filter (LP).
F), 5 is a voltage controlled oscillator (VCO), 6 is a variable frequency divider (1 / N), and 7 is a frequency switching control unit.

The digital phase comparator 2 outputs a digital phase error signal by comparing the reference signal f _R of the reference oscillator 1 and the signal f _V obtained by dividing the output signal f _{O of the} VCO 5 by N. The charge pump 3 converts the digital phase error signal into an analog phase error signal, and the low pass filter 4 removes an unnecessary high frequency component of the analog phase error signal and smoothes it. The VCO 5 generates an output signal f _O having a frequency corresponding to the output voltage of the low-pass filter 4 and feeds this output signal f _{O back} to the digital phase comparator 2 via the variable frequency divider 6 to form a PLL loop. is doing. Then, the switching control unit 7 variably sets the frequency division number N to switch the channel of the output signal f _O.

In such a configuration, the output frequency f_O= Nf
_ROutput signal f_OThe channel spacing of the
Wave number f_RDepends on. That is, for example, f_R= 25kH_Z, N
= 40000 + i (where i = 0, 1, 2, ...)
And the output frequency f_O= 1GH _Z+ I ・ 25kH_ZIn
It Therefore, the comparison frequency f_RBetween channels by decreasing
The gap can also be reduced.

However, the comparison frequency of the digital phase comparator 2 in the configuration of FIG. 4 is always f _R (= 25kH _Z), the phase error signal only every cycle (every = 0.04 ms) of the f _R is Does not occur. Therefore, when the channel interval is small, the comparison frequency f _R (that is, the loop gain) also becomes small, which requires a considerable time for the frequency pulling operation by the PLL loop. Moreover, when the output frequency f _O is switched over by several channels at a time, the pull-in time also becomes about several times, so that it is difficult to switch the output frequency f _O quickly.

FIG. 5 is a block diagram of another conventional frequency synthesizer, in which 8 is a variable frequency divider (1 / M) and 9 is a frequency divider.
Is a variable frequency divider (1 / D), and 9 ₁ is a prescaler (1 / D).
P, P + 1), 9 ₂ is a swallow counter (1 / A), 9
₃ is a program counter (1 / N), and 10 is a frequency switching control unit. In variable frequency divider 9, prescaler 9 ₁ initially operates at 1 / (P + 1) mode, swallow counter 9 ₂ outputs when A count output of the prescaler 9 ₁ Prescaler 9 _1-divided switching signal. The prescaler 9 ₁ receiving this operation operates in the 1 / P mode until the program counter 9 ₃ counts the remaining (NA). Therefore, the total frequency division number D is D = (P
+1) A + P (NA) = A + PN, where if A is 0 to (P-1) and N is an arbitrary integer, the total frequency division number D will be an arbitrary integer.

FIG. 6 shows the operation of the frequency synthesizer of FIG.
FIG. 6A is a diagram for explaining, and FIG. 6A shows frequency division numbers M and D (=
A + PN) setting sequence, FIG. 6B shows
Output frequency f of VCO5_OIt is a figure which shows the transition of. Na
In this example, the oscillation frequency of the reference oscillator 1 = 8 MH_Z,
And prescaler 9 ₁The frequency division number of P = 128 and VCO
Output frequency f of 5_OTo 800 MH_ZTarget 80 from below
0.08125MH_ZShows the case of switching all at once
There is.

First, the frequency division number D = 8001, the comparison frequency f
_R= 100KH_ZAs a result of setting, PLL loop gay
The output frequency f of the VCO 5 is_OBox's
Target frequency F at time_out= 800.1MH_ZTowards coarse
It is rising rapidly. However, in the configuration of FIG.
However, the output frequency f_O= Df_RHave a relationship
Finally, the comparison frequency f_RBelow the channel spacing
Without it, the target frequency cannot be converged. Therefore,
In the case of
Comparison frequency f_RThe loop gain in stages
Output frequency f_OThe final lap
Wave number F_out= 800.08125MH _ZExactly converged to
I am making it.

Therefore, according to the configuration of FIG. 5, when the output frequency f _O is skipped and switched for a plurality of channels, there is an effect of shortening the frequency pull-in time, but the frequency pull-in operation approaching the final stage. Since there is no difference from the case of FIG. 4, there is a limit to speeding up channel switching. FIG. 7 is a block diagram of still another conventional frequency synthesizer (Japanese Patent Laid-Open No. 3-250814). In FIG. 7, 11 is a fixed frequency divider (1 / B), 12 is a frequency switching control unit, and 30 is direct digital. Synthesizer (DD
S), 30 ₁ is a cumulative adder (SUM), 30 ₂ is a sine table ROM (ROM), and 30 ₃ is a D / A converter (D /
A), 30 ₄ are low-pass filters (LPF), and 30 ₅ are rectangular wave generating circuits (PC).

In the DDS 30, the cumulative adder 30₁Is one
The constant phase data φ is used as the clock signal f _CEvery timing
Cumulatively adds to an N-bit accumulator (not shown). So
As a result, the accumulator cumulative addition phase data is clocked
Signal f_CSpeed corresponding to the frequency of (ie, f_C・ Φ / 2^N
Frequency) of 0-2^NYou will be going around between. Rhino
Portable ROM 30₂Is the cumulative addition of phase data.
Change to width information, D / A converter 30₃The amplitude information
Convert to log signal. Low pass filter 30_FourIs an analog
Harmonic components other than the target output frequency of the signal
Then, the rectangular wave generation circuit 30_FiveIs a low pass filter
Thirty_FourConvert the output of to a square wave signal of the corresponding frequency
It

From the above, the output frequency f of the DDS 30_R
Has f_R= F_C・ Φ / 2^NHave a relationship. Switching control unit
12 is, for example, the clock frequency f_CF_C= F_C0+ I
Δf _C(However, i = 0,1,2, ...)
And the comparison frequency f_RIs f_R=
(Φ / 2^N) × (f_C0+ I · Δf_C) = F_R0+ I · Δf
_RChanges in the form of. In this case, f_C0A big, bonito
Δf compared to this_CIf you choose a very small
Wave number f_R= 2.25MH_Z＋ i ・ 500H_ZCan be realized
It Alternatively, the switching control unit 12 uses the cumulative adder 30.₁Phase of
Increment value φ is φ = φ₀+ I · Δφ (however, i
= 0,1,2, ...),
As a result, the comparison frequency f_RIs f_R= (F_C/ 2^N) ×
(Φ₀+ I ・ Δφ) = f_R0+ I · Δf_RChanges in the form of
It In this case, φ₀Is larger and Δφ compared to this
If f is selected to be extremely small, for example, the comparison frequency f_R= 2.2
5 MH_Z＋ i ・ 500H_ZCan be realized.

On the other hand, for the PLL loop, f_O= B
・ F_RHowever, the switching control 12 is compared as described above.
Frequency f_RF_R= F_R0+ I · Δf_RCan be controlled in the form of
Therefore, the output frequency f of the VCO 5 is finally_OF_O=
Bf_R0+ B ・ i ・ Δf_RCan be controlled in the form of. Therefore,
For example, if the frequency division number B = 400, f_O= 900MH _Z
+ I ・ 0.2MH_Zbecome.

According to the configuration of FIG. 7, although the channel spacing of the output frequency f _O is as small as 0.2 MH _Z , the comparison frequency f _R can always be kept as high as 2.25 MH _Z or higher, and therefore the loop The gain is always high and the channel can be switched quickly. By the way, generally, in a frequency synthesizer using a PLL loop, the low pass filter 4 removes harmonic components of the phase error signal, but the comparison frequency f _R of the phase comparison circuit 2 is VCO via the external route A.
5 input, which can adversely affect the operation of VCO 5 during phase lock. Therefore, conventionally,
Although not shown, it is usual to provide a notch filter centered on the comparison frequency f _R at the input of the VCO 5.

[0014]

However, the structure of FIG.
Comparison frequency f_RVariably generated by DDS30
The PLL loop responds to channel switching.
By comparison, various comparison frequencies f _R(= F_R0+ I · Δf_R)
It will be phase locked. Therefore, various comparison frequencies
Number f_RThere is a risk that noise due to leaks into the input of VCO5.
Therefore, in the frequency synthesizer of FIG.
It is necessary to provide multiple or wide band notch filters at the 5 inputs.
There was a point. And this is what makes the frequency synthesizer
It was complicated, expensive, and unreliable in operation.

An object of the present invention is to provide a frequency synthesizer capable of performing fast and stable frequency switching with a constant comparison frequency regardless of the channel step width.

[0016]

The above problems can be solved by the structure shown in FIG. That is, the frequency synthesizer of the present invention (1) is a frequency synthesizer using the PLL system, and a phase comparator 2 for detecting a fixed frequency reference oscillator 1 and a phase difference between an output of the reference oscillator 1 and a comparison signal described later. A low-pass filter 4 for smoothing the output of the phase comparator 2, and a voltage-controlled oscillator 5 for generating an output signal of a corresponding frequency according to the output of the low-pass filter 4.
And a direct digital synthesizer 40 that forms the comparison signal of the corresponding frequency based on the output of the voltage controlled oscillator 5 and the phase data set from the outside.

The above problem can be solved by the structure of FIG. That is, the frequency synthesizer of the present invention (2) is a frequency synthesizer using a PLL system, in which a fixed frequency reference oscillator 1, a first variable frequency divider 8 that divides the output of the reference oscillator 1 and a variable frequency divider are used. Phase comparator 2 for detecting a phase difference between the output of the frequency divider 8 and a comparison signal described later.
A low-pass filter 4 that smoothes the output of the phase comparator 2, a voltage-controlled oscillator 5 that generates an output signal of a corresponding frequency according to the output of the low-pass filter 4, and a second that divides the output of the voltage-controlled oscillator 5. Output of the voltage controlled oscillator 5 and the direct digital synthesizer 40 that forms a signal of the corresponding frequency based on the phase data set from the outside, and the output of the second variable frequency divider 9. Switch means 16 for switching between the output of the direct digital synthesizer 40 and the output of the comparison signal.
And a first PLL loop including the second variable frequency divider 9 and a PLL control of a second PLL loop including the direct digital synthesizer 40 and a switching control unit 15 for performing switching control of these loops. , Switching control unit 15
In the first PLL loop, the output frequency is controlled by the second PLL loop, and after the frequency is controlled, the phase synchronization control is performed by the first PLL loop.

[0018]

In FIG. 1A, the direct digital
Output frequency of synthesizer (hereinafter referred to as DDS) 40
f_VIs f_V= F_O・ Φ / 2^NGiven in. Therefore,
φ <2^NIf set to, DDS40 will set the phase data φ
Frequency division number f according to_O/ F _V= 2^N/ Φ variable frequency divider
Works.

Therefore, the PLL loop has a relationship of f _O = 2 ^N · f _R / φ when the phase is locked. In this case, the phase data φ is φ = φ ₀ −i · Δφ (however, i
= 0,1,2, ...), the output frequency f _O of the voltage controlled oscillator 5 is f _O = 2 ^N · f _R / (φ ₀ −i
・ Changes in the form of Δφ). Therefore, choose a large φ ₀ ,
And by choosing Δφ to be extremely small compared to this,
The channel step width of the output frequency f _O can be arbitrarily reduced.

Moreover, in this case, the comparison frequency f _R is constant, and it is possible to select a high value, so that P
The loop gain of the LL loop is always high, so channel switching is done quickly. Further, since the comparison frequency f _R is constant, the frequency of noise leaking into the input of the voltage controlled oscillator 5 via the external path during the phase lock of the PLL loop is also constant f _R. Therefore, even if a notch filter is provided, a simple configuration will suffice. Also, since there is little concern about noise, highly reliable PLL operation can be performed.

In FIG. 1B, the switching controller 15
When switching the channel of the output frequency f _O , the first variable frequency divider 8 outputs the comparative frequency f _R2 which is relatively higher than the channel step width, and the terminals b and c of the switch means 16 are connected to each other. By the second PLL loop including the DDS 40, quick frequency pull-in control (which may include subsequent phase synchronization control) of the output frequency f _{O to} the target value is performed. After the frequency pull-in is performed, the first variable frequency divider 8 outputs the comparison frequency f _R1 of the channel step width, and the terminals ac of the switch means 16 are connected to each other so that the predetermined frequency division is performed. The phase synchronization control is continuously performed by the first PLL loop including the second variable frequency divider 9 set to the number D.

In this case, preferably, the switching controller 15
Turns off the power of the DDS 40 when not in use or sets it to a power save mode with low power consumption. Generally, DDS consumes more power than the variable frequency divider, so after achieving the original purpose of high-speed channel switching, the power supply should be turned off completely or in a power save mode with low power consumption. The power consumption is thereby reduced. In particular, this measure is effective for battery-driven communication devices such as mobile devices.

[0023]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 is a block diagram of the frequency synthesizer of the first embodiment, in which 1 is a reference oscillator (RO) and 2 is a digital phase comparator (DP).
D), 3 is a charge pump (CP), 4 is a low pass filter (LPF), 11 is a notch filter (NF) having a center frequency f _R , 5 is a voltage controlled oscillator (VCO), 17 is a prescaler (1 / P), 13 is a frequency switching control unit, 4
0 is a direct digital synthesizer (DDS), 4
0 ₁ is a phase accumulator, 40 ₁₁ is an adder (AD
D), 40 ₁₂ is an N-bit register (REG), 40 ₂
Is a waveform conversion ROM (ROM), 40 ₃ is a D / A converter (D / A), 40 ₄ is a low-pass filter (LPF), 4
0 ₅ is a rectangular wave generating circuit (PC).

The notch filter 14 is connected to the external path A.
It may be provided when there is a risk of leakage of the comparison frequency f _R via. Further, the prescaler 17 is not necessary when the DDS 40 can directly operate at the output frequency f _O. The digital phase comparator 2 receives the reference signals f _R and V of the reference oscillator 1.
And it outputs the digital phase error signal by comparing the output signal f _O of CO5 by the frequency division number P · 2 ^N / φ a divided signal f _V. The charge pump 3 converts the digital phase error signal into an analog phase error signal, and the low pass filter 4 removes an unnecessary high frequency component of the analog phase error signal and smoothes it. The VCO 5 generates an output signal f _O having a frequency according to the output voltage of the low pass filter 4, and further outputs this output signal f _O to the prescaler 17 and the DDS.
By feeding back to the digital phase comparator 2 via 40, a PLL loop is formed. Then, the switching control unit 13 variably sets the phase data φ to switch the channel of the output frequency f _O.

In the DDS 40, the phase accumulator 40 ₁ cumulatively adds the phase data φ from the switching controller 13 to the N-bit register 40 ₁₂ at each timing of the clock signal f _C from the prescaler 17. As a result, the cumulative addition phase data of the output of the register 40 ₁₂ circulates between 0 and 2 ^N at a speed corresponding to the frequency of the clock signal f _C (that is, the frequency of f _C · φ / 2 ^N ). Become. The waveform conversion ROM 40 ₂ uses the cumulative addition phase data as an address input to read a part of the corresponding waveform data from the data output, and the D / A converter 40 ₃ converts a part of the read waveform data to a corresponding analog signal. To do. The low-pass filter 40 ₄ removes harmonic components other than the target waveform signal from the analog signal, and the rectangular wave generation circuit 40 ₅ converts the output of the low-pass filter 40 ₄ into a rectangular wave signal f _V having a corresponding frequency. .

From the above, the output frequency f of the DDS 40
_V is represented by f _V = f _C · φ / 2 ^N , where φ <2 ^N
If selected, the DDS 40 functions as a variable frequency divider having a frequency division number f _C / f _V = 2 ^N / φ according to the set value of the phase data φ. Therefore, the PLL loop has a relationship of f _O = P · 2 ^N · f _R / φ when the phase is locked. In this case, the switching control unit 13 sets the phase data φ to φ = φ ₀ −i ·
When controlled in the form of Δφ (however, i = 0, 1, 2, ...)
The output frequency f _O of the voltage controlled oscillator 5 is f _O = P · 2 ^N
· F _R / will change in the form of (φ ₀ -i · Δφ). Therefore, choose φ ₀ to be large and compare it with Δφ
It is possible to arbitrarily reduce the channel step width of the output frequency f _O by selecting an extremely small value.

Incidentally, for simplicity of calculation, P = 10,
2 ^N = 10 ⁵ , f _R = 100 KH _Z , φ ₀ = 10 ⁴ , Δ
Assuming φ = 10, the output frequency f _{OCH0 of} channel 0
^{= 10 11/10 4 = 10.00MH} Z, the output frequency ^{_{f OCH1 = 10 11 / (10}} 4 -10) Channel 1 = 10.0
1 MH _Z, the output frequency of the channel 2 f _OCH2 = 10 ¹¹ /
(10 ⁴ −20) = 10.02 MH _Z , and so on.

Therefore, in this example, although the channel step width is as small as 10 KH _Z , the comparison frequency f _R is 1
It is as high as 00 KH _Z, and therefore the loop gain of the PLL loop is always high, whereby the channel switching of the output frequency is performed quickly. The comparison frequency f _R is 100KH _Z
Always because it is constant, the frequency of the noise that leaks into the input of the voltage controlled oscillator 5 is also fixed such that the center of the 100KH _Z. Therefore, 100KH if necessary
A single notch filter whose center frequency is _Z may be provided.

For simplicity of explanation, the phase data φ is represented by φ = φ ₀ −iΔφ (where i = 0, 1,
2) is controlled, but in actuality, Δφ may be slightly changed in the middle in order to keep the channel step width of the output frequency f _O exactly constant. FIG. 3 is a block diagram of the frequency synthesizer of the second embodiment. In the figure, 8 is a variable frequency divider (1 / M), 9 is a variable frequency divider (1 / D), 1
Reference numeral 6 is a switch means (SW), and 15 is a frequency switching control unit. In this case as well, the notch filter 14 may be provided if necessary, and the prescaler 17 may be the DDS 4
Not required if 0 is directly operable at output frequency f _O.

The switching control unit 15 outputs a comparatively high comparison frequency f _R2 = 100 KH _Z from the variable frequency divider 8 when switching the channel of the output frequency f _O , and connects the terminals b and c of the switch means 16. Second including DDS40
For example, the target value 1 of the output frequency f _O is obtained by
Rapid frequency pull-in control to 0.05MH _Z (which may also include a subsequent phase sync control) performed. At that time, the control signal TC having a time constant is sent to the low-pass filter 4 to increase the loop gain during the frequency pull-in control. Furthermore, in this state, the frequency division number D = 1005 is set in the variable frequency divider 9 to set the output frequency f _V1 of the variable frequency divider 9.
Has become 10KH _Z by 10.05MH _Z / 1005 it is.

[0031] After the frequency pull described above is performed, causes output a first variable frequency divider 8 than the channel step size following comparison frequency f _R1 = 10KH _Z, terminal a-c of the switching means 16 The first PLL loop including the variable frequency divider 9 is connected to each other, and the phase synchronization control is continuously performed. That is, the output frequency f _O of the VCO 5 at this time is
Already f _O = D · f _R1 = 1005 × 10 KH _Z = 10.0
Because have a relationship of 5MH _Z, the first PLL loop is not necessary to perform longer frequency pull operation. However, since the phase between the comparison frequencies f _R1 and f _V1 may deviate by up to ± π, the first PLL loop is preferably phase preset before it is closed. For example, when the switching controller 15 outputs the energizing signal E, the variable frequency divider 9 is preset in phase so as to be synchronized with the output of the DDS 40.

After that, the switching control section 15 sends a power control signal PWC to the DDS 40, which causes the DD when not in use.
The power of S40 is turned off or the power save mode with low power consumption is set. The power save mode is, for example, when the power of only the circuit part that can start up at high speed is completely turned on.
It is referred to as FF, or stopping the operation of the circuit portion by stopping the supply of the clock signal to the circuit portion composed of the CMOS IC element.

In mobile communication, since the mobile device can know in advance whether or not it is necessary to switch the channel during a call by monitoring the received electric field strength RSSI by the mobile device or the like, in such a case, the power source of the DDS 40 can be completely removed. It may be turned off. When switching the channel during a call in such a case, the power of the DDS 40 should be turned on again with sufficient margin.
This is because the operation can be started.

Although the digital phase comparator 2 is used in the above embodiment, an analog phase comparator may be used instead. Further, although the specific configuration of the DDS 40 as an example is shown in the above-described embodiment, the DDS may be configured in any manner as long as it has the same function as the DDS 40.

[0035]

As described above, since the frequency synthesizer of the present invention has the above-mentioned configuration, it can switch channels to any channel at high speed regardless of the small channel step width. Moreover, since the comparison frequency at that time is constant, it is possible to effectively prevent noise from leaking into the voltage controlled oscillator, thereby providing a frequency synthesizer with high operational reliability.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a frequency synthesizer of the first embodiment.

FIG. 3 is a block diagram of a frequency synthesizer of a second embodiment.

FIG. 4 is a block diagram of a conventional basic frequency synthesizer.

FIG. 5 is a block diagram of another conventional frequency synthesizer.

6 is a diagram for explaining the operation of the frequency synthesizer of FIG.

FIG. 7 is a block diagram of still another conventional frequency synthesizer.

[Explanation of symbols]

 1 Reference Oscillator 2 Phase Comparator 3 Charge Pump 4 Low Pass Filter 5 Voltage Controlled Oscillator 8, 9 Variable Frequency Divider 15 Switch Control Section 16 Switch Means 30, 40 Direct Digital Synthesizer

Claims (3)

[Claims] 1. A frequency synthesizer using a PLL system, comprising: a fixed frequency reference oscillator (1); and a phase comparator (2) for detecting a phase difference between an output of the reference oscillator (1) and a comparison signal described later. A low-pass filter (4) that smoothes the output of the phase comparator (2), a voltage-controlled oscillator (5) that generates an output signal of a corresponding frequency according to the output of the low-pass filter (4), and a voltage-controlled oscillator (5 ) And a direct digital synthesizer (40) that forms the comparison signal of a corresponding frequency based on the output of the external phase) and the phase data set from the outside. 2. In a frequency synthesizer using a PLL system, a fixed frequency reference oscillator (1), a first variable frequency divider (8) for dividing the output of the reference oscillator (1), and a variable frequency divider. A phase comparator (2) that detects a phase difference between the output of the comparator (8) and a comparison signal described later, a low-pass filter (4) that smoothes the output of the phase comparator (2), and a low-pass filter (4). A voltage controlled oscillator (5) that generates an output signal of a corresponding frequency according to the output of the second voltage divider, a second variable frequency divider (9) that divides the output of the voltage controlled oscillator (5), and a voltage controlled oscillator (5) Of the direct digital synthesizer (40), which forms a signal of a corresponding frequency based on the output of the above and the phase data set from the outside, and the output of the second variable frequency divider (9) and the direct digital synthesizer (40). output Of the first PLL loop including the switch means (16) for switching the output signal to output the comparison signal, the second PLL circuit including the second variable frequency divider (9), and the second PLL loop including the direct digital synthesizer (40). A switching control unit (15) for performing PLL control and switching control of these loops is provided, and the switching control unit (15) performs pull-in control of the output frequency by the second PLL loop, and after the frequency pull-in, the first control is performed. 2. A frequency synthesizer characterized in that phase synchronization control is performed by the PLL loop. 3. The switching control unit (15) turns off the power source of the direct digital synthesizer (40) when not in use.
Alternatively, the frequency synthesizer according to claim 2, wherein a power save mode with low power consumption is set.