JPH0927567A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0927567A JPH0927567A JP7176999A JP17699995A JPH0927567A JP H0927567 A JPH0927567 A JP H0927567A JP 7176999 A JP7176999 A JP 7176999A JP 17699995 A JP17699995 A JP 17699995A JP H0927567 A JPH0927567 A JP H0927567A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor element
- wiring
- support substrate
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48105—Connecting bonding areas at different heights
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、電源用電極および信号用電極を含む複数の端子電極
が形成された半導体素子が、端子電極に対応する複数の
配線が形成された支持基板に固着された半導体装置に適
用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor element having a plurality of terminal electrodes including power supply electrodes and signal electrodes, and a plurality of wirings corresponding to the terminal electrodes. The present invention relates to a technique effectively applied to a semiconductor device fixed to a supporting substrate.
【０００２】[0002]
【従来の技術】ＬＳＩで代表される最近の半導体装置
は、より高集積化、多機能化が要求されるに伴い、ます
ます多ピン化の傾向にある。このような多ピン化に対応
するパッケージ技術として、例えば、日経ＢＰ社発行、
「日経エレクトロニクス」、１９９４、２−１４号、Ｐ
５９〜Ｐ７３に記載されているようなＢＧＡ（Ｂａｌｌ
Ｇｒｉｄ Ａｒｒａｙ）構造が知られている。このＢＧ
Ａ構造は、表面実装型のＬＳＩにおいて、配線基板に対
する実装用電極として半田バンプのような球状電極を用
いるようにしたものであり、この球状電極は複数個がパ
ッケージの裏面に格子状に配置されている。この球状電
極を配線基板の対応した配線に半田付けすることにより
ＬＳＩは配線基板に面実装される。2. Description of the Related Art Recent semiconductor devices typified by LSIs tend to have more and more pins as higher integration and more functions are required. As a package technology corresponding to such an increase in the number of pins, for example, issued by Nikkei BP,
"Nikkei Electronics", 1994, No. 2-14, P
59-P73, BGA (Ball
The Grid Array) structure is known. This BG
The A structure is a surface mount type LSI in which a spherical electrode such as a solder bump is used as a mounting electrode for a wiring board. A plurality of spherical electrodes are arranged in a grid on the back surface of the package. ing. The LSI is surface-mounted on the wiring board by soldering the spherical electrodes to the corresponding wirings on the wiring board.
【０００３】このパッケージにおいては、表面に複数の
端子電極が形成された半導体素子（半導体チップ）は絶
縁性の支持基板の表面に固着されるとともに、複数の端
子電極はボンディングワイヤによって支持基板表面の対
応した配線に接続されている。そして、各配線はスルー
ホール配線を介して支持基板の裏面に配置されている複
数の球状電極に導通されている。In this package, a semiconductor element (semiconductor chip) having a plurality of terminal electrodes formed on the surface is fixed to the surface of an insulating support substrate, and the plurality of terminal electrodes are attached to the surface of the support substrate by bonding wires. It is connected to the corresponding wiring. Each wiring is electrically connected to a plurality of spherical electrodes arranged on the back surface of the supporting substrate through the through hole wiring.
【０００４】このＢＧＡ構造のパッケージは、ＬＳＩに
おいてこれ以前から用いられている代表的なパッケージ
であるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
に比較して、より高集積化された場合のピンピッチを小
さくでき、同じピン数の場合にはパッケージの面積を小
さくできるという利点がある。This BGA structure package is a QFP (Quad Flat Package) which is a typical package that has been used in LSIs before this.
Compared with, there is an advantage that the pin pitch in the case of higher integration can be reduced and the package area can be reduced in the case of the same number of pins.
【０００５】ＬＳＩを配線基板に実装する場合の実装用
電極として用いられる球状電極は、予め半田片を支持基
板の裏面に搭載した後、リフローによって加熱してその
半田片をバンプとすることによって形成される。あるい
は、支持基板の裏面の所望位置に予めクリーム半田を印
刷した後、リフローによって加熱してクリーム半田を溶
融してバンプ化させことによって形成される。A spherical electrode used as a mounting electrode when mounting an LSI on a wiring board is formed by previously mounting a solder piece on the back surface of a support substrate and then heating by reflow to form the solder piece as a bump. To be done. Alternatively, it is formed by printing the cream solder in advance on a desired position on the back surface of the support substrate and then heating it by reflow to melt the cream solder to form bumps.
【０００６】このようなＢＧＡ構造のパッケージを有す
るＬＳＩにおいて、半導体素子の複数の端子電極には複
数の電源（例えばＶｃｃ、Ｖｄｄ、Ｖｓｓなど）用電極
が含まれているが、この電源用電極は他の端子電極であ
る信号用電極と同様に、支持基板表面に形成されている
対応した配線にボンディングワイヤを通じて接続され
る。この電源用電極が配置されている半導体素子上の位
置は、品種によってあるいはチップサイズなどによって
異なっている。In an LSI having such a BGA structure package, a plurality of power source electrodes (for example, Vcc, Vdd, Vss, etc.) are included in a plurality of terminal electrodes of a semiconductor element. Similar to the signal electrodes that are other terminal electrodes, they are connected to corresponding wirings formed on the surface of the supporting substrate through bonding wires. The position of the power supply electrode on the semiconductor element differs depending on the product type or the chip size.
【０００７】[0007]
【発明が解決しようとする課題】前記のように支持基板
に固着された半導体素子の電源用電極を含む複数の端子
電極を支持基板の対応した配線にボンディングワイヤを
通じて接続する場合、特に半導体素子上の電源用電極の
位置は品種などによって異なっているので、支持基板裏
面の電源用の実装用電極の共通化を図ろうとすると、こ
の実装用電極に導通する配線を半導体素子の電源用電極
の位置に合わせるように支持基板上で種々引き回す必要
がある。しかしながら、支持基板の面積は制約されてい
るので、引き回す配線の自由度には限界が生ずる。When a plurality of terminal electrodes including the power supply electrodes of the semiconductor element fixed to the supporting substrate are connected to corresponding wirings of the supporting substrate through bonding wires, especially on the semiconductor element. Since the position of the power-supply electrode of the power supply electrode differs depending on the product type, etc. It is necessary to make various arrangements on the supporting substrate so as to match the above. However, since the area of the support substrate is limited, there is a limit to the degree of freedom of the wiring to be routed.
【０００８】このため、新しい品種を開発した場合に
は、この半導体素子の電源用電極の位置に合った配線を
形成した支持基板を新規に用意する必要があった。Therefore, when a new type of product is developed, it is necessary to newly prepare a support substrate on which wirings matching the positions of the power supply electrodes of this semiconductor element are formed.
【０００９】また、高速で信号を切り替えた場合に生ず
る同時切り替えノイズを低減させるために、支持基板上
に電源のグランド配線を設ける方法があるが、通常この
グランド配線に接続する実装用電極は特定されていない
ので、前記のように新しい品種を開発した場合には、新
規に支持基板を用意する必要がある。さらに、グランド
配線に接続する実装用電極の配置が必ずしも最適とは言
えなかった。In order to reduce the simultaneous switching noise that occurs when signals are switched at high speed, there is a method of providing a ground wiring of a power source on a supporting substrate. Normally, the mounting electrode connected to this ground wiring is specified. Therefore, when a new product is developed as described above, it is necessary to newly prepare a supporting substrate. Further, the placement of the mounting electrodes connected to the ground wiring has not always been optimal.
【００１０】本発明の目的は、半導体素子の電源用電極
と接続される支持基板上の配線に自由度を与えて、支持
基板の共通化を図ることが可能な技術を提供することに
ある。An object of the present invention is to provide a technique capable of sharing a support substrate by giving a degree of freedom to wiring on the support substrate connected to a power supply electrode of a semiconductor element.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１３】本発明の半導体装置は、複数の配線が形成
された支持基板に半導体素子が固着され、前記半導体素
子の電源用電極および信号用電極を含む複数の端子電極
が導電体を通じて対応した前記配線に接続されてなる半
導体装置であって、前記支持基板に形成される複数の配
線は、前記電源用電極に対応した電源用配線が前記半導
体素子の周囲位置で、かつ前記信号用電極に対応した信
号用配線よりも内側位置に設けられている。In the semiconductor device of the present invention, a semiconductor element is fixed to a supporting substrate on which a plurality of wirings are formed, and a plurality of terminal electrodes including a power electrode and a signal electrode of the semiconductor element correspond to each other through conductors. In the semiconductor device connected to the wiring, the plurality of wirings formed on the support substrate have a power supply wiring corresponding to the power supply electrode at a peripheral position of the semiconductor element and corresponding to the signal electrode. It is provided inside the signal wiring.
【００１４】[0014]
【作用】上述した手段によれば、本発明の半導体装置
は、複数の配線が形成された支持基板に半導体素子が固
着され、前記半導体素子の電源用電極および信号用電極
を含む複数の端子電極が導電体を通じて対応した前記配
線に接続されてなる半導体装置であって、前記支持基板
に形成される複数の配線は、前記電源用電極に対応した
電源用配線が前記半導体素子の周囲位置で、かつ前記信
号用電極に対応した信号用配線よりも内側位置に設けら
れているので、半導体素子の電源用電極と接続される支
持基板上の配線に自由度を与えて、支持基板の共通化を
図ることが可能となる。According to the above-mentioned means, in the semiconductor device of the present invention, the semiconductor element is fixed to the supporting substrate on which a plurality of wirings are formed, and the plurality of terminal electrodes including the power electrode and the signal electrode of the semiconductor element. Is a semiconductor device which is connected to the corresponding wiring through a conductor, a plurality of wirings formed on the support substrate, the power supply wiring corresponding to the power supply electrode in the peripheral position of the semiconductor element, Further, since it is provided inside the signal wiring corresponding to the signal electrode, the wiring on the supporting substrate connected to the power electrode of the semiconductor element is provided with a degree of freedom, so that the supporting substrate can be shared. It is possible to plan.
【００１５】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。The present invention will now be described in detail with reference to the drawings along with embodiments.
【００１６】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
【００１７】[0017]
（実施例１）図１は本発明の実施例１による半導体装置
を示す平面図で、ＢＧＡ構造のパッケージを有するＬＳ
Ｉに適用した例を示している。図２は図１のＡ−Ａ断面
図である。本実施例の半導体装置１は、絶縁性材料から
なる支持基板２の一主面である表面に半導体素子（半導
体チップ）３が接着剤４によって固着され、半導体素子
３の表面に形成されている複数の端子電極５は複数の電
源用電極６および複数の信号用電極７を含んでいる。(Embodiment 1) FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, in which an LS having a BGA structure package is provided.
The example applied to I is shown. 2 is a sectional view taken along line AA of FIG. In the semiconductor device 1 of this embodiment, a semiconductor element (semiconductor chip) 3 is fixed to the surface of the support substrate 2 made of an insulating material, which is one main surface, with an adhesive 4, and is formed on the surface of the semiconductor element 3. The plurality of terminal electrodes 5 include a plurality of power supply electrodes 6 and a plurality of signal electrodes 7.
【００１８】支持基板２の表面には複数の帯状の電源用
配線８（８ａ、８ｂ、８ｃ、８ｄ）とともに、複数の信
号用配線９が形成されている。そして、支持基板２の表
面の複数の電源用配線６および信号用配線７のうち、半
導体素子３の周囲位置には、特に電源用配線６が信号用
配線７よりも内側位置に設けられている。半導体素子３
の複数の信号用電極７と、支持基板３の表面の信号用配
線９との間の対応したもの同士は例えばＡｕ線からなる
ワイヤ１０によってボンディングされている。On the surface of the support substrate 2, a plurality of belt-shaped power supply wirings 8 (8a, 8b, 8c, 8d) and a plurality of signal wirings 9 are formed. Of the plurality of power supply wirings 6 and signal wirings 7 on the surface of the support substrate 2, the power supply wirings 6 are provided at positions around the semiconductor element 3, particularly at positions inside the signal wirings 7. . Semiconductor element 3
The corresponding electrodes between the plurality of signal electrodes 7 and the signal wirings 9 on the surface of the support substrate 3 are bonded by wires 10 made of, for example, Au wires.
【００１９】また、半導体素子３の複数の電源用電極６
は、半導体素子３の周囲の電源用配線８のうち、最短距
離にある電源用配線８が選ばれてボンディングワイヤ１
０によって接続されている。このように、特に電源用配
線８のみを半導体素子３の周囲位置で、かつ信号用配線
９よりも内側位置に設けておくことにより、電源用電極
６からボンディングワイヤ１０を電源用配線８に引き出
す場合に、電源用電極６が半導体素子３のどの位置にあ
っても近くの電源用配線８への接続が可能となる。The plurality of power supply electrodes 6 of the semiconductor element 3 are also provided.
Among the power supply wirings 8 around the semiconductor element 3, the power supply wiring 8 having the shortest distance is selected and the bonding wire 1 is selected.
Connected by 0. In this way, in particular, by providing only the power supply wiring 8 in the peripheral position of the semiconductor element 3 and in the position inside the signal wiring 9, the bonding wire 10 is pulled out from the power supply electrode 6 to the power supply wiring 8. In this case, regardless of the position of the power supply electrode 6 on the semiconductor element 3, it is possible to connect to the nearby power supply wiring 8.
【００２０】なお、半導体素子３の複数の電源用電極６
および信号用電極７の数、支持基板２の信号用配線９の
数は説明を簡単にするため一例を示したものであり、実
際にはこれらは数１０個乃至数１００個が配置されてい
る。The plurality of power supply electrodes 6 of the semiconductor element 3 are provided.
The number of signal electrodes 7 and the number of signal wirings 9 of the support substrate 2 are shown as an example for simplification of description, and in actuality, several tens to several hundreds are arranged. .
【００２１】支持基板２の他主面である裏面には半田バ
ンプからなる球状電極のような実装用電極１１が配置さ
れていて、複数の電源用配線８および信号用配線９は支
持基板２に形成されているスルーホール配線（図示せ
ず）を介して対応した実装用電極１１に導通されてい
る。これによって、半導体素子３の複数の電源用電極６
および信号用電極７は電気的に支持基板２の裏面に引き
出されたことになる。A mounting electrode 11 such as a spherical electrode made of a solder bump is arranged on the back surface which is the other main surface of the support substrate 2, and a plurality of power supply wirings 8 and signal wirings 9 are provided on the support substrate 2. It is electrically connected to the corresponding mounting electrode 11 through the formed through-hole wiring (not shown). As a result, the plurality of power supply electrodes 6 of the semiconductor element 3 are
And the signal electrode 7 is electrically drawn to the back surface of the support substrate 2.
【００２２】支持基板２の表面は半導体素子３およびボ
ンディングワイヤ１０を外部の雰囲気から保護するよう
に例えばエポキシ樹脂からなるパッケージ１２によって
封止されている。但し、図１では説明を理解し易くする
ためにパッケージ１２を取り除いた構造で示している。The surface of the support substrate 2 is sealed by a package 12 made of, for example, an epoxy resin so as to protect the semiconductor element 3 and the bonding wire 10 from the external atmosphere. However, in FIG. 1, the structure is shown with the package 12 removed to facilitate understanding of the description.
【００２３】支持基板２としては、エポキシ樹脂、ポリ
イミド樹脂などをガラスクロスに含浸させてこの表面に
Ｃｕなどの配線を施したものを複数積層して多層配線基
板としたプラスチック基板、あるいはアルミナ、窒化ア
ルミニウム、窒化珪素などからなるセラミック基板を用
いることができる。また、一般に半導体装置に使用され
ているリードフレームに絶縁性のテープを貼り付けて、
基板と同等の機能を有するようにしたものも使用可能で
ある。As the supporting substrate 2, a plastic substrate which is a multilayer wiring substrate obtained by impregnating glass cloth with epoxy resin, polyimide resin or the like, and wiring of Cu or the like on the surface thereof is laminated, or alumina, nitride. A ceramic substrate made of aluminum, silicon nitride, or the like can be used. In addition, by attaching an insulating tape to the lead frame that is generally used in semiconductor devices,
A substrate having a function equivalent to that of the substrate can also be used.
【００２４】次に、本実施例の半導体装置の製造方法を
図３乃至図６を参照して工程順に説明する。Next, a method of manufacturing the semiconductor device of this embodiment will be described in the order of steps with reference to FIGS.
【００２５】まず、図３に示すように、表面に図１に示
したような所望のパターンで電源用配線８および信号用
配線９が形成された、例えばプラスチック基板、セラミ
ック基板からなる絶縁性の支持基板２を用意する。First, as shown in FIG. 3, a power source wiring 8 and a signal wiring 9 are formed on the surface in a desired pattern as shown in FIG. 1, and are made of an insulating material such as a plastic substrate or a ceramic substrate. The supporting substrate 2 is prepared.
【００２６】次に、図４に示すように、半導体素子３を
接着剤４によって支持基板２表面に固着した後、半導体
素子３の複数の信号用電極７と支持基板３の表面の信号
用配線９との間の対応したもの同士を例えばＡｕ線から
なるワイヤ１０によってボンディングする。同様にし
て、半導体素子３の複数の電源用電極６を、半導体素子
３の周囲の電源用配線８のうち、最短距離にある電源用
配線８を選んでボンディングワイヤ１０によって接続す
る。Next, as shown in FIG. 4, after the semiconductor element 3 is fixed to the surface of the supporting substrate 2 with an adhesive 4, a plurality of signal electrodes 7 of the semiconductor element 3 and signal wiring on the surface of the supporting substrate 3 are formed. 9 and 9 are bonded to each other by a wire 10 made of, for example, an Au wire. Similarly, the plurality of power supply electrodes 6 of the semiconductor element 3 are connected by the bonding wire 10 by selecting the power supply wiring 8 having the shortest distance among the power supply wirings 8 around the semiconductor element 3.
【００２７】続いて、図５に示すように、支持基板２を
トランスファモールド装置の上型１３と下型１４との間
のキャビティ１５にセットして、ゲート１６から流動状
態の例えばエポキシ樹脂からなる樹脂１７を矢印のよう
に充填する。これによって、支持基板２の表面にはパッ
ケージ１２が形成される。Subsequently, as shown in FIG. 5, the support substrate 2 is set in the cavity 15 between the upper mold 13 and the lower mold 14 of the transfer molding apparatus, and is made of, for example, epoxy resin in a fluid state from the gate 16. Resin 17 is filled as shown by the arrow. As a result, the package 12 is formed on the surface of the support substrate 2.
【００２８】次に、図６に示すように、支持基板２をト
ランスファモールド装置から取り外した後、支持基板２
の裏面に半田バンプのような球状電極からなる実装用電
極１１を形成する。この実装用電極の形成方法は、例え
ば予め半田片を支持基板２の裏面に供給した後、リフロ
ーによって加熱してその半田片をバンプとすることによ
って形成できる。あるいは、支持基板２の裏面の所望位
置に予めクリーム半田を印刷した後、リフローによって
加熱してクリーム半田を溶融してバンプ化させことによ
って形成できる。Next, as shown in FIG. 6, after removing the supporting substrate 2 from the transfer molding apparatus, the supporting substrate 2 is removed.
A mounting electrode 11 composed of a spherical electrode such as a solder bump is formed on the back surface of the. This mounting electrode can be formed by, for example, supplying a solder piece to the back surface of the support substrate 2 in advance and then heating it by reflow to form the solder piece into a bump. Alternatively, it can be formed by printing cream solder in advance on a desired position on the back surface of the support substrate 2 and then heating it by reflow to melt the cream solder to form bumps.
【００２９】以上によって、図１および図２に示したよ
うな半導体素子１が得られる。As described above, the semiconductor device 1 as shown in FIGS. 1 and 2 is obtained.
【００３０】このような実施例１によれば次のような効
果が得られる。According to the first embodiment, the following effects can be obtained.
【００３１】（１）支持基板２の表面の複数の電源用配
線６および信号用配線７のうち、半導体素子３の周囲位
置には、特に電源用配線８が信号用配線９よりも内側位
置に設けられているので、電源用電極６からボンディン
グワイヤ１０を電源用配線８に引き出す場合に、電源用
電極６が半導体素子３のどの位置にあっても近くの電源
用配線８への接続が可能となる。従って、半導体素子３
の電源用電極６と接続される支持基板２上の電源用配線
８および信号用配線９に自由度を与えて、支持基板２の
共通化を図ることが可能となる。(1) Of the plurality of power supply wirings 6 and signal wirings 7 on the surface of the support substrate 2, the power supply wirings 8 are located inside the signal wirings 9, especially around the semiconductor element 3. Since it is provided, when the bonding wire 10 is pulled out from the power supply electrode 6 to the power supply wiring 8, the power supply electrode 6 can be connected to the nearby power supply wiring 8 regardless of the position of the semiconductor element 3. Becomes Therefore, the semiconductor device 3
The power supply wiring 8 and the signal wiring 9 on the support substrate 2 connected to the power supply electrode 6 can be given a degree of freedom, and the support substrate 2 can be shared.
【００３２】すなわち、複数の電源用電極６が半導体素
子３のどの位置にあっても近くの電源用配線８への接続
が可能となるように、支持基板２上で特に電源用配線８
の形成位置を優先させて半導体素子３の周囲位置でかつ
信号用配線９よりも内側位置に設けるようにしたので、
新しい品種を開発した場合でも、ボンディングワイヤ１
０の接続上の制約がない範囲内で、この半導体素子３の
電源用電極６の位置に合った電源用配線８を利用するこ
とができるため、新規の支持基板２を用意する必要はな
くなる。That is, the power supply wiring 8 is particularly provided on the support substrate 2 so that the power supply electrode 6 can be connected to the nearby power supply wiring 8 regardless of the position of the semiconductor element 3.
Since the priority is given to the formation position of the above, it is provided in the peripheral position of the semiconductor element 3 and inside the signal wiring 9.
Bonding wire 1 even when developing a new product
Since the power supply wiring 8 matching the position of the power supply electrode 6 of the semiconductor element 3 can be used within a range where there is no connection restriction of 0, it is not necessary to prepare a new support substrate 2.
【００３３】（２）支持基板２上に形成した電源用配線
８に特定の電源用電極６を割り当てることにより、新し
い品種を開発した場合でも新規の支持基板２を用意する
必要はなくなるので、バーンイン基板、エージング基
板、テスト基板などとの共通化が可能になる。(2) By assigning the specific power supply electrode 6 to the power supply wiring 8 formed on the support substrate 2, it is not necessary to prepare a new support substrate 2 even when a new product type is developed. It can be shared with boards, aging boards, test boards, etc.
【００３４】（実施例２）図７は本発明の実施例２によ
る半導体装置を示す平面図で、図８は図６のＡ−Ａ断面
図である。本実施例の半導体装置１は、支持基板２上に
形成する電源用配線として、特にグランド用配線１８
を、半導体素子３の周囲位置でかつ信号用配線９よりも
内側位置に設けた例を示すものである。(Embodiment 2) FIG. 7 is a plan view showing a semiconductor device according to Embodiment 2 of the present invention, and FIG. 8 is a sectional view taken along line AA of FIG. The semiconductor device 1 according to the present embodiment is particularly equipped with a ground wiring 18 as a power wiring formed on the support substrate 2.
Is provided in the peripheral position of the semiconductor element 3 and in the position inside the signal wiring 9.
【００３５】この場合、グランド用配線１８は共通電極
として使用されるので連続した無端形状に形成できるた
め、半導体素子３の電源用電極６のうちグランド用電極
からボンディングワイヤ１０をグランド用配線１８に引
き出す場合に、グランド用電極６が半導体素子３のどの
位置にあっても近くの電源用配線１８への接続が可能と
なる。In this case, since the ground wiring 18 is used as a common electrode and can be formed in a continuous endless shape, the bonding wire 10 is connected to the ground wiring 18 from the ground electrode of the power supply electrode 6 of the semiconductor element 3. When pulled out, it is possible to connect to the nearby power supply wiring 18 regardless of the position of the ground electrode 6 on the semiconductor element 3.
【００３６】従って、実施例２によっても実施例１と同
様な効果を得ることができる。さらに加えて、各配線
８、９間のインダクタンスを下げることができるので、
高速で信号を切り替えた場合に生ずる同時切り替えノイ
ズを低減させるのに有効となる。Therefore, according to the second embodiment, the same effect as that of the first embodiment can be obtained. In addition, since the inductance between the wirings 8 and 9 can be reduced,
This is effective in reducing simultaneous switching noise that occurs when signals are switched at high speed.
【００３７】（実施例３）図９は本発明の実施例３によ
る半導体装置を示す断面図で、実施例２と同様に、グラ
ンド用配線１８を半導体素子３の周囲位置でかつ信号用
配線９よりも内側位置に設ける構造の他の例を示すもの
である。これは、支持基板２表面の半導体素子３を固着
する位置を除いた全面にグランド用配線１８を形成した
後、このグランド用配線１８を連続した無端形状になる
ように、絶縁層１９によって覆い、さらにこの絶縁層１
９上に複数の信号用配線９を形成することによって製造
することができる。(Embodiment 3) FIG. 9 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention. As with Embodiment 2, the ground wiring 18 is provided around the semiconductor element 3 and the signal wiring 9 is provided. It shows another example of the structure provided at the inner side position. This is because after forming the ground wiring 18 on the entire surface of the surface of the support substrate 2 excluding the position where the semiconductor element 3 is fixed, the ground wiring 18 is covered with an insulating layer 19 so as to have a continuous endless shape, Furthermore, this insulating layer 1
It can be manufactured by forming a plurality of signal wirings 9 on the wiring 9.
【００３８】この実施例３によっても、実施例２と同様
な構造を有することにより、実施例２と同様な効果を得
ることができる。According to the third embodiment, the same effect as that of the second embodiment can be obtained by having the same structure as that of the second embodiment.
【００３９】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention.
【００４０】例えば、前記実施例ではＢＧＡ構造のパッ
ケージを有するＬＳＩに適用した例で説明したが、これ
に限らずＰＧＡ構造のパッケージを有する他のタイプに
適用することもできる。For example, in the above-described embodiment, an example in which the present invention is applied to an LSI having a BGA structure package has been described, but the present invention is not limited to this and can be applied to other types having a PGA structure package.
【００４１】また、パッケージを形成する方法はトラン
スファモールド法に限らず、液状樹脂で覆ったり、樹脂
キャップで覆うなどの他の方法を採ることもできる。The method of forming the package is not limited to the transfer molding method, and other methods such as covering with a liquid resin or covering with a resin cap can be adopted.
【００４２】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である半導体
装置の技術に適用した場合について説明したが、それに
限定されるものではない。本発明は、少なくとも半導体
素子の電源用電極から支持基板上の対応する配線に導電
体を引き出す条件のものには適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the technology of the semiconductor device which is the field of application of the background has been described, but the invention is not limited thereto. The present invention is applicable at least under the condition that the conductor is drawn from the power supply electrode of the semiconductor element to the corresponding wiring on the supporting substrate.
【００４３】[0043]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４４】支持基板表面に形成された複数の電源用配
線および信号用配線のうち、半導体素子の周囲位置には
特に電源用配線が信号用配線よりも内側位置に設けられ
ているので、電源用電極から導電体を電源用配線に引き
出す場合に、電源用電極が半導体素子のどの位置にあっ
ても近くの電源用配線への接続が可能となるため、半導
体素子の電源用電極と接続される支持基板上の電源用配
線および信号用配線に自由度を与えて、支持基板の共通
化を図ることが可能となる。Among the plurality of power supply wirings and signal wirings formed on the surface of the supporting substrate, the power supply wirings are provided inside the signal wirings especially in the peripheral position of the semiconductor element. When a conductor is pulled out from the electrode to the power supply wiring, the power supply electrode can be connected to a nearby power supply wiring regardless of the position of the semiconductor element, so that it is connected to the power supply electrode of the semiconductor element. The power source wiring and the signal wiring on the supporting substrate can be given a degree of freedom, and the supporting substrate can be shared.
【図１】本発明の実施例１による半導体装置を示す平面
図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
【図２】図１のＡ−Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の実施例１による半導体装置の製造法の
一工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the first embodiment of the present invention.
【図４】本発明の実施例１による半導体装置の製造法の
他の工程を示す断面図である。FIG. 4 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図５】本発明の実施例１による半導体装置の製造法の
その他の工程を示す断面図である。FIG. 5 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図６】本発明の実施例１による半導体装置の製造法の
その他の工程を示す断面図である。FIG. 6 is a cross-sectional view showing another process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図７】本発明の実施例２による半導体装置を示す平面
図である。FIG. 7 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
【図８】図７のＡ−Ａ断面図である。FIG. 8 is a sectional view taken along line AA of FIG. 7;
【図９】本発明の実施例３による半導体装置に用いられ
る支持基板を示す断面図である。FIG. 9 is a sectional view showing a supporting substrate used for a semiconductor device according to a third embodiment of the present invention.
１…半導体装置、２…支持基板、３…半導体素子（半導
体チップ）、４…接着剤、５…半導体素子の端子電極、
６…半導体素子の電源用電極、７…半導体素子の信号用
電極、８…支持基板の電源用配線、９…支持基板の信号
用配線、１０…ボンディングワイヤ、１１…実装用電
極、１２…パッケージ、１３…トランスファモールド装
置の上型、１４…トランスファモールド装置の下型、１
５…トランスファモールド装置のキャビティ、１６…ト
ランスファモールド装置のゲート、１７…流動状態の樹
脂、１８…支持基板のグランド用配線。１９…絶縁層。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Support substrate, 3 ... Semiconductor element (semiconductor chip), 4 ... Adhesive agent, 5 ... Terminal electrode of semiconductor element,
6 ... Power source electrode of semiconductor element, 7 ... Signal electrode of semiconductor element, 8 ... Power wiring of supporting substrate, 9 ... Signal wiring of supporting substrate, 10 ... Bonding wire, 11 ... Mounting electrode, 12 ... Package , 13 ... upper mold of transfer molding apparatus, 14 ... lower mold of transfer molding apparatus, 1
5 ... Cavity of transfer molding apparatus, 16 ... Gate of transfer molding apparatus, 17 ... Resin in a fluid state, 18 ... Wiring for ground of supporting substrate. 19 ... Insulating layer.
Claims (5)
体素子が固着され、前記半導体素子の電源用電極および
信号用電極を含む複数の端子電極が導電体を通じて対応
した前記配線に接続されてなる半導体装置であって、前
記支持基板に形成される複数の配線は、前記電源用電極
に対応した電源用配線が前記半導体素子の周囲位置で、
かつ前記信号用電極に対応した信号用配線よりも内側位
置に設けられたことを特徴とする半導体装置。1. A semiconductor element is fixed to a support substrate on which a plurality of wirings are formed, and a plurality of terminal electrodes including power supply electrodes and signal electrodes of the semiconductor element are connected to corresponding wirings through conductors. In the semiconductor device, the plurality of wirings formed on the support substrate have power supply wirings corresponding to the power supply electrodes at a peripheral position of the semiconductor element,
Further, the semiconductor device is provided inside the signal wiring corresponding to the signal electrode.
ンド用電極に対応した配線からなることを特徴とする請
求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the wiring corresponding to the power electrode is a wiring corresponding to the ground electrode.
ることを特徴とする請求項１または２に記載の半導体装
置。3. The semiconductor device according to claim 1, wherein the conductor is a bonding wire.
複数の実装用電極が配置され、前記複数の配線はスルー
ホール配線を通じて前記複数の実装用電極に導通してい
ることを特徴とする請求項１乃至３のいずれか１項に記
載の半導体装置。4. A plurality of mounting electrodes are arranged on a surface of the support substrate opposite to a wiring forming surface, and the plurality of wirings are electrically connected to the plurality of mounting electrodes through through hole wirings. The semiconductor device according to claim 1, wherein
子および導電体を樹脂製パッケージによって封止したこ
とを特徴とする請求項１乃至４のいずれか１項に記載の
半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor element and the conductor fixed to the support substrate are sealed with a resin package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7176999A JPH0927567A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7176999A JPH0927567A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0927567A true JPH0927567A (en) | 1997-01-28 |
Family
ID=16023413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7176999A Pending JPH0927567A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0927567A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338955A (en) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method |
-
1995
- 1995-07-13 JP JP7176999A patent/JPH0927567A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338955A (en) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method |
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