JP2803656B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a tape carrier semiconductor device suitable for high-density mounting.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high performance of electronic devices, there has been an increasing demand for more pins and higher density of semiconductor packages. Along with this, it has become difficult to mount the board by batch reflow due to the narrow pitch of the leads.
The package of the peripheral lead type mounting method typified by the QFP is shifting to the package of the surface grid terminal type mounting method typified by the BGA (Ball Grid Array) capable of expanding the pitch.

At present, wire bonding is mainly used for electrical connection between semiconductor chips and leads.
The connection between the pads and the inner leads has become difficult due to the narrow pitch of the chip pads accompanying the increase in the number of pins.
The AB connection method is receiving attention. In the TAB method, an inner lead provided on an insulating tape and drawn out on a chip is bonded to a bump formed on a chip pad, so that a pad having a pitch of about 60 μm can be used. Tape-BGA is one that uses this bonding technique and the surface lattice terminal mounting method.

The Tape-BGA has a tape carrier 4 as shown in FIGS. The tape carrier 4 includes an opening 16 provided at the center of the insulating tape 15 for receiving the semiconductor chip 1, and an insulating tape 15.
And wirings 3 (3a, 3b) formed by patterning wiring layers 14a, 14b provided on one or both sides of the semiconductor chip 1. One end of the wirings 3a, 3b and the electrode pads 2 of the semiconductor chip 1 are TAB inner. They are connected by a TAB method connected by leads 12. 9 is a support ring.

The electrode pad 2 of the semiconductor chip 1 has a TA
The solder bumps 13 for connection are respectively provided on the bumps for ground 6a, the bumps for power supply 6b, and the bumps for signal 6c, which are connected via the inner lead 12 and the wiring 3 of B, respectively.
Is served. The wiring 3a formed on the front surface side of the insulating tape 15 and the wiring 3b formed on the back surface side are appropriately selected and electrically connected by the conductive metal 8 in the through hole 5. 11 is a sealing resin.

However, the Tape-BG shown in FIGS.
In the structure of A, the weight of the semiconductor chip 1 is applied to the inner leads 12.
Care must be taken in the handling of the insulating tape 1
The area of the opening 16 of 5 cannot be used as a wiring and mounting area, and the wiring provided on the insulating tape 15 is formed so as to avoid the opening 16, and the size of the tape carrier 4 is reduced. There was a limit to shrinking, which was an obstacle to miniaturization.

Further, since the wiring 3 is routed from the inner lead 12 to the solder ball 13, the wiring length is long, and the more pins, the narrower the wiring width and the more complicated the arrangement becomes. Further, when the wiring length is long, there is a problem that the electrical characteristics are affected, such as an increase in impedance.

As a method for solving the problem of the electric characteristics, there is a method of providing a power and ground plane layer as disclosed in Japanese Patent Publication No. 1-60941. According to the technique disclosed in Japanese Patent Publication No. 1-60941, the provision of the plane layer significantly reduces the inductance, thereby improving the electrical characteristics. In this known example, a recent semiconductor chip is often provided with a plurality of power supply electrodes for the purpose of dispersing the amount of current. However, by providing a plane layer, the number of pins can be reduced at the same time. Emphasized.

The specification of Japanese Patent Application No. Hei 6-110857 discloses that through-hole bonding employed in a tape carrier type (TCP) package having a flexible film is effective for improving electrical characteristics. Emphasized. 7 and 8 in this package
As shown in FIG. 5, the tape carrier 4 has a wiring layer 14 provided on one surface of an insulating tape 15 and a through hole 5 formed immediately below a connection portion between the wiring layer 14 and the electrode pad 2.

The wiring layer 14 is electrically connected to a bump 6 as an external connection terminal via a conductive metal 8 formed in a through hole 5 formed in the insulating tape 15 by plating. Tape carrier 4 and semiconductor chip 1
Is through-hole bonded via an adhesive tape 7 in the middle.

[0011]

A conventional tape carrier in which a metal wiring layer is provided on one or both sides of an insulating tape, a tape portion directly below a chip mounting portion is opened, and inner leads are drawn out. So-called Tape-BGA in which electrode pads of a semiconductor chip and inner leads are connected by TAB bonding.
In the type of tape carrier semiconductor device, the power supply and the ground wiring are also routed in the same way as the signal wiring, and the connection wiring length becomes longer as the bump becomes farther from the electrode pad of the semiconductor chip, so that the inductance becomes large and the influence of noise increases. I can't ignore it. In addition, since wiring is provided for each electrode pad, the number of pins is increased, and wiring is complicated.

Further, in this type of tape carrier semiconductor device, since a tape portion corresponding to a portion directly below the semiconductor chip mounting portion is opened and the inner leads are drawn out, wiring cannot be routed to this portion and bumps cannot be formed. Can not be attached. Accordingly, the wiring is always routed toward the outer periphery of the chip, which has a drawback that it becomes an obstacle in increasing the number of pins and reducing the size of the package.

An object of the present invention is to provide a tape carrier semiconductor device which solves the above-mentioned conventional problems, improves electric characteristics, and is suitable for simplifying a wiring pattern, increasing the number of pins, and reducing the size. It is in.

[0014]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor chip and an insulating tape having a metal wiring layer provided on both sides, the semiconductor device comprising: Is mounted on an insulating tape, and the insulating tape is provided on one side of the wiring layer, a connection portion to the electrode of the semiconductor chip, and a portion corresponding directly below the connection portion on the tape back surface. It has a through hole that is opened to reach and buried the conductive pole, and a conductive protrusion as an external connection terminal provided on the back of the tape, and the electrode and the wiring layer of the semiconductor chip are connected by through hole bonding. It is electrically connected, and a power or ground plane layer is provided on at least one surface of the insulating tape.

The ground electrode of the semiconductor chip is connected to a ground external terminal on the back surface of the tape via a ground plane layer, and the ground external terminal is integrated at a peripheral portion of the insulating tape. is there.

Further, the power supply electrode of the semiconductor chip is connected to a power supply external connection terminal on the back surface of the tape via a power supply plane layer, and the power supply external connection terminal is integrated at a central portion of the insulating tape. It is.

[0017]

By connecting the electrode pads of the semiconductor chip to the wiring layer by through-hole bonding and providing a power supply or ground plane layer on at least one side of the insulating tape, wiring processing is performed at a minimum distance to reduce inductance and reduce noise. Decrease. The plane layer is more effective if the ground potential side is made wider. Further, when the ground plane layer and the signal wiring are formed as separate wirings and the signal wiring is formed so as to cover the ground plane layer, noise from the signal wiring is shielded by the ground plane layer, which is more effective. By providing the plane layer, the number of power supply or ground pins can be reduced at the same time.

Furthermore, the wiring pattern is partially simplified by consolidating the ground pins or the power supply pins at the peripheral portion or the central portion of the insulating tape. Since the ground pin and the power supply pin are connected by through holes, the wiring length is short, which is advantageous in terms of electrical characteristics. Therefore, if the bumps far from the chip electrode are filled with these pins, the signal wiring will be shortened as much as possible. be able to. Also, by employing through-hole bonding, wiring can also be provided at a portion directly below the chip mounting and bumps can be arranged, which is advantageous for miniaturization of the package forming the semiconductor device body.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a plan view thereof.

In the figure, the tape carrier semiconductor device of the present invention has a tape carrier 4 composed of an insulating tape 15 provided with metal wiring layers 14a and 14b formed on both sides by etching or the like.

The electrode pad 2 and the wiring 3 of the semiconductor chip 1
(3a, 3b) are directly connected by through-hole bonding using a through-hole 5 provided immediately below the electrode pad 2. After pattern formation, the through hole 5 is provided with a hole in a tape portion at a desired position and is plated with a conductive metal 8.
Filled with.

Also, as an external connection terminal, a bump electrode (conductive material) 6 (6a, 6b, 6c) made of a conductive metal.
Are formed, and the bump electrodes 6 are arranged in a plane lattice at the same pitch, for example, using substantially the entire surface of the tape carrier 4.

In the above-mentioned tape carrier semiconductor device, the wiring is arranged as follows. First, the ground electrode of the semiconductor chip 1 is connected to the ground plane layer 10a provided on the wiring layer 14a, and the plane layer 10a
Through the through hole 5 provided in the thickness direction, the insulating tape 15 is connected to the ground bump 6a provided on the peripheral portion on the back surface side (peripheral portion side of the package forming the semiconductor device body).

The power supply electrode is connected to the power supply plane layer 10b formed in the center of the wiring layer 14b through the through hole 5 provided below the electrode pad 2, and is connected to the center of the insulating tape 15 (the package forming the semiconductor device body). In the middle)
Connected to the power supply bump 6b.

The remaining signal electrodes are connected to the wiring layer 14b through the through holes 5 provided below the electrode pads 2, and the individual wirings 3 formed in the wiring layer 14b except for the power supply plane layer 10b are formed. Through each of the signal bumps 6c on the back surface of the insulating tape 15. That is, signal pins are not arranged as far as possible on bumps located far from the electrode pads.

(Embodiments) Embodiments of the present invention will be described below in more detail with reference to the drawings.

The tape carrier semiconductor device of this embodiment is
Wiring layers 14a and 14b obtained by processing a copper foil into a desired shape by etching or the like, and connection portions 17 for connecting the electrode pads 2 of the semiconductor chip 1 to the wiring layers 14a are provided. The tape carrier 4 includes a polyimide resin insulating tape 15 having through holes 5 formed therein. The through-hole 5 is filled with a conductive metal 8 by plating treatment such as copper. Also, solder bumps 6 as external connection terminals are formed and arranged in a plane lattice at the same pitch using substantially the entire surface of the tape carrier 4.

The electrode pads 2 provided on the outer peripheral edge of the semiconductor chip 1 have connection portions 17 provided on the wiring layer 14a.
Are through-hole bonded. A ground plane layer 10a is provided in a region of the wiring layer 14a other than the connection portion 17, and a plurality of ground electrodes of the semiconductor chip 1
The connection part 17 connects to the plane layer 10a. The plane layer 10a is connected to the wiring layer 14a by a through hole 5 provided in a peripheral portion of the insulating tape 15, and further connected to a ground bump 6a provided near the through hole 5.

On the other hand, the power supply and the signal electrodes are connected to the wiring layer 14 by through-hole bonding via the through-holes 5 provided directly under the pads and filled with the conductive metal 8 inside.
b is connected by the shortest path. The inside of the through hole 5
It is not necessary to be always filled with metal, and plating with a conductive metal may be performed. However, when filled, the connection portion is reinforced and reliability is improved. Also, since energy can be efficiently transmitted through the filling metal, the inner lead bonding condition can be relaxed.

A power supply plane layer 10b having a size equal to the chip size is provided in a region of the wiring layer 14b immediately below the chip 1 mounting portion, and a plurality of power supply electrode pads 2 are all passed through the through holes 5. Plane layer 10b
To the power supply bump 6b provided immediately below the plane layer 10b. The remaining signal wires are individually routed using the entire area of the wiring layer 14b except for the power plane layer 10b, and are connected to the signal bumps 6c on the back surface of the tape.

Next, a method of manufacturing a tape carrier semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 3 (a), the members required to constitute the tape carrier semiconductor device of the present embodiment are a tape carrier 4, an adhesive tape 7, and a semiconductor chip 1.
It is.

The tape carrier 4 can be manufactured, for example, by the following manufacturing method. As shown in FIG. 4A, in a three-layer base material in which a metal foil such as copper is provided on both surfaces of an insulating tape 15, first, a desired shape is formed by a photoresist method and the electrode pad 2 of the semiconductor chip 1 is formed. The wiring layers 14a and 14b are positioned with high precision so that they can be connected.

Next, as shown in FIG. 4B, the adhesive tape 7 is positioned on the tape carrier 4 from the wiring layer 14a side corresponding to the chip, and then fixed. In the case of a thermoplastic resin, it can be temporarily fixed by heating to a temperature at which the adhesive tape melts.

Next, as shown in FIG. 4C, through holes 5 are formed in the insulating tape 15 and the adhesive tape 7 from the wiring layer 14a side by laser or etching.

Further, as shown in FIG.
A through hole 5 is also formed in the insulating tape 15 from the side 4b.

Then, as shown in FIG. 4E, a conductive metal 8 is formed on the wiring layer 14 in the through hole 5 by electrolytic plating or the like. As shown in FIG.
The nickel plating 19 and the gold plating 20 are applied to the surface as shown in FIG.

Next, as shown in FIG. 3B, the semiconductor chip 1 is aligned with the tape carrier 4 to which the adhesive tape 7 is temporarily fixed by a single point bonder used for TAB connection, and then the inner leads are connected.

Next, as shown in FIG.
Are positioned and set, and heating and pressing are performed from the tape carrier 4 side or the chip 1 side.
And the semiconductor chip 1 and the support ring 9 are bonded together with an adhesive tape 7 therebetween. The bonding of the semiconductor chip 1 and the support ring 9 may be performed separately.

Finally, as shown in FIG. 3D, bumps 6 made of, for example, solder and arranged in a plane lattice at the same pitch are formed on the substrate side of the carrier tape 4. Various methods have been proposed for forming solder bumps, but are not particularly limited in the present invention. Further, as a bump material, 63/37 eutectic solder is generally suitable, but the composition of the solder is not limited, and is not limited to solder.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment.
Of course, various modifications and changes may be made without departing from the spirit of the present invention. For example, the power and ground plane layers may be provided on the same wiring layer, and the routing of the signal wiring need not be limited to the wiring layer on the surface corresponding to the substrate, but may be on either of the wiring layers.

Further, the size of the package forming the semiconductor device body is not larger than the size of the semiconductor chip, and may be equal to the size of the semiconductor chip. In this case, the step of attaching the support ring 9 is omitted.

[0043]

As described above, according to the present invention, by employing through-hole bonding and providing a ground or power supply plane layer on at least one surface of the insulating tape, the wiring length can be extremely reduced. In addition, the inductance of the ground or the power supply can be reduced to reduce noise.

Further, if the ground plane layer is made as large as possible and arranged so that the ground plane layer exists on the signal wiring, the noise due to the signal wiring is shielded by the ground plane layer. Can be reduced by half.

For example, 352p Tape-BGA (package size: 35 mmSQ, chip size: 7.3)
8 mmSQ), the inductance of a signal pin having no ground plane layer is about 10 nH. However, when a ground plane layer is provided on a signal wiring with an insulating tape interposed therebetween as in the present invention, the inductance is 5 nH.
H can be reduced to around H. Further, if the characteristic impedance is adjusted in the plane layer, the electrical characteristics can be expected to be further improved.

The power supply pin and the ground pin are considerably separated from each other at the center and the periphery of the insulating tape, and there is a concern that the inductance of the power supply may increase. Since the distance from the electrode to the mounting board is extremely short, it is considered that the above arrangement of the electrode pins and the ground pins has almost no influence.

Further, by consolidating at least one of the ground pin and the power supply pin in the peripheral portion or the central portion of the insulating tape, a part of the wiring pattern is simplified, and the wiring for the signal wiring can be provided with a margin. Further, since the wiring layers and the bumps can be provided directly under the semiconductor chip mounting portion by employing the through holes, the wiring area can be expanded. As a result, the pitch of the bumps can be reduced, which is effective for increasing the number of pins and reducing the size of the package forming the semiconductor device body.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a process chart showing a method of manufacturing a tape carrier used for a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing a conventional technique.

FIG. 6 is a plan view showing the prior art of FIG. 5;

FIG. 7 is a cross-sectional view showing another conventional technique.

FIG. 8 is a plan view showing the conventional example of FIG.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 electrode pad 3 wiring 4 tape carrier 5 through hole 6 bump 7 adhesive tape 8 conductive metal 9 support ring 10 plane layer 11 sealing resin 12 inner lead 13 solder ball 14 wiring layer 15 insulating tape 16 opening 17 Connection between electrode pad and wiring 18 Bonding tool 19 Nickel plating 20 Gold plating

Claims (3)

(57) [Claims] 1. A semiconductor device having a semiconductor chip and an insulating tape provided with a metal wiring layer on both surfaces, wherein the semiconductor chip is mounted on the insulating tape. Either one side of the wiring layer, a connection portion to the electrode of the semiconductor chip, a through-hole in which a conductive electrode is buried and opened to reach the back surface of the tape in a portion corresponding directly below the connection portion, A conductive protrusion as an external connection terminal provided; an electrode of the semiconductor chip and a wiring layer are electrically connected by through-hole bonding; at least one surface of the insulating tape includes a power supply or A semiconductor device comprising a ground plane layer. 2. A ground electrode of the semiconductor chip is connected to a ground external terminal on the back surface of the tape via a ground plane layer, and the ground external terminal is integrated at a peripheral portion of the insulating tape. The semiconductor device according to claim 1, wherein: 3. A power supply electrode of the semiconductor chip is connected to a power supply external connection terminal on a back surface of the tape via a power supply plane layer, and the power supply external connection terminal is integrated at a central portion of the insulating tape. The semiconductor device according to claim 1, wherein