JPH09231775A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of film fatigue only in one of a pair of reference cells, to reduce the failure rate of a storage device and to improve the reliability of a system by connecting and mounting an inversion circuit to a write circuit. SOLUTION: An inversion circuit DF is installed by connecting data to a pair of reference cells DCt, DCb to a write circuit W, and write data are inverted at every read cycle or at every number of times of arbitrary read-cycles. Accordingly, inversion polarization is not deviated only to one side of a pair of the reference cells, the fatigue of a ferroelectric film can be lowered, the failure of a ferroelectric storage device is reduced, and the reliability of a system is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device.

[0002]

2. Description of the Related Art A ferroelectric memory device is a memory device that utilizes the spontaneous polarization characteristic of a ferroelectric material, does not require a refresh operation, and does not lose stored data even when the power supply voltage drops or the power supply is cut off. It has features.

As a memory cell using a ferroelectric substance, there is a cell composed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor which has been conventionally used in a DRAM (Dynamic Random Access Memory). Although this cell has a small cell area and is suitable for high integration, it requires a reference voltage for amplifying a memory cell signal when reading stored data. In other words, it is necessary to operate the reference cell that generates the reference voltage every read cycle. As a circuit for generating such a reference voltage, there is, for example, one disclosed in Japanese Patent Laid-Open No. 5-242684.

FIG. 16 shows a conventional example. Dt and Db are bit lines, W0 to Wn are word lines, and IOt and IOb are IO lines. The IO line is connected to the bit line via the MOS transistors Yt and Yb to exchange signals with the outside of the chip. The plurality of memory cells MC0 to MCn are arranged at intersections of bit lines and word lines. The capacitors Ht and Hb of the memory cell are capacitors using a ferroelectric material as a dielectric material, and one terminal is connected to the switching transistors St and Sb and the other terminal is connected to the plate line CPL. The reference cells DCt and DCb are also connected in the same manner as the memory cells. The precharge circuit PCC and the sense amplifier SA are connected to the bit line. Further, a circuit W for writing a voltage in the reference cell is connected.

Here, the read operation of the data stored in, for example, MC0 will be described assuming that the data 1 and 0 are the high potential Vcc and the low potential Vss. First, in order to generate a reference voltage on the bit line Db, the signals PCt, PCb, EQ are set to a high potential and the circuit PCC is operated to operate the bit lines Dt, Db.
Is precharged to Vcc / 2. At this time, the potential of the plate RPL connected to the reference cells DCt and DCb is kept at Vcc / 2. After that, PCt, PC
When b and EQ are set to low potential and the word line RW for the reference cell is set to high potential, Mt and Mb become conductive and Dt.
And Ct, and Db and Cb are connected. When RPL is changed to Vcc or Vss in this state, the polarization of the capacitors Ct and Cb using the ferroelectric substance changes by the change of the electric field, and the amount of charges precharged on the bit line also changes according to the change of the polarization. .

By the way, since the potential Vcc corresponding to the data 1 is written in the reference cell DCt and the data 0 is written in the DCb, the difference between the charge amounts generated in Dt and Db is the signal difference between the data 1 and 0. be equivalent to. Therefore, when EQ is set to a high potential, Dt and Db are short-circuited and an intermediate potential of the signal difference between data 1 and 0 appears. This intermediate potential is used as a reference voltage.

The read operation of the memory cell MC0 may be performed only on the bit line Dt as in the above operation. Next, Dt
When the memory cell signal appearing at 1 and the reference voltage of Db are differentially amplified using the sense amplifier SA, the read operation of the data written in the memory cell is completed.

FIG. 17 shows the polarization characteristics of a capacitor using a ferroelectric substance. In FIG. 17, the horizontal axis shows the voltage V, the vertical axis shows the polarization magnitude P, and the solid line shows the polarization characteristics. The polarization characteristic has a hysteresis loop with respect to the voltage V.

The operation of the reference cell will be described with reference to FIG. 17 in comparison with the polarization state of the capacitor. At point A, the plate RPL is kept at Vcc / 2 and the data 1 is V
The state where cc is written and the point B shows the state where data 0 is written. At this time, if the word line has a low potential, the capacitor maintains this polarized state. Next, points C and D are in a state when the word line is selected, Mt and Mb are conductive, and the bit lines Dt and Db are also precharged to Vcc / 2, so the voltage V applied to the capacitor is zero. Become. At this time, point C is a stable polarization state + Pr, and point D is a stable polarization state −Pr.

Point G and point F indicate polarization states when RPL is changed to Vss. Point G is the intersection of straight line J and the hysteresis curve, and point F is the intersection of straight line K and the hysteresis curve. J and K are the values of the bit line capacitance Cd and are straight lines having a negative slope.

Considering the state when RPL is changed from the point C to Vss, it means that the amount of charge stored in the capacitor Ct and the amount of charge stored in Cd change with changes in polarization. A straight line having a slope of Cd moves from the point C to the voltage −Vcc / 2, and the voltage applied to the capacitor Ct at this time has a value indicated by the point G on the straight line. The same applies to point F. The amount of charges read at this time becomes a signal corresponding to data 1 and 0. After that, data is written by the operation of the write circuit W, and the point G returns to the point A and the point F to the point B through the loop of H.

The problem here is the inversion polarization in the ferroelectric body from the point C to the point G. Capacitor C
From t point A to C, t is polarized by a positive voltage,
Inversion polarization is performed between points C and G by a negative voltage. In addition, inversion polarization is also performed in the H loop. This inversion polarization causes fatigue of the ferroelectric film. Also, this phenomenon appears only in data 1 and does not appear in data 0. However,
When the plate is changed to Vcc, it appears only in data 0 and does not appear in data 1. That is, the fatigue of the ferroelectric material has data dependence.

Particularly, when a pair of reference cells are connected to a pair of bit lines, the same reference cell is used for each of a plurality of memory cells every read cycle, so that the film fatigue is more severe than that of the memory cell. This film fatigue causes a failure of the semiconductor memory device and further causes a problem of a system failure.

[0014]

As described above, the reference cell of the ferroelectric memory device in which the memory cell is composed of one MOS transistor and one capacitor has data dependence on the fatigue of the ferroelectric film. There is a problem that the same reference cell causes film fatigue every time depending on the read operation. The problem to be solved by the present invention is to reduce the fatigue of the ferroelectric film of the reference cell. Further, it is to reduce the fatigue of the ferroelectric film, reduce the failure of the ferroelectric memory device, and improve the system reliability.

[0015]

Means for Solving the Problems The above-mentioned problems are caused by inverting complementary data to be written in a pair of reference cells at every read cycle or every arbitrary number of read cycles, and film fatigue of a ferroelectric film having data dependence. It is achieved by eliminating the bias of.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> FIG. 1 shows a first conceptual embodiment of the present invention. A feature of this embodiment is that an inversion circuit is connected to a write circuit for writing data in a reference cell and the write data is inverted every cycle.

The portion surrounded by AR and the reference cells DCt and DCb of this embodiment are the same as those of the conventional example of FIG. 16, except that the write circuit W is changed and an inversion circuit DF is newly provided.

FIG. 2 shows an embodiment of the write circuit. This embodiment is a so-called tri-state buffer in which the PMOS transistor Pt and the NMOS transistor Nt are connected in cascade, and so is Pb and Nb. Also, At, A
b is a NAND circuit, and Rt and Rb are NOR circuits. The output Ot is a node in which the drains of Pt and Nt are shared and is connected to the bit line Dt, and the output Ob is connected to Db.

In this circuit, when It becomes high potential, the NAND circuit and NOR circuit become conductive, At and Rt invert the signal of Qt, and the same signal as the logic of Qt is output to the output Ot. Similarly, Ab and Rb invert the signal of Qb and Q to Ob.
It outputs the same signal as the logic of b. When It becomes low potential, the outputs Ipt and Ipb of the NAND path become high potential and outputs Int and Inb of the NOR circuit become low potential, and the write circuit W
Outputs Ot and Ob become high impedance.

FIG. 3 shows an embodiment of the inverting circuit. In this embodiment, the portion of DF surrounded by the broken line is a D-type flip-flop, and the DF inputs the inverted output Qb to the input terminal Din. Therefore, the output Qt, Qb is inverted. Here, Qt and Qb are complementary signals.

FIG. 4 shows the logic symbol (a) and its circuit (b) used in FIG. The circuit is a clocked inverter using CMOS, and the gate Cn of the NMOS has a low potential P
By setting the gate Cp of the MOS to a high potential, the output O is
When the impedance becomes high and Cn has a high potential and Cp has a low potential, an inverted signal of the input I is output.

FIG. 5 shows a timing chart of the embodiment. For example, the read operation will be described assuming that the data 1 is written in the memory cell MC0. First, PCt,
Dt and Db are Vcc / by the pulse signal of PCb and EQ.
Precharge to 2. Next, when the word line RW for the reference cell is raised and RPL is set to Vss, Dt
The signal voltage of data 1 appears at, and the signal voltage of data 0 appears at Db. Therefore, when EQ is raised, Dt and Db are short-circuited, and the intermediate value of the signal voltages of data 1 and 0, that is, the reference voltage appears. After that, similarly, the above-described operation is performed only on Dt.

Dt is precharged by the pulse of PCt, the word line W0 is raised, and the plate CPL is set to Vss.
When it is lowered to, the signal of data 1 is read. Up to this point, the reference voltage appears at Db and the data 1 signal appears at Dt.
After that, the signal on the bit line is differentially amplified by the sense amplifier drive signals SAP and SAN, and the Ysn signal is raised to output the amplified signal on the bit line to the outside of the chip through the IO line.

After this, the data is written in the reference cell. First, SAP, SAN and RPL are returned to Vcc / 2 and RW is started. Next, the clock It of the inverting circuit
When the signal is raised, the output of the write circuit outputs Vss as the inverted signal Ot of the data of the previous cycle and Vcc as Ob and writes the same in the reference cells DCt and DCb. afterwards,
Writing to the reference cell ends when RW falls.

As described above, since the data written in the reference cell for each read operation is written by a signal obtained by inverting the data written in the previous cycle, the inversion polarization is not biased to only one side of the paired reference cells, and the ferroelectric substance It can reduce membrane fatigue. Further, the failure of the ferroelectric memory device is reduced and the reliability of the system is improved.

<Second Embodiment> FIG. 6 shows another embodiment of the present invention. The feature of this embodiment is that the reference cells DCt, DCb
Is connected to the data line via the MOS transistor. In this embodiment, the part surrounded by AR is the same as the conventional example, and the reference cells DCt and DCb are connected via the MOS transistors CMt and CMb. Mt, Mb
The gate of is connected to RW and makes Mt and Mb conductive or non-conductive by the signal of RW. When writing data to the capacitors Ct and Cb of the reference cell, CMt and CMb
Is turned off to disconnect the bit line and reduce the load on the write circuit.

Since the load of the write circuit can be reduced in this embodiment, there are advantages that data can be written at high speed and power consumption can be reduced.

<Embodiment 3> FIG. 7 shows another embodiment of the present invention. The feature of this embodiment is that the reference cell is newly provided with M
That is, an OS transistor is connected and a common write circuit is connected to a plurality of reference cells. In this embodiment, the portion surrounded by AR is the same as the conventional example, and the reference cells DCt and DCb have MOS transistors Tt and Tb.
Connect the drain terminal of. There are a plurality of array parts including AR, DCt, and DCb, which are denoted by B0 to Bn. Tt, Tb
The source terminal of is connected to the common write lines Wt and Wb. The gates of Tt and Tb are connected to WD to make Tt and Tb conductive or non-conductive by the signal of WD. The output of the write circuit W output to Ot and Ob is the same as that of the above-described embodiment, and the data is inverted every cycle of the clock input to It.

In this embodiment, the common write circuit is provided for a plurality of reference cells, so that there is an advantage that the layout area can be reduced and further the chip area can be reduced.

<Embodiment 4> FIG. 8 shows another embodiment of the present invention. The feature of this embodiment is that an inverter is used in the writing circuit. In this embodiment, a plurality of arrays B0-B
n is the same as in the above-mentioned embodiment, and the MOS transistor T
By using t and Tb, the write circuit W does not need a high impedance state, and an inverter is used instead of the tristate buffer.

The present embodiment has an advantage that the layout area can be reduced and the power consumption can be reduced by reducing the number of logic elements.

<Embodiment 5> FIG. 9 shows another embodiment of the present invention. The feature of this embodiment is that the memory cell array including the reference cell shown in FIG. 1 is symmetrically arranged around the write circuit, and the bit lines are connected to each other through the transistors. In this embodiment, the portion surrounded by AR is the same as the conventional one, and the circuit WC0 including the write circuit W and the inverting circuit DF is the same as WC0 in FIG.

The reference cell DCTt is connected to the bit line DtL of the left array, and the reference cell DCTb is MOS.
It is connected to the bit line DtR of the right array that faces the transistor Et across it. Similarly, DCBb is on the bit line DbL, and DCBt is D on both sides of the MOS transistor Eb.
Connect to bR respectively. That is, DCTt and DCTb, D
CBt and DCBb form a pair of reference cells.

For example, in the case of performing the read operation of the memory cell connected to the bit line DbL in this embodiment, it is necessary to generate the reference voltage at DtL. For DCTt and DCTb, complementary data is written in advance by a write circuit, and if the word line RWt for the reference cell is set to a high potential and the potential of the plate RPt is changed as in the conventional case, the bit lines DtL and DtR become 1. A signal of 0 is generated. Next, EQt is set to a high potential, and the MOS transistor Et
If DtL and DtR are short-circuited, the signal 1,0
Intermediate potential, that is, a reference voltage is generated.

In this embodiment, when the reference voltage is generated,
Since the bit line connected to the memory cell is not used, the memory cell signal and the reference voltage can be read at the same time, and there is an advantage that the data read time can be shortened.

<Embodiment 6> FIG. 10 shows another embodiment of the present invention. The feature of this embodiment is that a counter circuit is provided in the embodiment shown in FIG. 1 and an output Ic of the counter circuit is converted into an inverting circuit DF.
That is what I entered. This is to invert the data to be written in the reference cell every arbitrary number of times of reading.

In this embodiment, the count value is incremented by one for each read cycle, and it is determined whether the set read cycle number and the count value match, and a one-shot pulse is output to Ic. As described above, the present embodiment has an advantage that the designer or the user can freely set the data inversion timing.

FIG. 11 shows an embodiment of the counter circuit. This circuit is roughly divided into three parts. A count circuit CC that counts the read cycle, a determination circuit DR that determines whether the set read cycle number and the count value match, and an output circuit OC that converts the signal output by the match of the count value into a one-shot pulse.

The count circuit CC is a circuit in which flip-flops FF0 to FFn that output one cycle of an input signal in a half cycle are connected in a chain. The least significant bit represented by the binary system is a signal Tr that outputs one cycle for each read cycle, and thereafter, the count value is sequentially output up to the output signal Cn of the most significant bit FFn.

The judgment circuit DR is composed of a circuit PF for setting the number of read cycles, EN0 to ENn for judging whether the set value and the count value match, and a NAND circuit. P
F is a register circuit or ROM (Read Onl
y Memory), EN0 to ENn are exclusive (E
xclucive) NOR circuit is used. EN0 to ENn output High level signals to the outputs E0 to En when the set value and the count value match. The NAND circuit NA inputs the signal and outputs a low level.

The output circuit OC comprises a delay circuit DL and a NOR circuit NR. The output O1 of NA and the output O2 of the delay circuit DL are inputs of the NOR circuit NR, and O1 and O2 are Lo.
When it becomes w level, the output It outputs High level.

FIG. 12 shows an embodiment of the flip-flop circuit. This circuit is a half frequency divider circuit, and the input signal Cn
The output signal Cn + 1 is output in a half cycle for each cycle.

FIG. 13 shows a timing chart of the counter circuit. In the figure, the low level and the high level of the voltage correspond to 0 and 1 of the binary system.

An example in which the read cycle value is set to 1000 will be described. First, a one-shot pulse that once rises to a high level is input to Rst. The outputs C0 to C3 of the counter circuit are count values of the least significant bit to the most significant bit, and all outputs are set to low level.
Next, the signal Tr that outputs one cycle for each read cycle is input to the counter circuit. Counter circuit outputs C0 to C
3 repeats 0 and 1 according to the binary count value. PF
The values set in step D0 to D3 are the least significant bit to the most significant bit. That is, in the value 1000, only D3 is at the high level and the others are at the low level. E0 to E3 are EN0
~ ENn are output, and E0 to E2 are signals obtained by inverting C0 to C2. O1 is the output of NA, E0 to E3
When all become high level, low level is output. O2
The delay circuit DL outputs a high level with a slight delay after the change of O1. O1 and O during this delayed time td
Both 2 are at a low level, the NOR circuit NR outputs a high level to the output Ic, and the instant Ic when O2 becomes a high level falls to a low level and outputs a one-shot signal.

As described above, the data inversion signal is output for each set value of the number of read cycles, and the inverted data is written in the reference cell.

<Embodiment 7> FIG. 14 shows another embodiment of the present invention. FIG. 14 is an embodiment in which a plurality of reference cell pairs are connected to the first conceptual embodiment shown in FIG. 1, and a decoder DC for selecting the word line of the reference cell is provided, and other than that is the same as FIG. is there. There are many ways to select a reference cell. For example, there are a method of changing every cycle, a method of changing every several cycles, and a method of changing every set time. In any case, it may be selected so that the ferroelectric films of the plurality of reference cells are uniformly deteriorated.

The present embodiment has an advantage of further reducing the deterioration of the ferroelectric film by connecting a plurality of reference cell pairs.

<Embodiment 8> FIG. 15 shows another embodiment of the present invention. This embodiment is an example in which a counter circuit is provided in the example of FIG. 14, and is an example in which data to be written is inverted every arbitrary read cycle while using a plurality of reference cells.

In this embodiment, there is an advantage that the deterioration of the ferroelectric film can be reduced by using a plurality of reference cells and the data inversion timing can be set to an arbitrary read cycle number value.

[0050]

By inverting the data to be written in the reference cell, the film fatigue generated in one of the reference cells to be paired can be reduced, so that the failure rate of the ferroelectric memory device can be reduced and the system reliability can be improved. Can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a write circuit according to a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of an inverting circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of logic symbols and circuits used in the inverting circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 6 is a circuit diagram of a main part of a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part of a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a main part of a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of a main part of a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of a main part of a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram showing an example of a counter circuit according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing an example of a flip-flop used in a counter circuit according to a sixth embodiment of the present invention.

FIG. 13 is a timing chart of the counter circuit according to the sixth embodiment of the present invention.

FIG. 14 is a circuit diagram of a seventh embodiment of the present invention.

FIG. 15 is a circuit diagram of an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram of a conventional semiconductor memory device.

FIG. 17 is an explanatory diagram showing a relationship between voltage and polarization of a ferroelectric capacitor.

[Explanation of symbols]

Dt, Db ... Bit line, IOt, IOb ... I / O line, P
CC: precharge circuit, SA: sense amplifier, MC0
-MCn ... Memory cell, DCt, DCb ... Reference cell, W ... Reference cell write circuit, DF ... Inversion circuit, SAN, SAP ... Sense amplifier drive signal line, P
Ct, PCb ... Precharge circuit drive signal line, SAN,
SAP ... Sense amplifier drive signal line, EQ ... Equalize drive signal line, RW ... Reference cell word line, CPL
... Plate line, RPL ... Reference cell plate line, It ... Inversion circuit clock line, Vcc / 2 ... Power supply voltage intermediate voltage line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Tanaka 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Ken Sakata Kokubunji, Tokyo 1-280, Higashi Koigakubo, Higashi, Ltd. In the Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Katsutaka Kimura 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A semiconductor memory device having a sense amplifier circuit for detecting and amplifying a potential change of a bit line pair caused by a memory cell, wherein the memory cell has a structure in which a ferroelectric substance is sandwiched between electrodes of a capacitor. A reference cell in which a charge transfer transistor is connected between one electrode of a dielectric capacitor and a bit line, and a reference potential is generated in the other bit line paired with the bit line in which the potential change is caused by the data in the memory cell. Is composed of a ferroelectric capacitor having the same structure as the memory cell and the charge transfer transistor, and the reference potential is generated using a reference cell in which data 1 is written and a reference cell in which data 0 is written, and the data is A ferroelectric memory device characterized by inverting and writing every read cycle. 2. The charge transfer transistor of the reference cell is connected to an output line of a write circuit that outputs the data, and the output line is connected to a bit line of a memory cell array including a sense amplifier. A ferroelectric memory device in which a transistor is non-conducting when data is written to the reference cell, the transistor being electrically connected via a transistor. 3. The write transistor according to claim 1, wherein a write transistor having a drain or source terminal of the transistor connected between the ferroelectric capacitor of the reference cell and the charge transfer transistor is provided, and the output line is written to the write transistor. Ferroelectric memory device connected to the other end of the transistor. 4. The memory cell array according to claim 1, wherein two memory cell arrays including a sense amplifier and the reference cell are arranged,
A bit line connecting transistor for connecting bit lines between the memory cell arrays is provided, and when amplifying a signal from the memory cell, the reference potential thereof is arranged and connected across the bit line connecting transistor. A ferroelectric memory device generated by using one of the reference cells. 5. The ferroelectric memory device according to claim 1, wherein the data written in the reference cell is inverted every arbitrary number of read cycles. 6. The ferroelectric memory device according to claim 1, wherein a plurality of the reference cell pairs are connected to a bit line, and a reference cell pair selected in each read cycle is changed. 7. The ferroelectric memory device according to claim 6, wherein the data written in the reference cell is inverted every arbitrary number of read cycles. 8. A ferroelectric memory device according to claim 5, wherein a counter circuit for counting the number of read cycles is provided in the ferroelectric memory device.